1;; Generic DFA-based pipeline description for LoongArch targets 2;; Copyright (C) 2021-2022 Free Software Foundation, Inc. 3;; Contributed by Loongson Ltd. 4;; Based on MIPS target for GNU compiler. 5 6;; This file is part of GCC. 7 8;; GCC is free software; you can redistribute it and/or modify it 9;; under the terms of the GNU General Public License as published 10;; by the Free Software Foundation; either version 3, or (at your 11;; option) any later version. 12 13;; GCC is distributed in the hope that it will be useful, but WITHOUT 14;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16;; License for more details. 17 18;; You should have received a copy of the GNU General Public License 19;; along with GCC; see the file COPYING3. If not see 20;; <http://www.gnu.org/licenses/>. 21 22(define_automaton "alu,imuldiv") 23 24(define_cpu_unit "alu" "alu") 25(define_cpu_unit "imuldiv" "imuldiv") 26 27;; Ghost instructions produce no real code. 28;; They exist purely to express an effect on dataflow. 29(define_insn_reservation "ghost" 0 30 (eq_attr "type" "ghost") 31 "nothing") 32 33(define_insn_reservation "generic_alu" 1 34 (eq_attr "type" "unknown,prefetch,prefetchx,condmove,const,arith, 35 shift,slt,clz,trap,multi,nop,logical,signext,move") 36 "alu") 37 38(define_insn_reservation "generic_load" 3 39 (eq_attr "type" "load,fpload,fpidxload") 40 "alu") 41 42(define_insn_reservation "generic_store" 1 43 (eq_attr "type" "store,fpstore,fpidxstore") 44 "alu") 45 46(define_insn_reservation "generic_xfer" 2 47 (eq_attr "type" "mftg,mgtf") 48 "alu") 49 50(define_insn_reservation "generic_branch" 1 51 (eq_attr "type" "branch,jump,call") 52 "alu") 53 54(define_insn_reservation "generic_imul" 17 55 (eq_attr "type" "imul") 56 "imuldiv*17") 57 58(define_insn_reservation "generic_fcvt" 1 59 (eq_attr "type" "fcvt") 60 "alu") 61 62(define_insn_reservation "generic_fmove" 2 63 (eq_attr "type" "fabs,fneg,fmove") 64 "alu") 65 66(define_insn_reservation "generic_fcmp" 3 67 (eq_attr "type" "fcmp") 68 "alu") 69 70(define_insn_reservation "generic_fadd" 4 71 (eq_attr "type" "fadd") 72 "alu") 73 74(define_insn_reservation "generic_fmul_single" 7 75 (and (eq_attr "type" "fmul,fmadd") 76 (eq_attr "mode" "SF")) 77 "alu") 78 79(define_insn_reservation "generic_fmul_double" 8 80 (and (eq_attr "type" "fmul,fmadd") 81 (eq_attr "mode" "DF")) 82 "alu") 83 84(define_insn_reservation "generic_fdiv_single" 23 85 (and (eq_attr "type" "fdiv,frdiv") 86 (eq_attr "mode" "SF")) 87 "alu") 88 89(define_insn_reservation "generic_fdiv_double" 36 90 (and (eq_attr "type" "fdiv,frdiv") 91 (eq_attr "mode" "DF")) 92 "alu") 93 94(define_insn_reservation "generic_fsqrt_single" 54 95 (and (eq_attr "type" "fsqrt,frsqrt") 96 (eq_attr "mode" "SF")) 97 "alu") 98 99(define_insn_reservation "generic_fsqrt_double" 112 100 (and (eq_attr "type" "fsqrt,frsqrt") 101 (eq_attr "mode" "DF")) 102 "alu") 103 104(define_insn_reservation "generic_atomic" 10 105 (eq_attr "type" "atomic") 106 "alu") 107 108;; Sync loop consists of (in order) 109;; (1) optional sync, 110;; (2) LL instruction, 111;; (3) branch and 1-2 ALU instructions, 112;; (4) SC instruction, 113;; (5) branch and ALU instruction. 114;; The net result of this reservation is a big delay with a flush of 115;; ALU pipeline. 116(define_insn_reservation "generic_sync_loop" 40 117 (eq_attr "type" "syncloop") 118 "alu*39") 119