1;; Constraint definitions for LoongArch. 2;; Copyright (C) 2021-2022 Free Software Foundation, Inc. 3;; Contributed by Loongson Ltd. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify 8;; it under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, 13;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15;; GNU General Public License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21;; Register constraints 22 23;; "a" "A constant call global and noplt address." 24;; "b" <-----unused 25;; "c" "A constant call local address." 26;; "d" <-----unused 27;; "e" JIRL_REGS 28;; "f" FP_REGS 29;; "g" <-----unused 30;; "h" "A constant call plt address." 31;; "i" "Matches a general integer constant." (Global non-architectural) 32;; "j" SIBCALL_REGS 33;; "k" "A memory operand whose address is formed by a base register and 34;; (optionally scaled) index register." 35;; "l" "A signed 16-bit constant." 36;; "m" "A memory operand whose address is formed by a base register and offset 37;; that is suitable for use in instructions with the same addressing mode 38;; as @code{st.w} and @code{ld.w}." 39;; "n" "Matches a non-symbolic integer constant." (Global non-architectural) 40;; "o" "Matches an offsettable memory reference." (Global non-architectural) 41;; "p" "Matches a general address." (Global non-architectural) 42;; "q" CSR_REGS 43;; "r" GENERAL_REGS (Global non-architectural) 44;; "s" "Matches a symbolic integer constant." (Global non-architectural) 45;; "t" "A constant call weak address" 46;; "u" "A signed 52bit constant and low 32-bit is zero (for logic instructions)" 47;; "v" "A signed 64-bit constant and low 44-bit is zero (for logic instructions)." 48;; "w" "Matches any valid memory." 49;; "x" <-----unused 50;; "y" <-----unused 51;; "z" FCC_REGS 52;; "A" <-----unused 53;; "B" <-----unused 54;; "C" <-----unused 55;; "D" <-----unused 56;; "E" "Matches a floating-point constant." (Global non-architectural) 57;; "F" "Matches a floating-point constant." (Global non-architectural) 58;; "G" "Floating-point zero." 59;; "H" <-----unused 60;; "I" "A signed 12-bit constant (for arithmetic instructions)." 61;; "J" "Integer zero." 62;; "K" "An unsigned 12-bit constant (for logic instructions)." 63;; "L" <-----unused 64;; "M" <-----unused 65;; "N" <-----unused 66;; "O" <-----unused 67;; "P" <-----unused 68;; "Q" <-----unused 69;; "R" <-----unused 70;; "S" <-----unused 71;; "T" <-----unused 72;; "U" <-----unused 73;; "V" "Matches a non-offsettable memory reference." (Global non-architectural) 74;; "W" <-----unused 75;; "X" "Matches anything." (Global non-architectural) 76;; "Y" - 77;; "Yd" 78;; "A constant @code{move_operand} that can be safely loaded using 79;; @code{la}." 80;; "Yx" 81;; "Z" - 82;; "ZC" 83;; "A memory operand whose address is formed by a base register and offset 84;; that is suitable for use in instructions with the same addressing mode 85;; as @code{ll.w} and @code{sc.w}." 86;; "ZB" 87;; "An address that is held in a general-purpose register. 88;; The offset is zero" 89;; "<" "Matches a pre-dec or post-dec operand." (Global non-architectural) 90;; ">" "Matches a pre-inc or post-inc operand." (Global non-architectural) 91 92(define_constraint "a" 93 "@internal 94 A constant call global and noplt address." 95 (match_operand 0 "is_const_call_global_noplt_symbol")) 96 97(define_constraint "c" 98 "@internal 99 A constant call local address." 100 (match_operand 0 "is_const_call_local_symbol")) 101 102(define_register_constraint "e" "JIRL_REGS" 103 "@internal") 104 105(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS" 106 "A floating-point register (if available).") 107 108(define_constraint "h" 109 "@internal 110 A constant call plt address." 111 (match_operand 0 "is_const_call_plt_symbol")) 112 113(define_register_constraint "j" "SIBCALL_REGS" 114 "@internal") 115 116(define_memory_constraint "k" 117 "A memory operand whose address is formed by a base register and (optionally scaled) 118 index register." 119 (and (match_code "mem") 120 (match_test "loongarch_base_index_address_p (XEXP (op, 0), mode)"))) 121 122(define_constraint "l" 123"A signed 16-bit constant." 124(and (match_code "const_int") 125 (match_test "IMM16_OPERAND (ival)"))) 126 127(define_memory_constraint "m" 128 "A memory operand whose address is formed by a base register and offset 129 that is suitable for use in instructions with the same addressing mode 130 as @code{st.w} and @code{ld.w}." 131 (and (match_code "mem") 132 (match_test "loongarch_12bit_offset_address_p (XEXP (op, 0), mode)"))) 133 134(define_register_constraint "q" "CSR_REGS" 135 "A general-purpose register except for $r0 and $r1 for lcsr.") 136 137(define_constraint "t" 138 "@internal 139 A constant call weak address." 140 (match_operand 0 "is_const_call_weak_symbol")) 141 142(define_constraint "u" 143 "A signed 52bit constant and low 32-bit is zero (for logic instructions)." 144 (and (match_code "const_int") 145 (match_test "LU32I_OPERAND (ival)"))) 146 147(define_constraint "v" 148 "A signed 64-bit constant and low 44-bit is zero (for logic instructions)." 149 (and (match_code "const_int") 150 (match_test "LU52I_OPERAND (ival)"))) 151 152(define_register_constraint "z" "FCC_REGS" 153 "A floating-point condition code register.") 154 155;; Floating-point constraints 156 157(define_constraint "G" 158 "Floating-point zero." 159 (and (match_code "const_double") 160 (match_test "op == CONST0_RTX (mode)"))) 161 162;; Integer constraints 163 164(define_constraint "I" 165 "A signed 12-bit constant (for arithmetic instructions)." 166 (and (match_code "const_int") 167 (match_test "IMM12_OPERAND (ival)"))) 168 169(define_constraint "J" 170 "Integer zero." 171 (and (match_code "const_int") 172 (match_test "ival == 0"))) 173 174(define_constraint "K" 175 "An unsigned 12-bit constant (for logic instructions)." 176 (and (match_code "const_int") 177 (match_test "IMM12_OPERAND_UNSIGNED (ival)"))) 178 179(define_constraint "Yd" 180 "@internal 181 A constant @code{move_operand} that can be safely loaded using 182 @code{la}." 183 (and (match_operand 0 "move_operand") 184 (match_test "CONSTANT_P (op)"))) 185 186(define_constraint "Yx" 187 "@internal" 188 (match_operand 0 "low_bitmask_operand")) 189 190(define_memory_constraint "ZC" 191 "A memory operand whose address is formed by a base register and offset 192 that is suitable for use in instructions with the same addressing mode 193 as @code{ll.w} and @code{sc.w}." 194 (and (match_code "mem") 195 (match_test "loongarch_14bit_shifted_offset_address_p (XEXP (op, 0), mode)"))) 196 197(define_memory_constraint "ZB" 198 "@internal 199 An address that is held in a general-purpose register. 200 The offset is zero" 201 (and (match_code "mem") 202 (match_test "REG_P (XEXP (op, 0))"))) 203