1 /* $NetBSD: clk_10_0_2_sh_mask.h,v 1.2 2021/12/18 23:45:09 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _clk_10_0_2_SH_MASK_HEADER 24 #define _clk_10_0_2_SH_MASK_HEADER 25 26 27 // addressBlock: clk_clk1_0_SmuClkDec 28 //CLK1_CLK_PLL_REQ 29 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0 30 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc 31 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10 32 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL 33 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L 34 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L 35 //CLK1_CLK0_BYPASS_CNTL 36 #define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT 0x0 37 #define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV__SHIFT 0x10 38 #define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK 0x00000007L 39 #define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV_MASK 0x000F0000L 40 //CLK1_CLK1_BYPASS_CNTL 41 #define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT 0x0 42 #define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV__SHIFT 0x10 43 #define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK 0x00000007L 44 #define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV_MASK 0x000F0000L 45 //CLK1_CLK2_BYPASS_CNTL 46 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT 0x0 47 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT 0x10 48 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L 49 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK 0x000F0000L 50 //CLK1_CLK3_DS_CNTL 51 #define CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT 0x0 52 #define CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK 0x00000007L 53 //CLK1_CLK3_ALLOW_DS 54 #define CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS__SHIFT 0x0 55 #define CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS_MASK 0x00000001L 56 //CLK1_CLK3_BYPASS_CNTL 57 #define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT 0x0 58 #define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV__SHIFT 0x10 59 #define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK 0x00000007L 60 #define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV_MASK 0x000F0000L 61 //CLK1_CLK0_CURRENT_CNT 62 #define CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0 63 #define CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL 64 //CLK1_CLK1_CURRENT_CNT 65 #define CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0 66 #define CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL 67 //CLK1_CLK2_CURRENT_CNT 68 #define CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0 69 #define CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL 70 //CLK1_CLK3_CURRENT_CNT 71 #define CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0 72 #define CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL 73 74 75 #endif 76