1 /* $NetBSD: clk_10_0_2_offset.h,v 1.2 2021/12/18 23:45:09 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _clk_10_0_2_OFFSET_HEADER 24 #define _clk_10_0_2_OFFSET_HEADER 25 26 27 28 // addressBlock: clk_clk1_0_SmuClkDec 29 // base address: 0x5b800 30 #define mmCLK1_CLK_PLL_REQ 0x000f 31 #define mmCLK1_CLK_PLL_REQ_BASE_IDX 1 32 #define mmCLK1_CLK0_BYPASS_CNTL 0x0049 33 #define mmCLK1_CLK0_BYPASS_CNTL_BASE_IDX 1 34 #define mmCLK1_CLK1_BYPASS_CNTL 0x0053 35 #define mmCLK1_CLK1_BYPASS_CNTL_BASE_IDX 1 36 #define mmCLK1_CLK2_BYPASS_CNTL 0x005d 37 #define mmCLK1_CLK2_BYPASS_CNTL_BASE_IDX 1 38 #define mmCLK1_CLK2_STATUS 0x005e 39 #define mmCLK1_CLK2_STATUS_BASE_IDX 1 40 #define mmCLK1_CLK3_DFS_CNTL 0x005f 41 #define mmCLK1_CLK3_DFS_CNTL_BASE_IDX 1 42 #define mmCLK1_CLK3_DS_CNTL 0x0060 43 #define mmCLK1_CLK3_DS_CNTL_BASE_IDX 1 44 #define mmCLK1_CLK3_ALLOW_DS 0x0061 45 #define mmCLK1_CLK3_ALLOW_DS_BASE_IDX 1 46 #define mmCLK1_CLK3_BYPASS_CNTL 0x0067 47 #define mmCLK1_CLK3_BYPASS_CNTL_BASE_IDX 1 48 #define mmCLK1_CLK0_CURRENT_CNT 0x008a 49 #define mmCLK1_CLK0_CURRENT_CNT_BASE_IDX 1 50 #define mmCLK1_CLK1_CURRENT_CNT 0x008b 51 #define mmCLK1_CLK1_CURRENT_CNT_BASE_IDX 1 52 #define mmCLK1_CLK2_CURRENT_CNT 0x008c 53 #define mmCLK1_CLK2_CURRENT_CNT_BASE_IDX 1 54 #define mmCLK1_CLK3_CURRENT_CNT 0x008d 55 #define mmCLK1_CLK3_CURRENT_CNT_BASE_IDX 1 56 57 58 #endif 59