xref: /dpdk/drivers/net/bnxt/bnxt_filter.h (revision 6d160d770974ff1e212dd8a18646b15823256240)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2014-2023 Broadcom
3  * All rights reserved.
4  */
5 
6 #ifndef _BNXT_FILTER_H_
7 #define _BNXT_FILTER_H_
8 
9 #include <rte_ether.h>
10 
11 #define bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)	\
12 		(((filter)->enables & (chk)) &&			\
13 		 ((filter)->l2_ivlan == (vlan_id) &&		\
14 		  (filter)->l2_ivlan_mask == 0x0FFF) &&		\
15 		 !memcmp((filter)->l2_addr, (bp)->mac_addr,	\
16 			 RTE_ETHER_ADDR_LEN))
17 struct bnxt;
18 
19 #define BNXT_FLOW_L2_VALID_FLAG			BIT(0)
20 #define BNXT_FLOW_L2_SRC_VALID_FLAG		BIT(1)
21 #define BNXT_FLOW_L2_INNER_SRC_VALID_FLAG	BIT(2)
22 #define BNXT_FLOW_L2_DST_VALID_FLAG		BIT(3)
23 #define BNXT_FLOW_L2_INNER_DST_VALID_FLAG	BIT(4)
24 #define BNXT_FLOW_L2_DROP_FLAG			BIT(5)
25 #define BNXT_FLOW_PARSE_INNER_FLAG		BIT(6)
26 #define BNXT_FLOW_MARK_FLAG			BIT(7)
27 
28 struct bnxt_flow_stats {
29 	uint64_t	packets;
30 	uint64_t	bytes;
31 };
32 
33 struct bnxt_filter_info {
34 	STAILQ_ENTRY(bnxt_filter_info)	next;
35 	uint32_t		flow_id;
36 	uint64_t		fw_l2_filter_id;
37 	struct bnxt_filter_info *matching_l2_fltr_ptr;
38 	uint64_t		fw_em_filter_id;
39 	uint64_t		fw_ntuple_filter_id;
40 #define INVALID_MAC_INDEX	((uint16_t)-1)
41 	uint16_t		mac_index;
42 #define HWRM_CFA_L2_FILTER	0
43 #define HWRM_CFA_EM_FILTER	1
44 #define HWRM_CFA_NTUPLE_FILTER	2
45 #define HWRM_CFA_TUNNEL_REDIRECT_FILTER	3
46 #define HWRM_CFA_CONFIG		4
47 	uint8_t                 filter_type;
48 	uint32_t                dst_id;
49 
50 	/* Filter Characteristics */
51 	uint32_t		flags;
52 	uint32_t		enables;
53 	uint32_t		l2_ref_cnt;
54 	uint8_t			l2_addr[RTE_ETHER_ADDR_LEN];
55 	uint8_t			l2_addr_mask[RTE_ETHER_ADDR_LEN];
56 	uint32_t		valid_flags;
57 	uint16_t		l2_ovlan;
58 	uint16_t		l2_ovlan_mask;
59 	uint16_t		l2_ivlan;
60 	uint16_t		l2_ivlan_mask;
61 	uint8_t			t_l2_addr[RTE_ETHER_ADDR_LEN];
62 	uint8_t			t_l2_addr_mask[RTE_ETHER_ADDR_LEN];
63 	uint16_t		t_l2_ovlan;
64 	uint16_t		t_l2_ovlan_mask;
65 	uint16_t		t_l2_ivlan;
66 	uint16_t		t_l2_ivlan_mask;
67 	uint8_t			tunnel_type;
68 	uint16_t		mirror_vnic_id;
69 	uint32_t		vni;
70 	uint8_t			pri_hint;
71 	uint64_t		l2_filter_id_hint;
72 	uint32_t		src_id;
73 	uint8_t			src_type;
74 	uint8_t                 src_macaddr[6];
75 	uint8_t                 dst_macaddr[6];
76 	uint32_t                dst_ipaddr[4];
77 	uint32_t                dst_ipaddr_mask[4];
78 	uint32_t                src_ipaddr[4];
79 	uint32_t                src_ipaddr_mask[4];
80 	uint16_t                dst_port;
81 	uint16_t                dst_port_mask;
82 	uint16_t                src_port;
83 	uint16_t                src_port_mask;
84 	uint16_t                ip_protocol;
85 	uint16_t                ip_addr_type;
86 	uint16_t                ethertype;
87 	uint32_t		priority;
88 	/* Backptr to vnic. As of now, used only by an L2 filter
89 	 * to remember which vnic it was created on
90 	 */
91 	struct			bnxt_vnic_info *vnic;
92 	uint32_t		mark;
93 	struct bnxt_flow_stats	hw_stats;
94 };
95 
96 struct bnxt_filter_info *bnxt_alloc_filter(struct bnxt *bp);
97 struct bnxt_filter_info *bnxt_alloc_vf_filter(struct bnxt *bp, uint16_t vf);
98 void bnxt_free_all_filters(struct bnxt *bp);
99 void bnxt_free_filter_mem(struct bnxt *bp);
100 int bnxt_alloc_filter_mem(struct bnxt *bp);
101 struct bnxt_filter_info *bnxt_get_unused_filter(struct bnxt *bp);
102 void bnxt_free_filter(struct bnxt *bp, struct bnxt_filter_info *filter);
103 struct bnxt_filter_info *bnxt_get_l2_filter(struct bnxt *bp,
104 		struct bnxt_filter_info *nf, struct bnxt_vnic_info *vnic);
105 
106 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_MACADDR	\
107 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR
108 #define EM_FLOW_ALLOC_INPUT_EN_SRC_MACADDR	\
109 	HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR
110 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR	\
111 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR
112 #define EM_FLOW_ALLOC_INPUT_EN_DST_MACADDR	\
113 	HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR
114 #define NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE   \
115 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE
116 #define EM_FLOW_ALLOC_INPUT_EN_ETHERTYPE       \
117 	HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE
118 #define EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID       \
119 	HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID
120 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR  \
121 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR
122 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK     \
123 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK
124 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR  \
125 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR
126 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK     \
127 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK
128 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT    \
129 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT
130 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK       \
131 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK
132 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT    \
133 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT
134 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK       \
135 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK
136 #define NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO	\
137 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL
138 #define EM_FLOW_ALLOC_INPUT_EN_SRC_IPADDR	\
139 	HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR
140 #define EM_FLOW_ALLOC_INPUT_EN_DST_IPADDR	\
141 	HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR
142 #define EM_FLOW_ALLOC_INPUT_EN_SRC_PORT	\
143 	HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT
144 #define EM_FLOW_ALLOC_INPUT_EN_DST_PORT	\
145 	HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT
146 #define EM_FLOW_ALLOC_INPUT_EN_IP_PROTO	\
147 	HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL
148 #define EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6	\
149 	HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
150 #define NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6	\
151 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
152 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN	\
153 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN
154 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE	\
155 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE
156 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE  \
157 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE
158 #define L2_FILTER_ALLOC_INPUT_EN_L2_ADDR_MASK	\
159 	HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK
160 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_UDP	\
161 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
162 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_TCP	\
163 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP
164 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN	\
165 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN
166 #define NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4	\
167 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4
168 #define NTUPLE_FLTR_ALLOC_INPUT_EN_MIRROR_VNIC_ID	\
169 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID
170 #define NTUPLE_FLTR_ALLOC_INPUT_EN_MIRROR_VNIC_ID	\
171 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID
172 #define L2_FILTER_ALLOC_INPUT_EN_T_NUM_VLANS \
173 	HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS
174 #define L2_FILTER_ALLOC_INPUT_EN_NUM_VLANS \
175 	HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS
176 #define CFA_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
177 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4
178 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE	\
179 	HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE
180 #endif
181