xref: /plan9/sys/src/9/ppc/blast.h (revision 5d9de2d38d2503efca29e12e0e32036368a7a75f)
1 /*
2  * Here, we define everything that is specific for the blast board from Crawford Hill
3  */
4 
5 
6 /* Clock speed of the blast board */
7 #define	CLKIN	72000000
8 
9 /*
10  * Blast memory layout:
11  *	CS0: FE000000 -> FFFFFFFF (Flash)
12  *	CS1: FC000000 -> FCFFFFFF (DSP hpi)
13  *	CS2: 00000000 -> 03FFFFFF (60x sdram)
14  *	CS3: 04000000 -> 04FFFFFF (FPGA)
15  *	CS4: 05000000 -> 06FFFFFF (local bus sdram)
16  *	CS5: 07000000 -> 070FFFFF (eeprom - not populated)
17  *	CS6: E0000000 -> E0FFFFFF (FPGA)
18  *
19  * Main Board memory lay out:
20  *	CS0: FE000000 -> FEFFFFFF (16 M FLASH)
21  *	CS1: FC000000 -> FCFFFFFF (16 M DSP1)
22  *	CS2: 00000000 -> 03FFFFFF (64 M SDRAM)
23  *	CS3: 04000000 -> 04FFFFFF (16M DSP2)
24  *	CS4: 05000000 -> 06FFFFFF (32 M Local SDRAM)
25  *	CS5: 07000000 -> 070FFFFF (eeprom - not populated)
26  *	CS6: E0000000 -> E0FFFFFF (16 M FPGA)
27  *
28  *	CS2, CS3, CS4, (and CS5) are covered by DBAT 0,  CS0 and CS1 by DBAT 3, CS6 by DBAT 2
29  */
30 #define	IMMR		0xf0000000
31 
32 #define	FLASHMEM	0xfe000000
33 #define	FLASHSIZE	0x01000000
34 #define	DSP1BASE		0xfc000000
35 #define	DSP1SIZE		0x01000000
36 #define	MEM1BASE	0x00000000
37 #define	MEM1SIZE	0x04000000
38 #define	DSP2BASE		0x04000000
39 #define	DSP2SIZE		0x01000000
40 #define	MEM2BASE	0x05000000
41 /* #define	MEM2SIZE	0x02000000 */
42 #define	MEM2SIZE	0
43 #define	FPGABASE		0xe0000000
44 #define	FPGASIZE		0x01000000
45 
46 #define	PLAN9INI		0x00460000
47 
48 #define	TLBENTRIES	32
49 /*
50  *  PTE bits for fault.c.  These belong to the second PTE word.  Validity is
51  *  implied for putmmu(), and we always set PTE0_V.  PTEVALID is used
52  *  here to set cache policy bits on a global basis.
53  */
54 #define	PTEVALID		PTE1_M
55 #define	PTEWRITE		(PTE1_RW|PTE1_C)
56 #define	PTERONLY	PTE1_RO
57 #define	PTEUNCACHED	PTE1_I
58 
59 /* SMC Uart configuration */
60 #define	SMC1PORT	3	/* Port D */
61 #define	SMTXD1		BIT(9)
62 #define	SMRXD1		BIT(8)
63 
64 /* Ethernet FCC configuration */
65 #define	A1txer	 	0x00000004
66 #define	A1rxdv	 	0x00000010
67 #define	A1txen		 0x00000008
68 #define	A1rxer		 0x00000020
69 #define	A1col		 0x00000001
70 #define	A1crs		 0x00000002
71 #define	A1txdat		 0x00003c00
72 #define	A1rxdat		 0x0003c000
73 #define	B2txer		 0x00000001
74 #define	B2rxdv		 0x00000002
75 #define	B2txen		 0x00000004
76 #define	B2rxer		 0x00000008
77 #define	B2col		 0x00000010
78 #define	B2crs		 0x00000020
79 #define	B2txdat		 0x000003c0
80 #define	B2rxdat		 0x00003c00
81 #define	B3rxdv		 0x00004000
82 #define	B3rxer		 0x00008000
83 #define	B3txer		 0x00010000
84 #define	B3txen		 0x00020000
85 #define	B3col		 0x00040000
86 #define	B3crs		 0x00080000
87 #define	B3txdat		 0x0f000000
88 #define	B3rxdat		 0x00f00000
89 
90 #define	A1psor0		 (A1rxdat | A1txdat)
91 #define	A1psor1		 (A1col | A1crs | A1txer | A1txen | A1rxdv | A1rxer)
92 #define	A1dir0		 (A1rxdat | A1crs | A1col | A1rxer | A1rxdv)
93 #define	A1dir1		 (A1txdat | A1txen | A1txer)
94 #define	B2psor0		 (B2rxdat | B2txdat | B2crs | B2col | B2rxer | B2rxdv | B2txer)
95 #define	B2psor1		 (B2txen)
96 #define	B2dir0		 (B2rxdat | B2crs | B2col | B2rxer | B2rxdv)
97 #define	B2dir1		 (B2txdat | B2txen | B2txer)
98 #define	B3psor0		 (B3rxdat | B3txdat | B3crs | B3col | B3rxer | B3rxdv | B3txer | B3txen)
99 #define	B3psor1		 0
100 #define	B3dir0		 (B3rxdat | B3crs | B3col | B3rxer | B3rxdv)
101 #define	B3dir1		 (B3txdat | B3txen | B3txer)
102