1 /* $NetBSD: bif_3_0_d.h,v 1.2 2021/12/18 23:45:09 riastradh Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2016 Advanced Micro Devices, Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included 15 * in all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 21 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef BIF_3_0_D_H 26 #define BIF_3_0_D_H 27 28 #define ixPB0_DFT_DEBUG_CTRL_REG0 0x1300C 29 #define ixPB0_DFT_JIT_INJ_REG0 0x13000 30 #define ixPB0_DFT_JIT_INJ_REG1 0x13004 31 #define ixPB0_DFT_JIT_INJ_REG2 0x13008 32 #define ixPB0_GLB_CTRL_REG0 0x10004 33 #define ixPB0_GLB_CTRL_REG1 0x10008 34 #define ixPB0_GLB_CTRL_REG2 0x1000C 35 #define ixPB0_GLB_CTRL_REG3 0x10010 36 #define ixPB0_GLB_CTRL_REG4 0x10014 37 #define ixPB0_GLB_CTRL_REG5 0x10018 38 #define ixPB0_GLB_OVRD_REG0 0x10030 39 #define ixPB0_GLB_OVRD_REG1 0x10034 40 #define ixPB0_GLB_OVRD_REG2 0x10038 41 #define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x1001C 42 #define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x10020 43 #define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x10024 44 #define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x10028 45 #define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x1002C 46 #define ixPB0_HW_DEBUG 0x12004 47 #define ixPB0_PIF_CNTL 0x0010 48 #define ixPB0_PIF_CNTL2 0x0014 49 #define ixPB0_PIF_HW_DEBUG 0x0002 50 #define ixPB0_PIF_PAIRING 0x0011 51 #define ixPB0_PIF_PDNB_OVERRIDE_0 0x0020 52 #define ixPB0_PIF_PDNB_OVERRIDE_10 0x0032 53 #define ixPB0_PIF_PDNB_OVERRIDE_1 0x0021 54 #define ixPB0_PIF_PDNB_OVERRIDE_11 0x0033 55 #define ixPB0_PIF_PDNB_OVERRIDE_12 0x0034 56 #define ixPB0_PIF_PDNB_OVERRIDE_13 0x0035 57 #define ixPB0_PIF_PDNB_OVERRIDE_14 0x0036 58 #define ixPB0_PIF_PDNB_OVERRIDE_15 0x0037 59 #define ixPB0_PIF_PDNB_OVERRIDE_2 0x0022 60 #define ixPB0_PIF_PDNB_OVERRIDE_3 0x0023 61 #define ixPB0_PIF_PDNB_OVERRIDE_4 0x0024 62 #define ixPB0_PIF_PDNB_OVERRIDE_5 0x0025 63 #define ixPB0_PIF_PDNB_OVERRIDE_6 0x0026 64 #define ixPB0_PIF_PDNB_OVERRIDE_7 0x0027 65 #define ixPB0_PIF_PDNB_OVERRIDE_8 0x0030 66 #define ixPB0_PIF_PDNB_OVERRIDE_9 0x0031 67 #define ixPB0_PIF_PWRDOWN_0 0x0012 68 #define ixPB0_PIF_PWRDOWN_1 0x0013 69 #define ixPB0_PIF_PWRDOWN_2 0x0017 70 #define ixPB0_PIF_PWRDOWN_3 0x0018 71 #define ixPB0_PIF_SC_CTL 0x0016 72 #define ixPB0_PIF_SCRATCH 0x0001 73 #define ixPB0_PIF_SEQ_STATUS_0 0x0028 74 #define ixPB0_PIF_SEQ_STATUS_10 0x003A 75 #define ixPB0_PIF_SEQ_STATUS_1 0x0029 76 #define ixPB0_PIF_SEQ_STATUS_11 0x003B 77 #define ixPB0_PIF_SEQ_STATUS_12 0x003C 78 #define ixPB0_PIF_SEQ_STATUS_13 0x003D 79 #define ixPB0_PIF_SEQ_STATUS_14 0x003E 80 #define ixPB0_PIF_SEQ_STATUS_15 0x003F 81 #define ixPB0_PIF_SEQ_STATUS_2 0x002A 82 #define ixPB0_PIF_SEQ_STATUS_3 0x002B 83 #define ixPB0_PIF_SEQ_STATUS_4 0x002C 84 #define ixPB0_PIF_SEQ_STATUS_5 0x002D 85 #define ixPB0_PIF_SEQ_STATUS_6 0x002E 86 #define ixPB0_PIF_SEQ_STATUS_7 0x002F 87 #define ixPB0_PIF_SEQ_STATUS_8 0x0038 88 #define ixPB0_PIF_SEQ_STATUS_9 0x0039 89 #define ixPB0_PIF_TXPHYSTATUS 0x0015 90 #define ixPB0_PLL_LC0_CTRL_REG0 0x14480 91 #define ixPB0_PLL_LC0_OVRD_REG0 0x14490 92 #define ixPB0_PLL_LC0_OVRD_REG1 0x14494 93 #define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x14500 94 #define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x14504 95 #define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x14508 96 #define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x1450C 97 #define ixPB0_PLL_RO0_CTRL_REG0 0x14440 98 #define ixPB0_PLL_RO0_OVRD_REG0 0x14450 99 #define ixPB0_PLL_RO0_OVRD_REG1 0x14454 100 #define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x14460 101 #define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x14464 102 #define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x14468 103 #define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x1446C 104 #define ixPB0_PLL_RO_GLB_CTRL_REG0 0x14000 105 #define ixPB0_PLL_RO_GLB_OVRD_REG0 0x14010 106 #define ixPB0_RX_GLB_CTRL_REG0 0x16000 107 #define ixPB0_RX_GLB_CTRL_REG1 0x16004 108 #define ixPB0_RX_GLB_CTRL_REG2 0x16008 109 #define ixPB0_RX_GLB_CTRL_REG3 0x1600C 110 #define ixPB0_RX_GLB_CTRL_REG4 0x16010 111 #define ixPB0_RX_GLB_CTRL_REG5 0x16014 112 #define ixPB0_RX_GLB_CTRL_REG6 0x16018 113 #define ixPB0_RX_GLB_CTRL_REG7 0x1601C 114 #define ixPB0_RX_GLB_CTRL_REG8 0x16020 115 #define ixPB0_RX_GLB_OVRD_REG0 0x16030 116 #define ixPB0_RX_GLB_OVRD_REG1 0x16034 117 #define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x16028 118 #define ixPB0_RX_LANE0_CTRL_REG0 0x16440 119 #define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x16448 120 #define ixPB0_RX_LANE10_CTRL_REG0 0x17500 121 #define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x17508 122 #define ixPB0_RX_LANE11_CTRL_REG0 0x17600 123 #define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x17608 124 #define ixPB0_RX_LANE12_CTRL_REG0 0x17840 125 #define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x17848 126 #define ixPB0_RX_LANE13_CTRL_REG0 0x17880 127 #define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x17888 128 #define ixPB0_RX_LANE14_CTRL_REG0 0x17900 129 #define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x17908 130 #define ixPB0_RX_LANE15_CTRL_REG0 0x17A00 131 #define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x17A08 132 #define ixPB0_RX_LANE1_CTRL_REG0 0x16480 133 #define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x16488 134 #define ixPB0_RX_LANE2_CTRL_REG0 0x16500 135 #define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x16508 136 #define ixPB0_RX_LANE3_CTRL_REG0 0x16600 137 #define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x16608 138 #define ixPB0_RX_LANE4_CTRL_REG0 0x16800 139 #define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x16848 140 #define ixPB0_RX_LANE5_CTRL_REG0 0x16880 141 #define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x16888 142 #define ixPB0_RX_LANE6_CTRL_REG0 0x16900 143 #define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x16908 144 #define ixPB0_RX_LANE7_CTRL_REG0 0x16A00 145 #define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x16A08 146 #define ixPB0_RX_LANE8_CTRL_REG0 0x17440 147 #define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x17448 148 #define ixPB0_RX_LANE9_CTRL_REG0 0x17480 149 #define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x17488 150 #define ixPB0_STRAP_GLB_REG0 0x12020 151 #define ixPB0_STRAP_PLL_REG0 0x12030 152 #define ixPB0_STRAP_RX_REG0 0x12028 153 #define ixPB0_STRAP_RX_REG1 0x1202C 154 #define ixPB0_STRAP_TX_REG0 0x12024 155 #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x18014 156 #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x18018 157 #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x1801C 158 #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x18020 159 #define ixPB0_TX_GLB_CTRL_REG0 0x18000 160 #define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x18004 161 #define ixPB0_TX_GLB_OVRD_REG0 0x18030 162 #define ixPB0_TX_GLB_OVRD_REG1 0x18034 163 #define ixPB0_TX_GLB_OVRD_REG2 0x18038 164 #define ixPB0_TX_GLB_OVRD_REG3 0x1803C 165 #define ixPB0_TX_GLB_OVRD_REG4 0x18040 166 #define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x18010 167 #define ixPB0_TX_LANE0_CTRL_REG0 0x18440 168 #define ixPB0_TX_LANE0_OVRD_REG0 0x18444 169 #define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x18448 170 #define ixPB0_TX_LANE10_CTRL_REG0 0x19500 171 #define ixPB0_TX_LANE10_OVRD_REG0 0x19504 172 #define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x19508 173 #define ixPB0_TX_LANE11_CTRL_REG0 0x19600 174 #define ixPB0_TX_LANE11_OVRD_REG0 0x19604 175 #define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x19608 176 #define ixPB0_TX_LANE12_CTRL_REG0 0x19840 177 #define ixPB0_TX_LANE12_OVRD_REG0 0x19844 178 #define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x19848 179 #define ixPB0_TX_LANE13_CTRL_REG0 0x19880 180 #define ixPB0_TX_LANE13_OVRD_REG0 0x19884 181 #define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x19888 182 #define ixPB0_TX_LANE14_CTRL_REG0 0x19900 183 #define ixPB0_TX_LANE14_OVRD_REG0 0x19904 184 #define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x19908 185 #define ixPB0_TX_LANE15_CTRL_REG0 0x19A00 186 #define ixPB0_TX_LANE15_OVRD_REG0 0x19A04 187 #define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x19A08 188 #define ixPB0_TX_LANE1_CTRL_REG0 0x18480 189 #define ixPB0_TX_LANE1_OVRD_REG0 0x18484 190 #define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x18488 191 #define ixPB0_TX_LANE2_CTRL_REG0 0x18500 192 #define ixPB0_TX_LANE2_OVRD_REG0 0x18504 193 #define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x18508 194 #define ixPB0_TX_LANE3_CTRL_REG0 0x18600 195 #define ixPB0_TX_LANE3_OVRD_REG0 0x18604 196 #define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x18608 197 #define ixPB0_TX_LANE4_CTRL_REG0 0x18840 198 #define ixPB0_TX_LANE4_OVRD_REG0 0x18844 199 #define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x18848 200 #define ixPB0_TX_LANE5_CTRL_REG0 0x18880 201 #define ixPB0_TX_LANE5_OVRD_REG0 0x18884 202 #define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x18888 203 #define ixPB0_TX_LANE6_CTRL_REG0 0x18900 204 #define ixPB0_TX_LANE6_OVRD_REG0 0x18904 205 #define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x18908 206 #define ixPB0_TX_LANE7_CTRL_REG0 0x18A00 207 #define ixPB0_TX_LANE7_OVRD_REG0 0x18A04 208 #define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x18A08 209 #define ixPB0_TX_LANE8_CTRL_REG0 0x19440 210 #define ixPB0_TX_LANE8_OVRD_REG0 0x19444 211 #define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x19448 212 #define ixPB0_TX_LANE9_CTRL_REG0 0x19480 213 #define ixPB0_TX_LANE9_OVRD_REG0 0x19484 214 #define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x19488 215 #define ixPB1_DFT_DEBUG_CTRL_REG0 0x1300C 216 #define ixPB1_DFT_JIT_INJ_REG0 0x13000 217 #define ixPB1_DFT_JIT_INJ_REG1 0x13004 218 #define ixPB1_DFT_JIT_INJ_REG2 0x13008 219 #define ixPB1_GLB_CTRL_REG0 0x10004 220 #define ixPB1_GLB_CTRL_REG1 0x10008 221 #define ixPB1_GLB_CTRL_REG2 0x1000C 222 #define ixPB1_GLB_CTRL_REG3 0x10010 223 #define ixPB1_GLB_CTRL_REG4 0x10014 224 #define ixPB1_GLB_CTRL_REG5 0x10018 225 #define ixPB1_GLB_OVRD_REG0 0x10030 226 #define ixPB1_GLB_OVRD_REG1 0x10034 227 #define ixPB1_GLB_OVRD_REG2 0x10038 228 #define ixPB1_GLB_SCI_STAT_OVRD_REG0 0x1001C 229 #define ixPB1_GLB_SCI_STAT_OVRD_REG1 0x10020 230 #define ixPB1_GLB_SCI_STAT_OVRD_REG2 0x10024 231 #define ixPB1_GLB_SCI_STAT_OVRD_REG3 0x10028 232 #define ixPB1_GLB_SCI_STAT_OVRD_REG4 0x1002C 233 #define ixPB1_HW_DEBUG 0x12004 234 #define ixPB1_PIF_CNTL 0x0010 235 #define ixPB1_PIF_CNTL2 0x0014 236 #define ixPB1_PIF_HW_DEBUG 0x0002 237 #define ixPB1_PIF_PAIRING 0x0011 238 #define ixPB1_PIF_PDNB_OVERRIDE_0 0x0020 239 #define ixPB1_PIF_PDNB_OVERRIDE_10 0x0032 240 #define ixPB1_PIF_PDNB_OVERRIDE_1 0x0021 241 #define ixPB1_PIF_PDNB_OVERRIDE_11 0x0033 242 #define ixPB1_PIF_PDNB_OVERRIDE_12 0x0034 243 #define ixPB1_PIF_PDNB_OVERRIDE_13 0x0035 244 #define ixPB1_PIF_PDNB_OVERRIDE_14 0x0036 245 #define ixPB1_PIF_PDNB_OVERRIDE_15 0x0037 246 #define ixPB1_PIF_PDNB_OVERRIDE_2 0x0022 247 #define ixPB1_PIF_PDNB_OVERRIDE_3 0x0023 248 #define ixPB1_PIF_PDNB_OVERRIDE_4 0x0024 249 #define ixPB1_PIF_PDNB_OVERRIDE_5 0x0025 250 #define ixPB1_PIF_PDNB_OVERRIDE_6 0x0026 251 #define ixPB1_PIF_PDNB_OVERRIDE_7 0x0027 252 #define ixPB1_PIF_PDNB_OVERRIDE_8 0x0030 253 #define ixPB1_PIF_PDNB_OVERRIDE_9 0x0031 254 #define ixPB1_PIF_PWRDOWN_0 0x0012 255 #define ixPB1_PIF_PWRDOWN_1 0x0013 256 #define ixPB1_PIF_PWRDOWN_2 0x0017 257 #define ixPB1_PIF_PWRDOWN_3 0x0018 258 #define ixPB1_PIF_SC_CTL 0x0016 259 #define ixPB1_PIF_SCRATCH 0x0001 260 #define ixPB1_PIF_SEQ_STATUS_0 0x0028 261 #define ixPB1_PIF_SEQ_STATUS_10 0x003A 262 #define ixPB1_PIF_SEQ_STATUS_1 0x0029 263 #define ixPB1_PIF_SEQ_STATUS_11 0x003B 264 #define ixPB1_PIF_SEQ_STATUS_12 0x003C 265 #define ixPB1_PIF_SEQ_STATUS_13 0x003D 266 #define ixPB1_PIF_SEQ_STATUS_14 0x003E 267 #define ixPB1_PIF_SEQ_STATUS_15 0x003F 268 #define ixPB1_PIF_SEQ_STATUS_2 0x002A 269 #define ixPB1_PIF_SEQ_STATUS_3 0x002B 270 #define ixPB1_PIF_SEQ_STATUS_4 0x002C 271 #define ixPB1_PIF_SEQ_STATUS_5 0x002D 272 #define ixPB1_PIF_SEQ_STATUS_6 0x002E 273 #define ixPB1_PIF_SEQ_STATUS_7 0x002F 274 #define ixPB1_PIF_SEQ_STATUS_8 0x0038 275 #define ixPB1_PIF_SEQ_STATUS_9 0x0039 276 #define ixPB1_PIF_TXPHYSTATUS 0x0015 277 #define ixPB1_PLL_LC0_CTRL_REG0 0x14480 278 #define ixPB1_PLL_LC0_OVRD_REG0 0x14490 279 #define ixPB1_PLL_LC0_OVRD_REG1 0x14494 280 #define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 0x14500 281 #define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 0x14504 282 #define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 0x14508 283 #define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 0x1450C 284 #define ixPB1_PLL_RO0_CTRL_REG0 0x14440 285 #define ixPB1_PLL_RO0_OVRD_REG0 0x14450 286 #define ixPB1_PLL_RO0_OVRD_REG1 0x14454 287 #define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 0x14460 288 #define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 0x14464 289 #define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 0x14468 290 #define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 0x1446C 291 #define ixPB1_PLL_RO_GLB_CTRL_REG0 0x14000 292 #define ixPB1_PLL_RO_GLB_OVRD_REG0 0x14010 293 #define ixPB1_RX_GLB_CTRL_REG0 0x16000 294 #define ixPB1_RX_GLB_CTRL_REG1 0x16004 295 #define ixPB1_RX_GLB_CTRL_REG2 0x16008 296 #define ixPB1_RX_GLB_CTRL_REG3 0x1600C 297 #define ixPB1_RX_GLB_CTRL_REG4 0x16010 298 #define ixPB1_RX_GLB_CTRL_REG5 0x16014 299 #define ixPB1_RX_GLB_CTRL_REG6 0x16018 300 #define ixPB1_RX_GLB_CTRL_REG7 0x1601C 301 #define ixPB1_RX_GLB_CTRL_REG8 0x16020 302 #define ixPB1_RX_GLB_OVRD_REG0 0x16030 303 #define ixPB1_RX_GLB_OVRD_REG1 0x16034 304 #define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 0x16028 305 #define ixPB1_RX_LANE0_CTRL_REG0 0x16440 306 #define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 0x16448 307 #define ixPB1_RX_LANE10_CTRL_REG0 0x17500 308 #define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 0x17508 309 #define ixPB1_RX_LANE11_CTRL_REG0 0x17600 310 #define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 0x17608 311 #define ixPB1_RX_LANE12_CTRL_REG0 0x17840 312 #define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 0x17848 313 #define ixPB1_RX_LANE13_CTRL_REG0 0x17880 314 #define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 0x17888 315 #define ixPB1_RX_LANE14_CTRL_REG0 0x17900 316 #define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 0x17908 317 #define ixPB1_RX_LANE15_CTRL_REG0 0x17A00 318 #define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 0x17A08 319 #define ixPB1_RX_LANE1_CTRL_REG0 0x16480 320 #define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 0x16488 321 #define ixPB1_RX_LANE2_CTRL_REG0 0x16500 322 #define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 0x16508 323 #define ixPB1_RX_LANE3_CTRL_REG0 0x16600 324 #define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 0x16608 325 #define ixPB1_RX_LANE4_CTRL_REG0 0x16800 326 #define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 0x16848 327 #define ixPB1_RX_LANE5_CTRL_REG0 0x16880 328 #define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 0x16888 329 #define ixPB1_RX_LANE6_CTRL_REG0 0x16900 330 #define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 0x16908 331 #define ixPB1_RX_LANE7_CTRL_REG0 0x16A00 332 #define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 0x16A08 333 #define ixPB1_RX_LANE8_CTRL_REG0 0x17440 334 #define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 0x17448 335 #define ixPB1_RX_LANE9_CTRL_REG0 0x17480 336 #define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 0x17488 337 #define ixPB1_STRAP_GLB_REG0 0x12020 338 #define ixPB1_STRAP_PLL_REG0 0x12030 339 #define ixPB1_STRAP_RX_REG0 0x12028 340 #define ixPB1_STRAP_RX_REG1 0x1202C 341 #define ixPB1_STRAP_TX_REG0 0x12024 342 #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x18014 343 #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x18018 344 #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x1801C 345 #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x18020 346 #define ixPB1_TX_GLB_CTRL_REG0 0x18000 347 #define ixPB1_TX_GLB_LANE_SKEW_CTRL 0x18004 348 #define ixPB1_TX_GLB_OVRD_REG0 0x18030 349 #define ixPB1_TX_GLB_OVRD_REG1 0x18034 350 #define ixPB1_TX_GLB_OVRD_REG2 0x18038 351 #define ixPB1_TX_GLB_OVRD_REG3 0x1803C 352 #define ixPB1_TX_GLB_OVRD_REG4 0x18040 353 #define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 0x18010 354 #define ixPB1_TX_LANE0_CTRL_REG0 0x18440 355 #define ixPB1_TX_LANE0_OVRD_REG0 0x18444 356 #define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 0x18448 357 #define ixPB1_TX_LANE10_CTRL_REG0 0x19500 358 #define ixPB1_TX_LANE10_OVRD_REG0 0x19504 359 #define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 0x19508 360 #define ixPB1_TX_LANE11_CTRL_REG0 0x19600 361 #define ixPB1_TX_LANE11_OVRD_REG0 0x19604 362 #define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 0x19608 363 #define ixPB1_TX_LANE12_CTRL_REG0 0x19840 364 #define ixPB1_TX_LANE12_OVRD_REG0 0x19844 365 #define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 0x19848 366 #define ixPB1_TX_LANE13_CTRL_REG0 0x19880 367 #define ixPB1_TX_LANE13_OVRD_REG0 0x19884 368 #define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 0x19888 369 #define ixPB1_TX_LANE14_CTRL_REG0 0x19900 370 #define ixPB1_TX_LANE14_OVRD_REG0 0x19904 371 #define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 0x19908 372 #define ixPB1_TX_LANE15_CTRL_REG0 0x19A00 373 #define ixPB1_TX_LANE15_OVRD_REG0 0x19A04 374 #define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 0x19A08 375 #define ixPB1_TX_LANE1_CTRL_REG0 0x18480 376 #define ixPB1_TX_LANE1_OVRD_REG0 0x18484 377 #define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 0x18488 378 #define ixPB1_TX_LANE2_CTRL_REG0 0x18500 379 #define ixPB1_TX_LANE2_OVRD_REG0 0x18504 380 #define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 0x18508 381 #define ixPB1_TX_LANE3_CTRL_REG0 0x18600 382 #define ixPB1_TX_LANE3_OVRD_REG0 0x18604 383 #define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 0x18608 384 #define ixPB1_TX_LANE4_CTRL_REG0 0x18840 385 #define ixPB1_TX_LANE4_OVRD_REG0 0x18844 386 #define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 0x18848 387 #define ixPB1_TX_LANE5_CTRL_REG0 0x18880 388 #define ixPB1_TX_LANE5_OVRD_REG0 0x18884 389 #define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 0x18888 390 #define ixPB1_TX_LANE6_CTRL_REG0 0x18900 391 #define ixPB1_TX_LANE6_OVRD_REG0 0x18904 392 #define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 0x18908 393 #define ixPB1_TX_LANE7_CTRL_REG0 0x18A00 394 #define ixPB1_TX_LANE7_OVRD_REG0 0x18A04 395 #define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 0x18A08 396 #define ixPB1_TX_LANE8_CTRL_REG0 0x19440 397 #define ixPB1_TX_LANE8_OVRD_REG0 0x19444 398 #define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 0x19448 399 #define ixPB1_TX_LANE9_CTRL_REG0 0x19480 400 #define ixPB1_TX_LANE9_OVRD_REG0 0x19484 401 #define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 0x19488 402 #define ixPCIE_BUS_CNTL 0x0021 403 #define ixPCIE_CFG_CNTL 0x003C 404 #define ixPCIE_CI_CNTL 0x0020 405 #define ixPCIE_CNTL 0x0010 406 #define ixPCIE_CNTL2 0x001C 407 #define ixPCIE_CONFIG_CNTL 0x0011 408 #define ixPCIE_DEBUG_CNTL 0x0012 409 #define ixPCIE_ERR_CNTL 0x006A 410 #define ixPCIE_F0_DPA_CAP 0x00E0 411 #define ixPCIE_F0_DPA_CNTL 0x00E5 412 #define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x00E4 413 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x00E7 414 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x00E8 415 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x00E9 416 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x00EA 417 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x00EB 418 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x00EC 419 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x00ED 420 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x00EE 421 #define ixPCIE_FC_CPL 0x0062 422 #define ixPCIE_FC_NP 0x0061 423 #define ixPCIE_FC_P 0x0060 424 #define ixPCIE_HW_DEBUG 0x0002 425 #define ixPCIE_I2C_REG_ADDR_EXPAND 0x003A 426 #define ixPCIE_I2C_REG_DATA 0x003B 427 #define ixPCIE_INT_CNTL 0x001A 428 #define ixPCIE_INT_STATUS 0x001B 429 #define ixPCIE_LC_BEST_EQ_SETTINGS 0x00B9 430 #define ixPCIE_LC_BW_CHANGE_CNTL 0x00B2 431 #define ixPCIE_LC_CDR_CNTL 0x00B3 432 #define ixPCIE_LC_CNTL 0x00A0 433 #define ixPCIE_LC_CNTL2 0x00B1 434 #define ixPCIE_LC_CNTL3 0x00B5 435 #define ixPCIE_LC_CNTL4 0x00B6 436 #define ixPCIE_LC_CNTL5 0x00B7 437 #define ixPCIE_LC_FORCE_COEFF 0x00B8 438 #define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x00BA 439 #define ixPCIE_LC_LANE_CNTL 0x00B4 440 #define ixPCIE_LC_LINK_WIDTH_CNTL 0x00A2 441 #define ixPCIE_LC_N_FTS_CNTL 0x00A3 442 #define ixPCIE_LC_SPEED_CNTL 0x00A4 443 #define ixPCIE_LC_STATE0 0x00A5 444 #define ixPCIE_LC_STATE10 0x0026 445 #define ixPCIE_LC_STATE1 0x00A6 446 #define ixPCIE_LC_STATE11 0x0027 447 #define ixPCIE_LC_STATE2 0x00A7 448 #define ixPCIE_LC_STATE3 0x00A8 449 #define ixPCIE_LC_STATE4 0x00A9 450 #define ixPCIE_LC_STATE5 0x00AA 451 #define ixPCIE_LC_STATE6 0x0022 452 #define ixPCIE_LC_STATE7 0x0023 453 #define ixPCIE_LC_STATE8 0x0024 454 #define ixPCIE_LC_STATE9 0x0025 455 #define ixPCIE_LC_STATUS1 0x0028 456 #define ixPCIE_LC_STATUS2 0x0029 457 #define ixPCIE_LC_TRAINING_CNTL 0x00A1 458 #define ixPCIE_P_BUF_STATUS 0x0041 459 #define ixPCIE_P_CNTL 0x0040 460 #define ixPCIE_P_DECODER_STATUS 0x0042 461 #define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x0093 462 #define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x0094 463 #define ixPCIE_PERF_CNTL_MST_C_CLK 0x0087 464 #define ixPCIE_PERF_CNTL_MST_R_CLK 0x0084 465 #define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x0090 466 #define ixPCIE_PERF_CNTL_SLV_R_CLK 0x008A 467 #define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x008D 468 #define ixPCIE_PERF_CNTL_TXCLK 0x0081 469 #define ixPCIE_PERF_CNTL_TXCLK2 0x0095 470 #define ixPCIE_PERF_COUNT0_MST_C_CLK 0x0088 471 #define ixPCIE_PERF_COUNT0_MST_R_CLK 0x0085 472 #define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x0091 473 #define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x008B 474 #define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x008E 475 #define ixPCIE_PERF_COUNT0_TXCLK 0x0082 476 #define ixPCIE_PERF_COUNT0_TXCLK2 0x0096 477 #define ixPCIE_PERF_COUNT1_MST_C_CLK 0x0089 478 #define ixPCIE_PERF_COUNT1_MST_R_CLK 0x0086 479 #define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x0092 480 #define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x008C 481 #define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x008F 482 #define ixPCIE_PERF_COUNT1_TXCLK 0x0083 483 #define ixPCIE_PERF_COUNT1_TXCLK2 0x0097 484 #define ixPCIE_PERF_COUNT_CNTL 0x0080 485 #define ixPCIEP_HW_DEBUG 0x0002 486 #define ixPCIE_P_MISC_STATUS 0x0043 487 #define ixPCIEP_PORT_CNTL 0x0010 488 #define ixPCIE_P_PORT_LANE_STATUS 0x0050 489 #define ixPCIE_PRBS_CLR 0x00C8 490 #define ixPCIE_PRBS_ERRCNT_0 0x00D0 491 #define ixPCIE_PRBS_ERRCNT_10 0x00DA 492 #define ixPCIE_PRBS_ERRCNT_1 0x00D1 493 #define ixPCIE_PRBS_ERRCNT_11 0x00DB 494 #define ixPCIE_PRBS_ERRCNT_12 0x00DC 495 #define ixPCIE_PRBS_ERRCNT_13 0x00DD 496 #define ixPCIE_PRBS_ERRCNT_14 0x00DE 497 #define ixPCIE_PRBS_ERRCNT_15 0x00DF 498 #define ixPCIE_PRBS_ERRCNT_2 0x00D2 499 #define ixPCIE_PRBS_ERRCNT_3 0x00D3 500 #define ixPCIE_PRBS_ERRCNT_4 0x00D4 501 #define ixPCIE_PRBS_ERRCNT_5 0x00D5 502 #define ixPCIE_PRBS_ERRCNT_6 0x00D6 503 #define ixPCIE_PRBS_ERRCNT_7 0x00D7 504 #define ixPCIE_PRBS_ERRCNT_8 0x00D8 505 #define ixPCIE_PRBS_ERRCNT_9 0x00D9 506 #define ixPCIE_PRBS_FREERUN 0x00CB 507 #define ixPCIE_PRBS_HI_BITCNT 0x00CF 508 #define ixPCIE_PRBS_LO_BITCNT 0x00CE 509 #define ixPCIE_PRBS_MISC 0x00CC 510 #define ixPCIE_PRBS_STATUS1 0x00C9 511 #define ixPCIE_PRBS_STATUS2 0x00CA 512 #define ixPCIE_PRBS_USER_PATTERN 0x00CD 513 #define ixPCIE_P_RCV_L0S_FTS_DET 0x0050 514 #define ixPCIEP_RESERVED 0x0000 515 #define ixPCIEP_SCRATCH 0x0001 516 #define ixPCIEP_STRAP_LC 0x00C0 517 #define ixPCIEP_STRAP_MISC 0x00C1 518 #define ixPCIE_RESERVED 0x0000 519 #define ixPCIE_RX_CNTL 0x0070 520 #define ixPCIE_RX_CNTL2 0x001D 521 #define ixPCIE_RX_CNTL3 0x0074 522 #define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x0082 523 #define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x0081 524 #define ixPCIE_RX_CREDITS_ALLOCATED_P 0x0080 525 #define ixPCIE_RX_EXPECTED_SEQNUM 0x0071 526 #define ixPCIE_RX_LAST_TLP0 0x0031 527 #define ixPCIE_RX_LAST_TLP1 0x0032 528 #define ixPCIE_RX_LAST_TLP2 0x0033 529 #define ixPCIE_RX_LAST_TLP3 0x0034 530 #define ixPCIE_RX_NUM_NAK 0x000E 531 #define ixPCIE_RX_NUM_NAK_GENERATED 0x000F 532 #define ixPCIE_RX_VENDOR_SPECIFIC 0x0072 533 #define ixPCIE_SCRATCH 0x0001 534 #define ixPCIE_STRAP_F0 0x00B0 535 #define ixPCIE_STRAP_F1 0x00B1 536 #define ixPCIE_STRAP_F2 0x00B2 537 #define ixPCIE_STRAP_F3 0x00B3 538 #define ixPCIE_STRAP_F4 0x00B4 539 #define ixPCIE_STRAP_F5 0x00B5 540 #define ixPCIE_STRAP_F6 0x00B6 541 #define ixPCIE_STRAP_F7 0x00B7 542 #define ixPCIE_STRAP_I2C_BD 0x00C4 543 #define ixPCIE_STRAP_MISC 0x00C0 544 #define ixPCIE_STRAP_MISC2 0x00C1 545 #define ixPCIE_STRAP_PI 0x00C2 546 #define ixPCIE_TX_ACK_LATENCY_LIMIT 0x0026 547 #define ixPCIE_TX_CNTL 0x0020 548 #define ixPCIE_TX_CREDITS_ADVT_CPL 0x0032 549 #define ixPCIE_TX_CREDITS_ADVT_NP 0x0031 550 #define ixPCIE_TX_CREDITS_ADVT_P 0x0030 551 #define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x0037 552 #define ixPCIE_TX_CREDITS_INIT_CPL 0x0035 553 #define ixPCIE_TX_CREDITS_INIT_NP 0x0034 554 #define ixPCIE_TX_CREDITS_INIT_P 0x0033 555 #define ixPCIE_TX_CREDITS_STATUS 0x0036 556 #define ixPCIE_TX_LAST_TLP0 0x0035 557 #define ixPCIE_TX_LAST_TLP1 0x0036 558 #define ixPCIE_TX_LAST_TLP2 0x0037 559 #define ixPCIE_TX_LAST_TLP3 0x0038 560 #define ixPCIE_TX_REPLAY 0x0025 561 #define ixPCIE_TX_REQUESTER_ID 0x0021 562 #define ixPCIE_TX_REQUEST_NUM_CNTL 0x0023 563 #define ixPCIE_TX_SEQ 0x0024 564 #define ixPCIE_TX_VENDOR_SPECIFIC 0x0022 565 #define ixPCIE_WPR_CNTL 0x0030 566 #define mmBACO_CNTL 0x14E5 567 #define mmBF_ANA_ISO_CNTL 0x14C7 568 #define mmBIF_BACO_DEBUG 0x14DF 569 #define mmBIF_BACO_DEBUG_LATCH 0x14DC 570 #define mmBIF_BACO_MSIC 0x14DE 571 #define mmBIF_BUSNUM_CNTL1 0x1525 572 #define mmBIF_BUSNUM_CNTL2 0x152B 573 #define mmBIF_BUSNUM_LIST0 0x1526 574 #define mmBIF_BUSNUM_LIST1 0x1527 575 #define mmBIF_BUSY_DELAY_CNTR 0x1529 576 #define mmBIF_CLK_PDWN_DELAY_TIMER 0x151F 577 #define mmBIF_DEBUG_CNTL 0x151C 578 #define mmBIF_DEBUG_MUX 0x151D 579 #define mmBIF_DEBUG_OUT 0x151E 580 #define mmBIF_DEVFUNCNUM_LIST0 0x14E8 581 #define mmBIF_DEVFUNCNUM_LIST1 0x14E7 582 #define mmBIF_FB_EN 0x1524 583 #define mmBIF_FEATURES_CONTROL_MISC 0x14C2 584 #define mmBIF_PERFCOUNTER0_RESULT 0x152D 585 #define mmBIF_PERFCOUNTER1_RESULT 0x152E 586 #define mmBIF_PERFMON_CNTL 0x152C 587 #define mmBIF_PIF_TXCLK_SWITCH_TIMER 0x152F 588 #define mmBIF_RESET_EN 0x1511 589 #define mmBIF_SCRATCH0 0x150E 590 #define mmBIF_SCRATCH1 0x150F 591 #define mmBIF_SSA_DISP_LOWER 0x14D2 592 #define mmBIF_SSA_DISP_UPPER 0x14D3 593 #define mmBIF_SSA_GFX0_LOWER 0x14CA 594 #define mmBIF_SSA_GFX0_UPPER 0x14CB 595 #define mmBIF_SSA_GFX1_LOWER 0x14CC 596 #define mmBIF_SSA_GFX1_UPPER 0x14CD 597 #define mmBIF_SSA_GFX2_LOWER 0x14CE 598 #define mmBIF_SSA_GFX2_UPPER 0x14CF 599 #define mmBIF_SSA_GFX3_LOWER 0x14D0 600 #define mmBIF_SSA_GFX3_UPPER 0x14D1 601 #define mmBIF_SSA_MC_LOWER 0x14D4 602 #define mmBIF_SSA_MC_UPPER 0x14D5 603 #define mmBIF_SSA_PWR_STATUS 0x14C8 604 #define mmBIF_XDMA_HI 0x14C1 605 #define mmBIF_XDMA_LO 0x14C0 606 #define mmBIOS_SCRATCH_0 0x05C9 607 #define mmBIOS_SCRATCH_10 0x05D3 608 #define mmBIOS_SCRATCH_1 0x05CA 609 #define mmBIOS_SCRATCH_11 0x05D4 610 #define mmBIOS_SCRATCH_12 0x05D5 611 #define mmBIOS_SCRATCH_13 0x05D6 612 #define mmBIOS_SCRATCH_14 0x05D7 613 #define mmBIOS_SCRATCH_15 0x05D8 614 #define mmBIOS_SCRATCH_2 0x05CB 615 #define mmBIOS_SCRATCH_3 0x05CC 616 #define mmBIOS_SCRATCH_4 0x05CD 617 #define mmBIOS_SCRATCH_5 0x05CE 618 #define mmBIOS_SCRATCH_6 0x05CF 619 #define mmBIOS_SCRATCH_7 0x05D0 620 #define mmBIOS_SCRATCH_8 0x05D1 621 #define mmBIOS_SCRATCH_9 0x05D2 622 #define mmBUS_CNTL 0x1508 623 #define mmCAPTURE_HOST_BUSNUM 0x153C 624 #define mmCLKREQB_PAD_CNTL 0x1521 625 #define mmCONFIG_APER_SIZE 0x150C 626 #define mmCONFIG_CNTL 0x1509 627 #define mmCONFIG_F0_BASE 0x150B 628 #define mmCONFIG_MEMSIZE 0x150A 629 #define mmCONFIG_REG_APER_SIZE 0x150D 630 #define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520 631 #define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528 632 #define mmHOST_BUSNUM 0x153D 633 #define mmHW_DEBUG 0x1515 634 #define mmIMPCTL_RESET 0x14F5 635 #define mmINTERRUPT_CNTL 0x151A 636 #define mmINTERRUPT_CNTL2 0x151B 637 #define mmMASTER_CREDIT_CNTL 0x1516 638 #define mmMM_CFGREGS_CNTL 0x1513 639 #define mmMM_DATA 0x0001 640 #define mmMM_INDEX 0x0000 641 #define mmMM_INDEX_HI 0x0006 642 #define mmNEW_REFCLKB_TIMER 0x14EA 643 #define mmNEW_REFCLKB_TIMER_1 0x14E9 644 #define mmPCIE_DATA 0x000D 645 #define mmPCIE_INDEX 0x000C 646 #define mmPEER0_FB_OFFSET_HI 0x14F3 647 #define mmPEER0_FB_OFFSET_LO 0x14F2 648 #define mmPEER1_FB_OFFSET_HI 0x14F1 649 #define mmPEER1_FB_OFFSET_LO 0x14F0 650 #define mmPEER2_FB_OFFSET_HI 0x14EF 651 #define mmPEER2_FB_OFFSET_LO 0x14EE 652 #define mmPEER3_FB_OFFSET_HI 0x14ED 653 #define mmPEER3_FB_OFFSET_LO 0x14EC 654 #define mmPEER_REG_RANGE0 0x153E 655 #define mmPEER_REG_RANGE1 0x153F 656 #define mmSLAVE_HANG_ERROR 0x153B 657 #define mmSLAVE_HANG_PROTECTION_CNTL 0x1536 658 #define mmSLAVE_REQ_CREDIT_CNTL 0x1517 659 #define mmSMBCLK_PAD_CNTL 0x1523 660 #define mmSMBDAT_PAD_CNTL 0x1522 661 #define mmSMBUS_BACO_DUMMY 0x14C6 662 663 #endif 664