1 /* $NetBSD: bcm2835_bsc.c,v 1.16 2024/02/16 15:11:38 skrll Exp $ */
2
3 /*
4 * Copyright (c) 2019 Jason R. Thorpe
5 * Copyright (c) 2012 Jonathan A. Kollasch
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
21 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
23 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
24 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
26 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
27 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 __KERNEL_RCSID(0, "$NetBSD: bcm2835_bsc.c,v 1.16 2024/02/16 15:11:38 skrll Exp $");
32
33 #include <sys/param.h>
34 #include <sys/bus.h>
35 #include <sys/device.h>
36 #include <sys/kernhist.h>
37 #include <sys/intr.h>
38 #include <sys/mutex.h>
39 #include <sys/systm.h>
40
41 #include <dev/i2c/i2cvar.h>
42
43 #include <arm/broadcom/bcm2835reg.h>
44 #include <arm/broadcom/bcm2835_bscreg.h>
45 #include <arm/broadcom/bcm2835_bscvar.h>
46
47 static void bsciic_exec_func_idle(struct bsciic_softc * const);
48 static void bsciic_exec_func_send_addr(struct bsciic_softc * const);
49 static void bsciic_exec_func_send_cmd(struct bsciic_softc * const);
50 static void bsciic_exec_func_send_data(struct bsciic_softc * const);
51 static void bsciic_exec_func_recv_data(struct bsciic_softc * const);
52 static void bsciic_exec_func_done(struct bsciic_softc * const);
53 static void bsciic_exec_func_error(struct bsciic_softc * const);
54
55 const struct {
56 void (*func)(struct bsciic_softc * const);
57 uint32_t c_bits;
58 uint32_t s_bits;
59 } bsciic_exec_state_data[] = {
60 [BSC_EXEC_STATE_IDLE] = {
61 .func = bsciic_exec_func_idle,
62 },
63 [BSC_EXEC_STATE_SEND_ADDR] = {
64 .func = bsciic_exec_func_send_addr,
65 },
66 [BSC_EXEC_STATE_SEND_CMD] = {
67 .func = bsciic_exec_func_send_cmd,
68 .c_bits = BSC_C_INTT,
69 .s_bits = BSC_S_TXW,
70 },
71 [BSC_EXEC_STATE_SEND_DATA] = {
72 .func = bsciic_exec_func_send_data,
73 .c_bits = BSC_C_INTT,
74 .s_bits = BSC_S_TXW,
75 },
76 [BSC_EXEC_STATE_RECV_DATA] = {
77 .func = bsciic_exec_func_recv_data,
78 .c_bits = BSC_C_READ | BSC_C_INTR,
79 .s_bits = BSC_S_RXR,
80 },
81 [BSC_EXEC_STATE_DONE] = {
82 .func = bsciic_exec_func_done,
83 },
84 [BSC_EXEC_STATE_ERROR] = {
85 .func = bsciic_exec_func_error,
86 },
87 };
88
89 int bsciic_debug = 0;
90
91 void
bsciic_attach(struct bsciic_softc * sc)92 bsciic_attach(struct bsciic_softc *sc)
93 {
94 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_VM);
95 cv_init(&sc->sc_intr_wait, device_xname(sc->sc_dev));
96
97 /* clear FIFO, disable controller */
98 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_C, BSC_C_CLEAR_CLEAR);
99 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_S, BSC_S_CLKT |
100 BSC_S_ERR | BSC_S_DONE);
101 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_DLEN, 0);
102
103 u_int divider = howmany(sc->sc_frequency, sc->sc_clkrate);
104 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_DIV,
105 __SHIFTIN(divider, BSC_DIV_CDIV));
106 }
107
108 int
bsciic_acquire_bus(void * v,int flags)109 bsciic_acquire_bus(void *v, int flags)
110 {
111 struct bsciic_softc * const sc = v;
112 uint32_t s __diagused;
113
114 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_S, BSC_S_CLKT |
115 BSC_S_ERR | BSC_S_DONE);
116 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_C, BSC_C_I2CEN |
117 BSC_C_CLEAR_CLEAR);
118 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S);
119 KASSERT((s & BSC_S_TA) == 0);
120
121 return 0;
122 }
123
124 void
bsciic_release_bus(void * v,int flags)125 bsciic_release_bus(void *v, int flags)
126 {
127 struct bsciic_softc * const sc = v;
128
129 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_C, BSC_C_CLEAR_CLEAR);
130 }
131
132 static void
bsciic_exec_lock(struct bsciic_softc * const sc)133 bsciic_exec_lock(struct bsciic_softc * const sc)
134 {
135 if ((sc->sc_exec.flags & I2C_F_POLL) == 0) {
136 mutex_enter(&sc->sc_intr_lock);
137 }
138 }
139
140 static void
bsciic_exec_unlock(struct bsciic_softc * const sc)141 bsciic_exec_unlock(struct bsciic_softc * const sc)
142 {
143 if ((sc->sc_exec.flags & I2C_F_POLL) == 0) {
144 mutex_exit(&sc->sc_intr_lock);
145 }
146 }
147
148 static void
bsciic_txfill(struct bsciic_softc * const sc)149 bsciic_txfill(struct bsciic_softc * const sc)
150 {
151 uint32_t s;
152
153 while (sc->sc_bufpos != sc->sc_buflen) {
154 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S);
155 if ((s & BSC_S_TXD) == 0)
156 break;
157 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_FIFO,
158 sc->sc_buf[sc->sc_bufpos++]);
159 }
160 }
161
162 static void
bsciic_rxdrain(struct bsciic_softc * const sc)163 bsciic_rxdrain(struct bsciic_softc * const sc)
164 {
165 uint32_t s;
166
167 while (sc->sc_bufpos != sc->sc_buflen) {
168 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S);
169 if ((s & BSC_S_RXD) == 0)
170 break;
171 sc->sc_buf[sc->sc_bufpos++] =
172 (uint8_t)bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_FIFO);
173 }
174 }
175
176 static bsc_exec_state_t
bsciic_next_state(struct bsciic_softc * const sc)177 bsciic_next_state(struct bsciic_softc * const sc)
178 {
179 switch (sc->sc_exec_state) {
180 case BSC_EXEC_STATE_IDLE:
181 if (sc->sc_exec.addr > 0x7f) {
182 return BSC_EXEC_STATE_SEND_ADDR;
183 }
184 /* FALLTHROUGH */
185
186 case BSC_EXEC_STATE_SEND_ADDR:
187 if (sc->sc_exec.cmdlen) {
188 return BSC_EXEC_STATE_SEND_CMD;
189 }
190 /* FALLTHROUGH */
191
192 case BSC_EXEC_STATE_SEND_CMD:
193 if (sc->sc_exec.datalen == 0) {
194 return BSC_EXEC_STATE_DONE;
195 }
196
197 if (I2C_OP_READ_P(sc->sc_exec.op)) {
198 return BSC_EXEC_STATE_RECV_DATA;
199 }
200
201 return BSC_EXEC_STATE_SEND_DATA;
202
203 case BSC_EXEC_STATE_SEND_DATA:
204 case BSC_EXEC_STATE_RECV_DATA:
205 return BSC_EXEC_STATE_DONE;
206
207 case BSC_EXEC_STATE_DONE:
208 case BSC_EXEC_STATE_ERROR:
209 return sc->sc_exec_state;
210 }
211
212 panic("bsciic_next_state: invalid state: %d", sc->sc_exec_state);
213 }
214
215 #define BSC_EXEC_PHASE_COMPLETE(sc) \
216 ((sc)->sc_exec_state == BSC_EXEC_STATE_ERROR || \
217 (sc)->sc_bufpos == (sc)->sc_buflen)
218
219 static void
bsciic_signal(struct bsciic_softc * const sc)220 bsciic_signal(struct bsciic_softc * const sc)
221 {
222 if ((sc->sc_exec.flags & I2C_F_POLL) == 0) {
223 cv_signal(&sc->sc_intr_wait);
224 }
225 }
226
227 static void
bsciic_phase_done(struct bsciic_softc * const sc)228 bsciic_phase_done(struct bsciic_softc * const sc)
229 {
230 sc->sc_exec_state = bsciic_next_state(sc);
231 (*bsciic_exec_state_data[sc->sc_exec_state].func)(sc);
232 }
233
234 static void
bsciic_abort(struct bsciic_softc * const sc)235 bsciic_abort(struct bsciic_softc * const sc)
236 {
237 sc->sc_exec_state = BSC_EXEC_STATE_ERROR;
238 bsciic_phase_done(sc);
239 }
240
241 int
bsciic_intr(void * v)242 bsciic_intr(void *v)
243 {
244 struct bsciic_softc * const sc = v;
245 uint32_t s;
246
247 bsciic_exec_lock(sc);
248
249 if ((sc->sc_exec.flags & I2C_F_POLL) == 0 &&
250 sc->sc_expecting_interrupt == false) {
251 bsciic_exec_unlock(sc);
252 return 0;
253 }
254
255 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S);
256 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_S,
257 BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE);
258
259 if (s & (BSC_S_CLKT | BSC_S_ERR)) {
260 /*
261 * ERR might be a normal "probing for device" sort
262 * of thing, so don't complain about that one.
263 * Do complain about CLKT, though.
264 */
265 if ((s & BSC_S_CLKT) ||
266 (bsciic_debug && (s & BSC_S_ERR))) {
267 device_printf(sc->sc_dev,
268 "error s=0x%08x, aborting transfer\n", s);
269 }
270 bsciic_abort(sc);
271 goto out;
272 }
273
274 if (BSC_EXEC_STATE_SENDING(sc)) {
275 /*
276 * When transmitting, we need to wait for one final
277 * interrupt after pushing out the last of our data.
278 * Catch that case here and go to the next state.
279 */
280 if (BSC_EXEC_PHASE_COMPLETE(sc)) {
281 bsciic_phase_done(sc);
282 } else {
283 bsciic_txfill(sc);
284 }
285 } else if (BSC_EXEC_STATE_RECEIVING(sc)) {
286 bsciic_rxdrain(sc);
287 /*
288 * If we've received all of the data, go to the next
289 * state now; we might not get another interrupt.
290 */
291 if (BSC_EXEC_PHASE_COMPLETE(sc)) {
292 bsciic_phase_done(sc);
293 }
294 } else {
295 device_printf(sc->sc_dev,
296 "unexpected interrupt: state=%d s=0x%08x\n",
297 sc->sc_exec_state, s);
298 bsciic_abort(sc);
299 }
300
301 out:
302 bsciic_exec_unlock(sc);
303 return (1);
304 }
305
306 static void
bsciic_wait(struct bsciic_softc * const sc,const uint32_t events)307 bsciic_wait(struct bsciic_softc * const sc, const uint32_t events)
308 {
309 if ((sc->sc_exec.flags & I2C_F_POLL) == 0) {
310 return;
311 }
312
313 const uint32_t s_bits =
314 events | BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE;
315 uint32_t s;
316
317 /* sc_intr_lock is not held in this case. */
318
319 for (;;) {
320 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S);
321 if (s & s_bits) {
322 (void) bsciic_intr(sc);
323 }
324 if (BSC_EXEC_PHASE_COMPLETE(sc)) {
325 bsciic_phase_done(sc);
326 }
327 if (sc->sc_exec_state >= BSC_EXEC_STATE_DONE) {
328 return;
329 }
330 delay(1);
331 }
332 }
333
334 static void
bsciic_start(struct bsciic_softc * const sc)335 bsciic_start(struct bsciic_softc * const sc)
336 {
337
338 sc->sc_c_bits = BSC_C_I2CEN | BSC_C_INTD |
339 bsciic_exec_state_data[sc->sc_exec_state].c_bits;
340
341 /* Clear the interrupt-enable bits if we're polling. */
342 if (sc->sc_exec.flags & I2C_F_POLL) {
343 sc->sc_c_bits &= ~(BSC_C_INTD | BSC_C_INTT | BSC_C_INTR);
344 }
345
346 sc->sc_expecting_interrupt =
347 (sc->sc_c_bits & (BSC_C_INTD | BSC_C_INTT | BSC_C_INTR)) ? true
348 : false;
349
350 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_C,
351 sc->sc_c_bits | BSC_C_ST);
352 bsciic_wait(sc, bsciic_exec_state_data[sc->sc_exec_state].s_bits);
353 }
354
355 static void
bsciic_exec_func_idle(struct bsciic_softc * const sc)356 bsciic_exec_func_idle(struct bsciic_softc * const sc)
357 {
358 /* We kick off a transfer by setting the slave address register. */
359 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_A, sc->sc_exec.addr);
360
361 /* Immediately transition to the next state. */
362 bsciic_phase_done(sc);
363 }
364
365 static void
bsciic_exec_func_send_addr(struct bsciic_softc * const sc)366 bsciic_exec_func_send_addr(struct bsciic_softc * const sc)
367 {
368 /* XXX For 10-bit addressing; not implemented yet. */
369 panic("bsciic_exec_func_send_addr is not supposed to be called");
370 }
371
372 static void
bsciic_exec_func_send_cmd(struct bsciic_softc * const sc)373 bsciic_exec_func_send_cmd(struct bsciic_softc * const sc)
374 {
375 sc->sc_buf = __UNCONST(sc->sc_exec.cmdbuf);
376 sc->sc_bufpos = 0;
377 sc->sc_buflen = sc->sc_exec.cmdlen;
378
379 uint32_t dlen = sc->sc_exec.cmdlen;
380 if (! I2C_OP_READ_P(sc->sc_exec.op)) {
381 dlen += sc->sc_exec.datalen;
382 }
383 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_DLEN, dlen);
384
385 bsciic_start(sc);
386 }
387
388 static void
bsciic_exec_func_send_data(struct bsciic_softc * const sc)389 bsciic_exec_func_send_data(struct bsciic_softc * const sc)
390 {
391 sc->sc_buf = sc->sc_exec.databuf;
392 sc->sc_bufpos = 0;
393 sc->sc_buflen = sc->sc_exec.datalen;
394
395 if (sc->sc_exec.cmdlen) {
396 /*
397 * Output has already been started in this case; we just
398 * needed to switch buffers.
399 */
400 bsciic_wait(sc, BSC_S_TXW);
401 } else {
402 uint32_t dlen = sc->sc_exec.datalen;
403 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_DLEN, dlen);
404 bsciic_start(sc);
405 }
406 }
407
408 static void
bsciic_exec_func_recv_data(struct bsciic_softc * const sc)409 bsciic_exec_func_recv_data(struct bsciic_softc * const sc)
410 {
411 sc->sc_buf = sc->sc_exec.databuf;
412 sc->sc_bufpos = 0;
413 sc->sc_buflen = sc->sc_exec.datalen;
414
415 uint32_t dlen = sc->sc_exec.datalen;
416 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_DLEN, dlen);
417
418 bsciic_start(sc);
419 }
420
421 static void
bsciic_exec_func_done(struct bsciic_softc * const sc)422 bsciic_exec_func_done(struct bsciic_softc * const sc)
423 {
424 /* We're done! Disable interrupts. */
425 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_C, BSC_C_I2CEN);
426 sc->sc_expecting_interrupt = false;
427 bsciic_signal(sc);
428 }
429
430 static void
bsciic_exec_func_error(struct bsciic_softc * const sc)431 bsciic_exec_func_error(struct bsciic_softc * const sc)
432 {
433 /* Clear the FIFO and disable interrupts. */
434 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_C,
435 BSC_C_I2CEN | BSC_C_CLEAR_CLEAR);
436 sc->sc_expecting_interrupt = false;
437 bsciic_signal(sc);
438 }
439
440 int
bsciic_exec(void * v,i2c_op_t op,i2c_addr_t addr,const void * cmdbuf,size_t cmdlen,void * databuf,size_t datalen,int flags)441 bsciic_exec(void *v, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf,
442 size_t cmdlen, void *databuf, size_t datalen, int flags)
443 {
444 struct bsciic_softc * const sc = v;
445
446 /* XXX We don't do 10-bit addressing correctly yet. */
447 if (addr > 0x7f)
448 return (ENOTSUP);
449
450 /*
451 * The I2C middle layer has ensured that the client device has
452 * exclusive access to the controller. Copy the parameters
453 * and start the state machine that runs through the necessary
454 * phases of the request.
455 */
456 KASSERT(sc->sc_exec_state == BSC_EXEC_STATE_IDLE);
457 sc->sc_exec.op = op;
458 sc->sc_exec.addr = addr;
459 sc->sc_exec.cmdbuf = cmdbuf;
460 sc->sc_exec.cmdlen = cmdlen;
461 sc->sc_exec.databuf = databuf;
462 sc->sc_exec.datalen = datalen;
463 sc->sc_exec.flags = flags;
464
465 bsciic_exec_lock(sc);
466 (*bsciic_exec_state_data[sc->sc_exec_state].func)(sc);
467 while (sc->sc_exec_state < BSC_EXEC_STATE_DONE) {
468 KASSERT((flags & I2C_F_POLL) == 0);
469 cv_wait(&sc->sc_intr_wait, &sc->sc_intr_lock);
470 }
471 int error = sc->sc_exec_state == BSC_EXEC_STATE_ERROR ? EIO : 0;
472 uint32_t s;
473 do {
474 s = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BSC_S);
475 } while ((s & BSC_S_TA) != 0);
476 if (s & (BSC_S_CLKT | BSC_S_ERR)) {
477 error = EIO;
478 }
479 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_C,
480 BSC_C_I2CEN | BSC_C_CLEAR_CLEAR);
481 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_S,
482 BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE);
483 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BSC_DLEN, 0);
484 bsciic_exec_unlock(sc);
485
486 sc->sc_exec.flags = 0;
487 sc->sc_exec_state = BSC_EXEC_STATE_IDLE;
488 memset(&sc->sc_exec, 0, sizeof(sc->sc_exec));
489
490 return error;
491 }
492