1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Huawei Technologies Co., Ltd 3 */ 4 5 #ifndef _HINIC_PMD_HWDEV_H_ 6 #define _HINIC_PMD_HWDEV_H_ 7 8 #include "hinic_pmd_cmd.h" 9 10 #define HINIC_PAGE_SIZE_MAX 20 11 12 #define HINIC_MGMT_CMD_UNSUPPORTED 0xFF 13 #define HINIC_PF_SET_VF_ALREADY 0x4 14 15 #define MAX_PCIE_DFX_BUF_SIZE 1024 16 17 #define HINIC_DEV_BUSY_ACTIVE_FW 0xFE 18 19 /* dma pool */ 20 struct dma_pool { 21 rte_atomic32_t inuse; 22 size_t elem_size; 23 size_t align; 24 size_t boundary; 25 void *hwdev; 26 27 char name[32]; 28 }; 29 30 enum hinic_res_state { 31 HINIC_RES_CLEAN = 0, 32 HINIC_RES_ACTIVE = 1, 33 }; 34 35 enum hilink_info_print_event { 36 HILINK_EVENT_LINK_UP = 1, 37 HILINK_EVENT_LINK_DOWN, 38 HILINK_EVENT_CABLE_PLUGGED, 39 HILINK_EVENT_MAX_TYPE, 40 }; 41 42 struct hinic_port_link_status { 43 struct hinic_mgmt_msg_head mgmt_msg_head; 44 45 u16 func_id; 46 u8 link; 47 u8 port_id; 48 }; 49 50 enum link_err_status { 51 LINK_ERR_MODULE_UNRECOGENIZED, 52 LINK_ERR_NUM, 53 }; 54 55 struct hinic_cable_plug_event { 56 struct hinic_mgmt_msg_head mgmt_msg_head; 57 58 u16 func_id; 59 u8 plugged; /* 0: unplugged, 1: plugged */ 60 u8 port_id; 61 }; 62 63 struct hinic_link_err_event { 64 struct hinic_mgmt_msg_head mgmt_msg_head; 65 66 u16 func_id; 67 u8 err_type; 68 u8 port_id; 69 }; 70 71 struct hinic_cons_idx_attr { 72 struct hinic_mgmt_msg_head mgmt_msg_head; 73 74 u16 func_idx; 75 u8 dma_attr_off; 76 u8 pending_limit; 77 u8 coalescing_time; 78 u8 intr_en; 79 u16 intr_idx; 80 u32 l2nic_sqn; 81 u32 sq_id; 82 u64 ci_addr; 83 }; 84 85 struct hinic_clear_doorbell { 86 struct hinic_mgmt_msg_head mgmt_msg_head; 87 88 u16 func_idx; 89 u8 ppf_idx; 90 u8 rsvd1; 91 }; 92 93 struct hinic_clear_resource { 94 struct hinic_mgmt_msg_head mgmt_msg_head; 95 96 u16 func_idx; 97 u8 ppf_idx; 98 u8 rsvd1; 99 }; 100 101 struct hinic_cmd_set_res_state { 102 struct hinic_mgmt_msg_head mgmt_msg_head; 103 104 u16 func_idx; 105 u8 state; 106 u8 rsvd1; 107 u32 rsvd2; 108 }; 109 110 struct hinic_l2nic_reset { 111 struct hinic_mgmt_msg_head mgmt_msg_head; 112 113 u16 func_id; 114 u16 rsvd1; 115 }; 116 117 struct hinic_page_size { 118 struct hinic_mgmt_msg_head mgmt_msg_head; 119 120 u16 func_idx; 121 u8 ppf_idx; 122 u8 page_size; 123 u32 rsvd; 124 }; 125 126 struct hinic_msix_config { 127 struct hinic_mgmt_msg_head mgmt_msg_head; 128 129 u16 func_id; 130 u16 msix_index; 131 u8 pending_cnt; 132 u8 coalesct_timer_cnt; 133 u8 lli_tmier_cnt; 134 u8 lli_credit_cnt; 135 u8 resend_timer_cnt; 136 u8 rsvd1[3]; 137 }; 138 139 /* defined by chip */ 140 enum hinic_fault_type { 141 FAULT_TYPE_CHIP, 142 FAULT_TYPE_UCODE, 143 FAULT_TYPE_MEM_RD_TIMEOUT, 144 FAULT_TYPE_MEM_WR_TIMEOUT, 145 FAULT_TYPE_REG_RD_TIMEOUT, 146 FAULT_TYPE_REG_WR_TIMEOUT, 147 FAULT_TYPE_MAX, 148 }; 149 150 /* defined by chip */ 151 enum hinic_fault_err_level { 152 /* default err_level=FAULT_LEVEL_FATAL if 153 * type==FAULT_TYPE_MEM_RD_TIMEOUT || FAULT_TYPE_MEM_WR_TIMEOUT || 154 * FAULT_TYPE_REG_RD_TIMEOUT || FAULT_TYPE_REG_WR_TIMEOUT || 155 * FAULT_TYPE_UCODE 156 * other: err_level in event.chip.err_level if type==FAULT_TYPE_CHIP 157 */ 158 FAULT_LEVEL_FATAL, 159 FAULT_LEVEL_SERIOUS_RESET, 160 FAULT_LEVEL_SERIOUS_FLR, 161 FAULT_LEVEL_GENERAL, 162 FAULT_LEVEL_SUGGESTION, 163 FAULT_LEVEL_MAX 164 }; 165 166 /* defined by chip */ 167 struct hinic_fault_event { 168 /* enum hinic_fault_type */ 169 u8 type; 170 u8 rsvd0[3]; 171 union { 172 u32 val[4]; 173 /* valid only type==FAULT_TYPE_CHIP */ 174 struct { 175 u8 node_id; 176 /* enum hinic_fault_err_level */ 177 u8 err_level; 178 u8 err_type; 179 u8 rsvd1; 180 u32 err_csr_addr; 181 u32 err_csr_value; 182 /* func_id valid only err_level==FAULT_LEVEL_SERIOUS_FLR */ 183 u16 func_id; 184 u16 rsvd2; 185 } chip; 186 187 /* valid only type==FAULT_TYPE_UCODE */ 188 struct { 189 u8 cause_id; 190 u8 core_id; 191 u8 c_id; 192 u8 rsvd3; 193 u32 epc; 194 u32 rsvd4; 195 u32 rsvd5; 196 } ucode; 197 198 /* valid only type==FAULT_TYPE_MEM_RD_TIMEOUT || 199 * FAULT_TYPE_MEM_WR_TIMEOUT 200 */ 201 struct { 202 u32 err_csr_ctrl; 203 u32 err_csr_data; 204 u32 ctrl_tab; 205 u32 mem_index; 206 } mem_timeout; 207 208 /* valid only type==FAULT_TYPE_REG_RD_TIMEOUT || 209 * FAULT_TYPE_REG_WR_TIMEOUT 210 */ 211 struct { 212 u32 err_csr; 213 u32 rsvd6; 214 u32 rsvd7; 215 u32 rsvd8; 216 } reg_timeout; 217 } event; 218 }; 219 220 struct hinic_cmd_fault_event { 221 struct hinic_mgmt_msg_head mgmt_msg_head; 222 223 struct hinic_fault_event event; 224 }; 225 226 struct hinic_mgmt_watchdog_info { 227 struct hinic_mgmt_msg_head mgmt_msg_head; 228 229 u32 curr_time_h; 230 u32 curr_time_l; 231 u32 task_id; 232 u32 rsv; 233 234 u32 reg[13]; 235 u32 pc; 236 u32 lr; 237 u32 cpsr; 238 239 u32 stack_top; 240 u32 stack_bottom; 241 u32 sp; 242 u32 curr_used; 243 u32 peak_used; 244 u32 is_overflow; 245 246 u32 stack_actlen; 247 u8 data[1024]; 248 }; 249 250 struct hinic_pcie_dfx_ntc { 251 struct hinic_mgmt_msg_head mgmt_msg_head; 252 253 int len; 254 u32 rsvd; 255 }; 256 257 struct hinic_pcie_dfx_info { 258 struct hinic_mgmt_msg_head mgmt_msg_head; 259 260 u8 host_id; 261 u8 last; 262 u8 rsvd[2]; 263 u32 offset; 264 265 u8 data[MAX_PCIE_DFX_BUF_SIZE]; 266 }; 267 268 struct ffm_intr_info { 269 u8 node_id; 270 /* error level of the interrupt source */ 271 u8 err_level; 272 /* Classification by interrupt source properties */ 273 u16 err_type; 274 u32 err_csr_addr; 275 u32 err_csr_value; 276 }; 277 278 struct hinic_board_info { 279 u32 board_type; 280 u32 port_num; 281 u32 port_speed; 282 u32 pcie_width; 283 u32 host_num; 284 u32 pf_num; 285 u32 vf_total_num; 286 u32 tile_num; 287 u32 qcm_num; 288 u32 core_num; 289 u32 work_mode; 290 u32 service_mode; 291 u32 pcie_mode; 292 u32 cfg_addr; 293 u32 boot_sel; 294 }; 295 296 struct hinic_comm_board_info { 297 struct hinic_mgmt_msg_head mgmt_msg_head; 298 299 struct hinic_board_info info; 300 301 u32 rsvd1[5]; 302 }; 303 304 struct hi30_ctle_data { 305 u8 ctlebst[3]; 306 u8 ctlecmband[3]; 307 u8 ctlermband[3]; 308 u8 ctleza[3]; 309 u8 ctlesqh[3]; 310 u8 ctleactgn[3]; 311 u8 ctlepassgn; 312 }; 313 314 struct hi30_ffe_data { 315 u8 PRE2; 316 u8 PRE1; 317 u8 POST1; 318 u8 POST2; 319 u8 MAIN; 320 }; 321 322 enum hilink_fec_type { 323 HILINK_FEC_RSFEC, 324 HILINK_FEC_BASEFEC, 325 HILINK_FEC_NOFEC, 326 HILINK_FEC_MAX_TYPE, 327 }; 328 329 enum hinic_link_port_type { 330 LINK_PORT_FIBRE = 1, 331 LINK_PORT_ELECTRIC, 332 LINK_PORT_COPPER, 333 LINK_PORT_AOC, 334 LINK_PORT_BACKPLANE, 335 LINK_PORT_BASET, 336 LINK_PORT_MAX_TYPE, 337 }; 338 339 enum hilink_fibre_subtype { 340 FIBRE_SUBTYPE_SR = 1, 341 FIBRE_SUBTYPE_LR, 342 FIBRE_SUBTYPE_MAX, 343 }; 344 345 struct hinic_link_info { 346 u8 vendor_name[16]; 347 /* port type: 348 * 1 - fiber; 2 - electric; 3 - copper; 4 - AOC; 5 - backplane; 349 * 6 - baseT; 0xffff - unknown 350 * 351 * port subtype: 352 * Only when port_type is fiber: 353 * 1 - SR; 2 - LR 354 */ 355 u32 port_type; 356 u32 port_sub_type; 357 u32 cable_length; 358 u8 cable_temp; 359 u8 cable_max_speed;/* 1(G)/10(G)/25(G)... */ 360 u8 sfp_type; /* 0 - qsfp; 1 - sfp */ 361 u8 rsvd0; 362 u32 power[4]; /* uW; if is sfp, only power[2] is valid */ 363 364 u8 an_state; /* 0 - off; 1 - on */ 365 u8 fec; /* 0 - RSFEC; 1 - BASEFEC; 2 - NOFEC */ 366 u16 speed; /* 1(G)/10(G)/25(G)... */ 367 368 u8 cable_absent; /* 0 - cable present; 1 - cable unpresent */ 369 u8 alos; /* 0 - yes; 1 - no */ 370 u8 rx_los; /* 0 - yes; 1 - no */ 371 u8 pma_status; 372 u32 pma_dbg_info_reg; /* pma debug info: */ 373 u32 pma_signal_ok_reg; /* signal ok: */ 374 375 u32 pcs_err_blk_cnt_reg; /* error block counter: */ 376 u32 rf_lf_status_reg; /* RF/LF status: */ 377 u8 pcs_link_reg; /* pcs link: */ 378 u8 mac_link_reg; /* mac link: */ 379 u8 mac_tx_en; 380 u8 mac_rx_en; 381 u32 pcs_err_cnt; 382 383 u8 lane_used; 384 u8 hi30_ffe[5]; 385 u8 hi30_ctle[19]; 386 u8 hi30_dfe[14]; 387 u8 rsvd4; 388 }; 389 390 struct hinic_hilink_link_info { 391 struct hinic_mgmt_msg_head mgmt_msg_head; 392 393 u16 port_id; 394 u8 info_type; /* 1: link up 2: link down 3 cable plugged */ 395 u8 rsvd1; 396 397 struct hinic_link_info info; 398 399 u8 rsvd2[780]; 400 }; 401 402 /* dma os dependency implementation */ 403 struct hinic_os_dep { 404 /* kernel dma alloc api */ 405 rte_atomic32_t dma_alloc_cnt; 406 rte_spinlock_t dma_hash_lock; 407 struct rte_hash *dma_addr_hash; 408 }; 409 410 struct nic_interrupt_info { 411 u32 lli_set; 412 u32 interrupt_coalesc_set; 413 u16 msix_index; 414 u8 lli_credit_limit; 415 u8 lli_timer_cfg; 416 u8 pending_limt; 417 u8 coalesc_timer_cfg; 418 u8 resend_timer_cfg; 419 }; 420 421 struct hinic_sq_attr { 422 u8 dma_attr_off; 423 u8 pending_limit; 424 u8 coalescing_time; 425 u8 intr_en; 426 u16 intr_idx; 427 u32 l2nic_sqn; 428 /* bit[63:2] is addr's high 62bit, bit[0] is valid flag */ 429 u64 ci_dma_base; 430 }; 431 432 struct hinic_hwdev { 433 struct rte_pci_device *pcidev_hdl; 434 u32 ffm_num; 435 436 /* dma memory allocator */ 437 struct hinic_os_dep os_dep; 438 struct hinic_hwif *hwif; 439 struct cfg_mgmt_info *cfg_mgmt; 440 struct hinic_aeqs *aeqs; 441 struct hinic_mbox_func_to_func *func_to_func; 442 struct hinic_msg_pf_to_mgmt *pf_to_mgmt; 443 struct hinic_cmdqs *cmdqs; 444 struct hinic_nic_io *nic_io; 445 }; 446 447 int hinic_osdep_init(struct hinic_hwdev *hwdev); 448 449 void hinic_osdep_deinit(struct hinic_hwdev *hwdev); 450 451 void dma_free_coherent_volatile(void *hwdev, size_t size, 452 volatile void *virt, dma_addr_t phys); 453 454 int hinic_get_board_info(void *hwdev, struct hinic_board_info *info); 455 456 int hinic_set_ci_table(void *hwdev, u16 q_id, struct hinic_sq_attr *attr); 457 458 int hinic_func_rx_tx_flush(struct hinic_hwdev *hwdev); 459 460 int hinic_set_interrupt_cfg(struct hinic_hwdev *hwdev, 461 struct nic_interrupt_info interrupt_info); 462 463 int init_aeqs_msix_attr(void *hwdev); 464 465 void hinic_comm_async_event_handle(struct hinic_hwdev *hwdev, u8 cmd, 466 void *buf_in, u16 in_size, 467 void *buf_out, u16 *out_size); 468 469 void hinic_l2nic_async_event_handle(struct hinic_hwdev *hwdev, void *param, 470 u8 cmd, void *buf_in, u16 in_size, 471 void *buf_out, u16 *out_size); 472 473 void hinic_hilink_async_event_handle(struct hinic_hwdev *hwdev, u8 cmd, 474 void *buf_in, u16 in_size, void *buf_out, 475 u16 *out_size); 476 477 int hinic_init_attr_table(struct hinic_hwdev *hwdev); 478 479 int hinic_activate_hwdev_state(struct hinic_hwdev *hwdev); 480 481 void hinic_deactivate_hwdev_state(struct hinic_hwdev *hwdev); 482 483 int hinic_l2nic_reset(struct hinic_hwdev *hwdev); 484 485 int hinic_set_pagesize(void *hwdev, u8 page_size); 486 487 void hinic_cpu_to_be32(void *data, u32 len); 488 489 void hinic_be32_to_cpu(void *data, u32 len); 490 491 #endif /* _HINIC_PMD_HWDEV_H_ */ 492