1 /* $NetBSD: thm_10_0_sh_mask.h,v 1.2 2021/12/18 23:45:24 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _thm_10_0_SH_MASK_HEADER 24 #define _thm_10_0_SH_MASK_HEADER 25 26 27 // addressBlock: thm_thm_SmuThmDec 28 //THM_TCON_CUR_TMP 29 #define THM_TCON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0 30 #define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5 31 #define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7 32 #define THM_TCON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8 33 #define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10 34 #define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12 35 #define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13 36 #define THM_TCON_CUR_TMP__MCM_EN__SHIFT 0x14 37 #define THM_TCON_CUR_TMP__CUR_TEMP__SHIFT 0x15 38 #define THM_TCON_CUR_TMP__PER_STEP_TIME_UP_MASK 0x0000001FL 39 #define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP_MASK 0x00000060L 40 #define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN_MASK 0x00000080L 41 #define THM_TCON_CUR_TMP__PER_STEP_TIME_DN_MASK 0x00001F00L 42 #define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL_MASK 0x00030000L 43 #define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL_MASK 0x00040000L 44 #define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK 0x00080000L 45 #define THM_TCON_CUR_TMP__MCM_EN_MASK 0x00100000L 46 #define THM_TCON_CUR_TMP__CUR_TEMP_MASK 0xFFE00000L 47 //THM_TCON_HTC 48 #define THM_TCON_HTC__HTC_EN__SHIFT 0x0 49 #define THM_TCON_HTC__EXTERNAL_PROCHOT__SHIFT 0x2 50 #define THM_TCON_HTC__INTERNAL_PROCHOT__SHIFT 0x3 51 #define THM_TCON_HTC__HTC_ACTIVE__SHIFT 0x4 52 #define THM_TCON_HTC__HTC_ACTIVE_LOG__SHIFT 0x5 53 #define THM_TCON_HTC__HTC_DIAG__SHIFT 0x8 54 #define THM_TCON_HTC__DIS_PROCHOT_PIN__SHIFT 0x9 55 #define THM_TCON_HTC__HTC_TO_IH_EN__SHIFT 0xa 56 #define THM_TCON_HTC__PROCHOT_TO_IH_EN__SHIFT 0xb 57 #define THM_TCON_HTC__PROCHOT_EVENT_SRC__SHIFT 0xc 58 #define THM_TCON_HTC__HTC_TMP_LMT__SHIFT 0x10 59 #define THM_TCON_HTC__HTC_HYST_LMT__SHIFT 0x17 60 #define THM_TCON_HTC__HTC_SLEW_SEL__SHIFT 0x1b 61 #define THM_TCON_HTC__HTC_EN_MASK 0x00000001L 62 #define THM_TCON_HTC__EXTERNAL_PROCHOT_MASK 0x00000004L 63 #define THM_TCON_HTC__INTERNAL_PROCHOT_MASK 0x00000008L 64 #define THM_TCON_HTC__HTC_ACTIVE_MASK 0x00000010L 65 #define THM_TCON_HTC__HTC_ACTIVE_LOG_MASK 0x00000020L 66 #define THM_TCON_HTC__HTC_DIAG_MASK 0x00000100L 67 #define THM_TCON_HTC__DIS_PROCHOT_PIN_MASK 0x00000200L 68 #define THM_TCON_HTC__HTC_TO_IH_EN_MASK 0x00000400L 69 #define THM_TCON_HTC__PROCHOT_TO_IH_EN_MASK 0x00000800L 70 #define THM_TCON_HTC__PROCHOT_EVENT_SRC_MASK 0x00007000L 71 #define THM_TCON_HTC__HTC_TMP_LMT_MASK 0x007F0000L 72 #define THM_TCON_HTC__HTC_HYST_LMT_MASK 0x07800000L 73 #define THM_TCON_HTC__HTC_SLEW_SEL_MASK 0x18000000L 74 //THM_TCON_THERM_TRIP 75 #define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY__SHIFT 0x0 76 #define THM_TCON_THERM_TRIP__THERM_TP__SHIFT 0x1 77 #define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED__SHIFT 0x2 78 #define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT 0x3 79 #define THM_TCON_THERM_TRIP__RSVD2__SHIFT 0x4 80 #define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT 0x5 81 #define THM_TCON_THERM_TRIP__THERM_TP_LMT__SHIFT 0x6 82 #define THM_TCON_THERM_TRIP__RSVD3__SHIFT 0xe 83 #define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT 0x1f 84 #define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY_MASK 0x00000001L 85 #define THM_TCON_THERM_TRIP__THERM_TP_MASK 0x00000002L 86 #define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED_MASK 0x00000004L 87 #define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK 0x00000008L 88 #define THM_TCON_THERM_TRIP__RSVD2_MASK 0x00000010L 89 #define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK 0x00000020L 90 #define THM_TCON_THERM_TRIP__THERM_TP_LMT_MASK 0x00003FC0L 91 #define THM_TCON_THERM_TRIP__RSVD3_MASK 0x7FFFC000L 92 #define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000L 93 //THM_CTF_DELAY 94 #define THM_CTF_DELAY__CTF_DELAY_CNT__SHIFT 0x0 95 #define THM_CTF_DELAY__CTF_DELAY_CNT_MASK 0x000FFFFFL 96 //THM_GPIO_PROCHOT_CTRL 97 #define THM_GPIO_PROCHOT_CTRL__TXIMPSEL__SHIFT 0x0 98 #define THM_GPIO_PROCHOT_CTRL__PD__SHIFT 0x1 99 #define THM_GPIO_PROCHOT_CTRL__PU__SHIFT 0x2 100 #define THM_GPIO_PROCHOT_CTRL__SCHMEN__SHIFT 0x3 101 #define THM_GPIO_PROCHOT_CTRL__S0__SHIFT 0x4 102 #define THM_GPIO_PROCHOT_CTRL__S1__SHIFT 0x5 103 #define THM_GPIO_PROCHOT_CTRL__RXEN__SHIFT 0x6 104 #define THM_GPIO_PROCHOT_CTRL__RXSEL0__SHIFT 0x7 105 #define THM_GPIO_PROCHOT_CTRL__RXSEL1__SHIFT 0x8 106 #define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE__SHIFT 0x10 107 #define THM_GPIO_PROCHOT_CTRL__OE__SHIFT 0x11 108 #define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE__SHIFT 0x12 109 #define THM_GPIO_PROCHOT_CTRL__A__SHIFT 0x13 110 #define THM_GPIO_PROCHOT_CTRL__Y__SHIFT 0x1f 111 #define THM_GPIO_PROCHOT_CTRL__TXIMPSEL_MASK 0x00000001L 112 #define THM_GPIO_PROCHOT_CTRL__PD_MASK 0x00000002L 113 #define THM_GPIO_PROCHOT_CTRL__PU_MASK 0x00000004L 114 #define THM_GPIO_PROCHOT_CTRL__SCHMEN_MASK 0x00000008L 115 #define THM_GPIO_PROCHOT_CTRL__S0_MASK 0x00000010L 116 #define THM_GPIO_PROCHOT_CTRL__S1_MASK 0x00000020L 117 #define THM_GPIO_PROCHOT_CTRL__RXEN_MASK 0x00000040L 118 #define THM_GPIO_PROCHOT_CTRL__RXSEL0_MASK 0x00000080L 119 #define THM_GPIO_PROCHOT_CTRL__RXSEL1_MASK 0x00000100L 120 #define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE_MASK 0x00010000L 121 #define THM_GPIO_PROCHOT_CTRL__OE_MASK 0x00020000L 122 #define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE_MASK 0x00040000L 123 #define THM_GPIO_PROCHOT_CTRL__A_MASK 0x00080000L 124 #define THM_GPIO_PROCHOT_CTRL__Y_MASK 0x80000000L 125 //THM_THERMAL_INT_ENA 126 #define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 127 #define THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 128 #define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 129 #define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 130 #define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 131 #define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 132 #define THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x00000001L 133 #define THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x00000002L 134 #define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x00000004L 135 #define THM_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x00000008L 136 #define THM_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x00000010L 137 #define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x00000020L 138 //THM_THERMAL_INT_CTRL 139 #define THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 140 #define THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 141 #define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD__SHIFT 0x10 142 #define THM_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 143 #define THM_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 144 #define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a 145 #define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK__SHIFT 0x1b 146 #define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT 0x1c 147 #define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT 0x1d 148 #define THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0x000000FFL 149 #define THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0x0000FF00L 150 #define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD_MASK 0x00FF0000L 151 #define THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x01000000L 152 #define THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x02000000L 153 #define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x04000000L 154 #define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK_MASK 0x08000000L 155 #define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK 0x10000000L 156 #define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK 0xE0000000L 157 //THM_THERMAL_INT_STATUS 158 #define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 159 #define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 160 #define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 161 #define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT__SHIFT 0x3 162 #define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x00000001L 163 #define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x00000002L 164 #define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x00000004L 165 #define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT_MASK 0x00000008L 166 //THM_TMON0_RDIL0_DATA 167 #define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0 168 #define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb 169 #define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc 170 #define THM_TMON0_RDIL0_DATA__Z_MASK 0x000007FFL 171 #define THM_TMON0_RDIL0_DATA__VALID_MASK 0x00000800L 172 #define THM_TMON0_RDIL0_DATA__TEMP_MASK 0x00FFF000L 173 //THM_TMON0_RDIL1_DATA 174 #define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0 175 #define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb 176 #define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc 177 #define THM_TMON0_RDIL1_DATA__Z_MASK 0x000007FFL 178 #define THM_TMON0_RDIL1_DATA__VALID_MASK 0x00000800L 179 #define THM_TMON0_RDIL1_DATA__TEMP_MASK 0x00FFF000L 180 //THM_TMON0_RDIL2_DATA 181 #define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0 182 #define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb 183 #define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc 184 #define THM_TMON0_RDIL2_DATA__Z_MASK 0x000007FFL 185 #define THM_TMON0_RDIL2_DATA__VALID_MASK 0x00000800L 186 #define THM_TMON0_RDIL2_DATA__TEMP_MASK 0x00FFF000L 187 //THM_TMON0_RDIL3_DATA 188 #define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0 189 #define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb 190 #define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc 191 #define THM_TMON0_RDIL3_DATA__Z_MASK 0x000007FFL 192 #define THM_TMON0_RDIL3_DATA__VALID_MASK 0x00000800L 193 #define THM_TMON0_RDIL3_DATA__TEMP_MASK 0x00FFF000L 194 //THM_TMON0_RDIL4_DATA 195 #define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0 196 #define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb 197 #define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc 198 #define THM_TMON0_RDIL4_DATA__Z_MASK 0x000007FFL 199 #define THM_TMON0_RDIL4_DATA__VALID_MASK 0x00000800L 200 #define THM_TMON0_RDIL4_DATA__TEMP_MASK 0x00FFF000L 201 //THM_TMON0_RDIL5_DATA 202 #define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0 203 #define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb 204 #define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc 205 #define THM_TMON0_RDIL5_DATA__Z_MASK 0x000007FFL 206 #define THM_TMON0_RDIL5_DATA__VALID_MASK 0x00000800L 207 #define THM_TMON0_RDIL5_DATA__TEMP_MASK 0x00FFF000L 208 //THM_TMON0_RDIL6_DATA 209 #define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0 210 #define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb 211 #define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc 212 #define THM_TMON0_RDIL6_DATA__Z_MASK 0x000007FFL 213 #define THM_TMON0_RDIL6_DATA__VALID_MASK 0x00000800L 214 #define THM_TMON0_RDIL6_DATA__TEMP_MASK 0x00FFF000L 215 //THM_TMON0_RDIL7_DATA 216 #define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0 217 #define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb 218 #define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc 219 #define THM_TMON0_RDIL7_DATA__Z_MASK 0x000007FFL 220 #define THM_TMON0_RDIL7_DATA__VALID_MASK 0x00000800L 221 #define THM_TMON0_RDIL7_DATA__TEMP_MASK 0x00FFF000L 222 //THM_TMON0_RDIL8_DATA 223 #define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0 224 #define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb 225 #define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc 226 #define THM_TMON0_RDIL8_DATA__Z_MASK 0x000007FFL 227 #define THM_TMON0_RDIL8_DATA__VALID_MASK 0x00000800L 228 #define THM_TMON0_RDIL8_DATA__TEMP_MASK 0x00FFF000L 229 //THM_TMON0_RDIL9_DATA 230 #define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0 231 #define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb 232 #define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc 233 #define THM_TMON0_RDIL9_DATA__Z_MASK 0x000007FFL 234 #define THM_TMON0_RDIL9_DATA__VALID_MASK 0x00000800L 235 #define THM_TMON0_RDIL9_DATA__TEMP_MASK 0x00FFF000L 236 //THM_TMON0_RDIL10_DATA 237 #define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0 238 #define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb 239 #define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc 240 #define THM_TMON0_RDIL10_DATA__Z_MASK 0x000007FFL 241 #define THM_TMON0_RDIL10_DATA__VALID_MASK 0x00000800L 242 #define THM_TMON0_RDIL10_DATA__TEMP_MASK 0x00FFF000L 243 //THM_TMON0_RDIL11_DATA 244 #define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0 245 #define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb 246 #define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc 247 #define THM_TMON0_RDIL11_DATA__Z_MASK 0x000007FFL 248 #define THM_TMON0_RDIL11_DATA__VALID_MASK 0x00000800L 249 #define THM_TMON0_RDIL11_DATA__TEMP_MASK 0x00FFF000L 250 //THM_TMON0_RDIL12_DATA 251 #define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0 252 #define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb 253 #define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc 254 #define THM_TMON0_RDIL12_DATA__Z_MASK 0x000007FFL 255 #define THM_TMON0_RDIL12_DATA__VALID_MASK 0x00000800L 256 #define THM_TMON0_RDIL12_DATA__TEMP_MASK 0x00FFF000L 257 //THM_TMON0_RDIL13_DATA 258 #define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0 259 #define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb 260 #define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc 261 #define THM_TMON0_RDIL13_DATA__Z_MASK 0x000007FFL 262 #define THM_TMON0_RDIL13_DATA__VALID_MASK 0x00000800L 263 #define THM_TMON0_RDIL13_DATA__TEMP_MASK 0x00FFF000L 264 //THM_TMON0_RDIL14_DATA 265 #define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0 266 #define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb 267 #define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc 268 #define THM_TMON0_RDIL14_DATA__Z_MASK 0x000007FFL 269 #define THM_TMON0_RDIL14_DATA__VALID_MASK 0x00000800L 270 #define THM_TMON0_RDIL14_DATA__TEMP_MASK 0x00FFF000L 271 //THM_TMON0_RDIL15_DATA 272 #define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0 273 #define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb 274 #define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc 275 #define THM_TMON0_RDIL15_DATA__Z_MASK 0x000007FFL 276 #define THM_TMON0_RDIL15_DATA__VALID_MASK 0x00000800L 277 #define THM_TMON0_RDIL15_DATA__TEMP_MASK 0x00FFF000L 278 //THM_TMON0_RDIR0_DATA 279 #define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0 280 #define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb 281 #define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc 282 #define THM_TMON0_RDIR0_DATA__Z_MASK 0x000007FFL 283 #define THM_TMON0_RDIR0_DATA__VALID_MASK 0x00000800L 284 #define THM_TMON0_RDIR0_DATA__TEMP_MASK 0x00FFF000L 285 //THM_TMON0_RDIR1_DATA 286 #define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0 287 #define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb 288 #define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc 289 #define THM_TMON0_RDIR1_DATA__Z_MASK 0x000007FFL 290 #define THM_TMON0_RDIR1_DATA__VALID_MASK 0x00000800L 291 #define THM_TMON0_RDIR1_DATA__TEMP_MASK 0x00FFF000L 292 //THM_TMON0_RDIR2_DATA 293 #define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0 294 #define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb 295 #define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc 296 #define THM_TMON0_RDIR2_DATA__Z_MASK 0x000007FFL 297 #define THM_TMON0_RDIR2_DATA__VALID_MASK 0x00000800L 298 #define THM_TMON0_RDIR2_DATA__TEMP_MASK 0x00FFF000L 299 //THM_TMON0_RDIR3_DATA 300 #define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0 301 #define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb 302 #define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc 303 #define THM_TMON0_RDIR3_DATA__Z_MASK 0x000007FFL 304 #define THM_TMON0_RDIR3_DATA__VALID_MASK 0x00000800L 305 #define THM_TMON0_RDIR3_DATA__TEMP_MASK 0x00FFF000L 306 //THM_TMON0_RDIR4_DATA 307 #define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0 308 #define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb 309 #define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc 310 #define THM_TMON0_RDIR4_DATA__Z_MASK 0x000007FFL 311 #define THM_TMON0_RDIR4_DATA__VALID_MASK 0x00000800L 312 #define THM_TMON0_RDIR4_DATA__TEMP_MASK 0x00FFF000L 313 //THM_TMON0_RDIR5_DATA 314 #define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0 315 #define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb 316 #define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc 317 #define THM_TMON0_RDIR5_DATA__Z_MASK 0x000007FFL 318 #define THM_TMON0_RDIR5_DATA__VALID_MASK 0x00000800L 319 #define THM_TMON0_RDIR5_DATA__TEMP_MASK 0x00FFF000L 320 //THM_TMON0_RDIR6_DATA 321 #define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0 322 #define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb 323 #define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc 324 #define THM_TMON0_RDIR6_DATA__Z_MASK 0x000007FFL 325 #define THM_TMON0_RDIR6_DATA__VALID_MASK 0x00000800L 326 #define THM_TMON0_RDIR6_DATA__TEMP_MASK 0x00FFF000L 327 //THM_TMON0_RDIR7_DATA 328 #define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0 329 #define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb 330 #define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc 331 #define THM_TMON0_RDIR7_DATA__Z_MASK 0x000007FFL 332 #define THM_TMON0_RDIR7_DATA__VALID_MASK 0x00000800L 333 #define THM_TMON0_RDIR7_DATA__TEMP_MASK 0x00FFF000L 334 //THM_TMON0_RDIR8_DATA 335 #define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0 336 #define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb 337 #define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc 338 #define THM_TMON0_RDIR8_DATA__Z_MASK 0x000007FFL 339 #define THM_TMON0_RDIR8_DATA__VALID_MASK 0x00000800L 340 #define THM_TMON0_RDIR8_DATA__TEMP_MASK 0x00FFF000L 341 //THM_TMON0_RDIR9_DATA 342 #define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0 343 #define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb 344 #define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc 345 #define THM_TMON0_RDIR9_DATA__Z_MASK 0x000007FFL 346 #define THM_TMON0_RDIR9_DATA__VALID_MASK 0x00000800L 347 #define THM_TMON0_RDIR9_DATA__TEMP_MASK 0x00FFF000L 348 //THM_TMON0_RDIR10_DATA 349 #define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0 350 #define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb 351 #define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc 352 #define THM_TMON0_RDIR10_DATA__Z_MASK 0x000007FFL 353 #define THM_TMON0_RDIR10_DATA__VALID_MASK 0x00000800L 354 #define THM_TMON0_RDIR10_DATA__TEMP_MASK 0x00FFF000L 355 //THM_TMON0_RDIR11_DATA 356 #define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0 357 #define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb 358 #define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc 359 #define THM_TMON0_RDIR11_DATA__Z_MASK 0x000007FFL 360 #define THM_TMON0_RDIR11_DATA__VALID_MASK 0x00000800L 361 #define THM_TMON0_RDIR11_DATA__TEMP_MASK 0x00FFF000L 362 //THM_TMON0_RDIR12_DATA 363 #define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0 364 #define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb 365 #define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc 366 #define THM_TMON0_RDIR12_DATA__Z_MASK 0x000007FFL 367 #define THM_TMON0_RDIR12_DATA__VALID_MASK 0x00000800L 368 #define THM_TMON0_RDIR12_DATA__TEMP_MASK 0x00FFF000L 369 //THM_TMON0_RDIR13_DATA 370 #define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0 371 #define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb 372 #define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc 373 #define THM_TMON0_RDIR13_DATA__Z_MASK 0x000007FFL 374 #define THM_TMON0_RDIR13_DATA__VALID_MASK 0x00000800L 375 #define THM_TMON0_RDIR13_DATA__TEMP_MASK 0x00FFF000L 376 //THM_TMON0_RDIR14_DATA 377 #define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0 378 #define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb 379 #define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc 380 #define THM_TMON0_RDIR14_DATA__Z_MASK 0x000007FFL 381 #define THM_TMON0_RDIR14_DATA__VALID_MASK 0x00000800L 382 #define THM_TMON0_RDIR14_DATA__TEMP_MASK 0x00FFF000L 383 //THM_TMON0_RDIR15_DATA 384 #define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0 385 #define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb 386 #define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc 387 #define THM_TMON0_RDIR15_DATA__Z_MASK 0x000007FFL 388 #define THM_TMON0_RDIR15_DATA__VALID_MASK 0x00000800L 389 #define THM_TMON0_RDIR15_DATA__TEMP_MASK 0x00FFF000L 390 //THM_TMON0_INT_DATA 391 #define THM_TMON0_INT_DATA__Z__SHIFT 0x0 392 #define THM_TMON0_INT_DATA__VALID__SHIFT 0xb 393 #define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc 394 #define THM_TMON0_INT_DATA__Z_MASK 0x000007FFL 395 #define THM_TMON0_INT_DATA__VALID_MASK 0x00000800L 396 #define THM_TMON0_INT_DATA__TEMP_MASK 0x00FFF000L 397 //THM_TMON0_CTRL 398 #define THM_TMON0_CTRL__POWER_DOWN__SHIFT 0x0 399 #define THM_TMON0_CTRL__BGADJ__SHIFT 0x1 400 #define THM_TMON0_CTRL__BGADJ_MODE__SHIFT 0x9 401 #define THM_TMON0_CTRL__TMON_PAUSE__SHIFT 0xa 402 #define THM_TMON0_CTRL__INT_MEAS_EN__SHIFT 0xb 403 #define THM_TMON0_CTRL__DEBUG_MODE__SHIFT 0xc 404 #define THM_TMON0_CTRL__EN_CFG_SERDES__SHIFT 0xd 405 #define THM_TMON0_CTRL__POWER_DOWN_MASK 0x00000001L 406 #define THM_TMON0_CTRL__BGADJ_MASK 0x000001FEL 407 #define THM_TMON0_CTRL__BGADJ_MODE_MASK 0x00000200L 408 #define THM_TMON0_CTRL__TMON_PAUSE_MASK 0x00000400L 409 #define THM_TMON0_CTRL__INT_MEAS_EN_MASK 0x00000800L 410 #define THM_TMON0_CTRL__DEBUG_MODE_MASK 0x00001000L 411 #define THM_TMON0_CTRL__EN_CFG_SERDES_MASK 0x00002000L 412 //THM_TMON0_CTRL2 413 #define THM_TMON0_CTRL2__RDIL_PRESENT__SHIFT 0x0 414 #define THM_TMON0_CTRL2__RDIR_PRESENT__SHIFT 0x10 415 #define THM_TMON0_CTRL2__RDIL_PRESENT_MASK 0x0000FFFFL 416 #define THM_TMON0_CTRL2__RDIR_PRESENT_MASK 0xFFFF0000L 417 //THM_TMON0_DEBUG 418 #define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0 419 #define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5 420 #define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x0000001FL 421 #define THM_TMON0_DEBUG__DEBUG_Z_MASK 0x0000FFE0L 422 //THM_DIE1_TEMP 423 #define THM_DIE1_TEMP__TEMP__SHIFT 0x0 424 #define THM_DIE1_TEMP__VALID__SHIFT 0xb 425 #define THM_DIE1_TEMP__TEMP_MASK 0x000007FFL 426 #define THM_DIE1_TEMP__VALID_MASK 0x00000800L 427 //THM_DIE2_TEMP 428 #define THM_DIE2_TEMP__TEMP__SHIFT 0x0 429 #define THM_DIE2_TEMP__VALID__SHIFT 0xb 430 #define THM_DIE2_TEMP__TEMP_MASK 0x000007FFL 431 #define THM_DIE2_TEMP__VALID_MASK 0x00000800L 432 //THM_DIE3_TEMP 433 #define THM_DIE3_TEMP__TEMP__SHIFT 0x0 434 #define THM_DIE3_TEMP__VALID__SHIFT 0xb 435 #define THM_DIE3_TEMP__TEMP_MASK 0x000007FFL 436 #define THM_DIE3_TEMP__VALID_MASK 0x00000800L 437 //THM_SW_TEMP 438 #define THM_SW_TEMP__SW_TEMP__SHIFT 0x0 439 #define THM_SW_TEMP__SW_TEMP_MASK 0x000001FFL 440 //CG_MULT_THERMAL_CTRL 441 #define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0 442 #define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4 443 #define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9 444 #define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14 445 #define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0x0000000FL 446 #define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0x000001F0L 447 #define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x00000200L 448 #define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0x0FF00000L 449 //CG_MULT_THERMAL_STATUS 450 #define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0 451 #define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9 452 #define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x000001FFL 453 #define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x0003FE00L 454 //CG_THERMAL_RANGE 455 #define CG_THERMAL_RANGE__ASIC_T_MAX__SHIFT 0x0 456 #define CG_THERMAL_RANGE__ASIC_T_MIN__SHIFT 0x10 457 #define CG_THERMAL_RANGE__ASIC_T_MAX_MASK 0x000001FFL 458 #define CG_THERMAL_RANGE__ASIC_T_MIN_MASK 0x01FF0000L 459 //THM_TMON_CONFIG 460 #define THM_TMON_CONFIG__NUM_ACQ__SHIFT 0x0 461 #define THM_TMON_CONFIG__FORCE_MAX_ACQ__SHIFT 0x3 462 #define THM_TMON_CONFIG__RDI_INTERLEAVE__SHIFT 0x4 463 #define THM_TMON_CONFIG__CONFIG_SOURCE__SHIFT 0x5 464 #define THM_TMON_CONFIG__RE_CALIB_EN__SHIFT 0x6 465 #define THM_TMON_CONFIG__Z__SHIFT 0x15 466 #define THM_TMON_CONFIG__NUM_ACQ_MASK 0x00000007L 467 #define THM_TMON_CONFIG__FORCE_MAX_ACQ_MASK 0x00000008L 468 #define THM_TMON_CONFIG__RDI_INTERLEAVE_MASK 0x00000010L 469 #define THM_TMON_CONFIG__CONFIG_SOURCE_MASK 0x00000020L 470 #define THM_TMON_CONFIG__RE_CALIB_EN_MASK 0x00000040L 471 #define THM_TMON_CONFIG__Z_MASK 0xFFE00000L 472 //THM_TMON_CONFIG2 473 #define THM_TMON_CONFIG2__A__SHIFT 0x0 474 #define THM_TMON_CONFIG2__B__SHIFT 0xc 475 #define THM_TMON_CONFIG2__C__SHIFT 0x12 476 #define THM_TMON_CONFIG2__K__SHIFT 0x1d 477 #define THM_TMON_CONFIG2__A_MASK 0x00000FFFL 478 #define THM_TMON_CONFIG2__B_MASK 0x0003F000L 479 #define THM_TMON_CONFIG2__C_MASK 0x1FFC0000L 480 #define THM_TMON_CONFIG2__K_MASK 0x20000000L 481 //THM_TMON0_COEFF 482 #define THM_TMON0_COEFF__C_OFFSET__SHIFT 0x0 483 #define THM_TMON0_COEFF__D__SHIFT 0xb 484 #define THM_TMON0_COEFF__C_OFFSET_MASK 0x000007FFL 485 #define THM_TMON0_COEFF__D_MASK 0x0003F800L 486 //THM_TCON_LOCAL0 487 #define THM_TCON_LOCAL0__TMON0_PwrDn_Dis__SHIFT 0x1 488 #define THM_TCON_LOCAL0__TMON1_PwrDn_Dis__SHIFT 0x2 489 #define THM_TCON_LOCAL0__TMON0_PwrDn_Dis_MASK 0x00000002L 490 #define THM_TCON_LOCAL0__TMON1_PwrDn_Dis_MASK 0x00000004L 491 //THM_TCON_LOCAL1 492 #define THM_TCON_LOCAL1__Turn_Off_TMON0__SHIFT 0x0 493 #define THM_TCON_LOCAL1__Turn_Off_TMON1__SHIFT 0x1 494 #define THM_TCON_LOCAL1__PowerDownTmon0__SHIFT 0x4 495 #define THM_TCON_LOCAL1__PowerDownTmon1__SHIFT 0x5 496 #define THM_TCON_LOCAL1__Turn_Off_TMON0_MASK 0x00000001L 497 #define THM_TCON_LOCAL1__Turn_Off_TMON1_MASK 0x00000002L 498 #define THM_TCON_LOCAL1__PowerDownTmon0_MASK 0x00000010L 499 #define THM_TCON_LOCAL1__PowerDownTmon1_MASK 0x00000020L 500 //THM_TCON_LOCAL2 501 #define THM_TCON_LOCAL2__TMON_init_delay__SHIFT 0x0 502 #define THM_TCON_LOCAL2__TMON_pwrup_stagger_time__SHIFT 0x2 503 #define THM_TCON_LOCAL2__short_stagger_count__SHIFT 0x5 504 #define THM_TCON_LOCAL2__sbtsi_use_corrected__SHIFT 0x6 505 #define THM_TCON_LOCAL2__temp_read_skip_scale__SHIFT 0xa 506 #define THM_TCON_LOCAL2__skip_scale_correction__SHIFT 0xb 507 #define THM_TCON_LOCAL2__TMON_init_delay_MASK 0x00000003L 508 #define THM_TCON_LOCAL2__TMON_pwrup_stagger_time_MASK 0x0000000CL 509 #define THM_TCON_LOCAL2__short_stagger_count_MASK 0x00000020L 510 #define THM_TCON_LOCAL2__sbtsi_use_corrected_MASK 0x00000040L 511 #define THM_TCON_LOCAL2__temp_read_skip_scale_MASK 0x00000400L 512 #define THM_TCON_LOCAL2__skip_scale_correction_MASK 0x00000800L 513 //THM_TCON_LOCAL3 514 #define THM_TCON_LOCAL3__Global_TMAX__SHIFT 0x0 515 #define THM_TCON_LOCAL3__Global_TMAX_MASK 0x000007FFL 516 //THM_TCON_LOCAL4 517 #define THM_TCON_LOCAL4__Global_TMAX_ID__SHIFT 0x0 518 #define THM_TCON_LOCAL4__Global_TMAX_ID_MASK 0x000000FFL 519 //THM_TCON_LOCAL5 520 #define THM_TCON_LOCAL5__Global_TMIN__SHIFT 0x0 521 #define THM_TCON_LOCAL5__Global_TMIN_MASK 0x000007FFL 522 //THM_TCON_LOCAL6 523 #define THM_TCON_LOCAL6__Global_TMIN_ID__SHIFT 0x0 524 #define THM_TCON_LOCAL6__Global_TMIN_ID_MASK 0x000000FFL 525 //THM_TCON_LOCAL7 526 #define THM_TCON_LOCAL7__THERMID__SHIFT 0x0 527 #define THM_TCON_LOCAL7__THERMID_MASK 0x000000FFL 528 //THM_TCON_LOCAL8 529 #define THM_TCON_LOCAL8__THERMMAX__SHIFT 0x0 530 #define THM_TCON_LOCAL8__THERMMAX_MASK 0x000007FFL 531 //THM_TCON_LOCAL9 532 #define THM_TCON_LOCAL9__Tj_Max_TMON0__SHIFT 0x0 533 #define THM_TCON_LOCAL9__Tj_Max_TMON0_MASK 0x000007FFL 534 //THM_TCON_LOCAL10 535 #define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID__SHIFT 0x0 536 #define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID_MASK 0x000000FFL 537 //THM_TCON_LOCAL11 538 #define THM_TCON_LOCAL11__Tj_Max_TMON1__SHIFT 0x0 539 #define THM_TCON_LOCAL11__Tj_Max_TMON1_MASK 0x000007FFL 540 //THM_TCON_LOCAL12 541 #define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID__SHIFT 0x0 542 #define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID_MASK 0x000000FFL 543 //THM_TCON_LOCAL13 544 #define THM_TCON_LOCAL13__boot_done__SHIFT 0x0 545 #define THM_TCON_LOCAL13__boot_done_MASK 0x00000001L 546 //THM_PWRMGT 547 #define THM_PWRMGT__SBTSI_SBRMI_CLK_GATE_EN__SHIFT 0x0 548 #define THM_PWRMGT__SBAXI_CLK_GATE_EN__SHIFT 0x1 549 #define THM_PWRMGT__SB_CLK_GATE_MAX_CNT__SHIFT 0x8 550 #define THM_PWRMGT__SBTSI_SBRMI_CLK_GATE_EN_MASK 0x00000001L 551 #define THM_PWRMGT__SBAXI_CLK_GATE_EN_MASK 0x00000002L 552 #define THM_PWRMGT__SB_CLK_GATE_MAX_CNT_MASK 0x00FFFF00L 553 //SMUSBI_SBIREGADDR 554 #define SMUSBI_SBIREGADDR__SBI_REGADDR__SHIFT 0x0 555 #define SMUSBI_SBIREGADDR__SBI_REGADDR_MASK 0x000007FFL 556 //SMUSBI_SBIREGDATA 557 #define SMUSBI_SBIREGDATA__SBI_REGDATA__SHIFT 0x0 558 #define SMUSBI_SBIREGDATA__SBI_REGDATA_MASK 0xFFFFFFFFL 559 //SMUSBI_ERRATA_STAT_REG 560 #define SMUSBI_ERRATA_STAT_REG__ERRATA_STAT_REG__SHIFT 0x0 561 #define SMUSBI_ERRATA_STAT_REG__ERRATA_STAT_REG_MASK 0xFFFFFFFFL 562 //SMUSBI_SBICTRL 563 #define SMUSBI_SBICTRL__CK_SPRSBIWRDONE__SHIFT 0x0 564 #define SMUSBI_SBICTRL__NB_SBISELECT__SHIFT 0x1 565 #define SMUSBI_SBICTRL__NB_SBIADDR__SHIFT 0x2 566 #define SMUSBI_SBICTRL__NB_SBIADDR_OVERRIDE__SHIFT 0x5 567 #define SMUSBI_SBICTRL__CK_SPRSBIWRDONE_MASK 0x00000001L 568 #define SMUSBI_SBICTRL__NB_SBISELECT_MASK 0x00000002L 569 #define SMUSBI_SBICTRL__NB_SBIADDR_MASK 0x0000001CL 570 #define SMUSBI_SBICTRL__NB_SBIADDR_OVERRIDE_MASK 0x00000020L 571 //SMUSBI_CKNBIRESET 572 #define SMUSBI_CKNBIRESET__CKNBIRESET__SHIFT 0x0 573 #define SMUSBI_CKNBIRESET__CKNBIRESET_MASK 0x00000001L 574 //SMUSBI_TIMING 575 #define SMUSBI_TIMING__SETUP_TIME__SHIFT 0x0 576 #define SMUSBI_TIMING__SETUP_TIME_OVERRIDE__SHIFT 0x8 577 #define SMUSBI_TIMING__HOLD_TIME__SHIFT 0x10 578 #define SMUSBI_TIMING__HOLD_TIME_OVERRIDE__SHIFT 0x18 579 #define SMUSBI_TIMING__SETUP_TIME_MASK 0x0000003FL 580 #define SMUSBI_TIMING__SETUP_TIME_OVERRIDE_MASK 0x00000100L 581 #define SMUSBI_TIMING__HOLD_TIME_MASK 0x00FF0000L 582 #define SMUSBI_TIMING__HOLD_TIME_OVERRIDE_MASK 0x01000000L 583 //SMUSBI_HS_TIMING 584 #define SMUSBI_HS_TIMING__HS_SETUP_TIME__SHIFT 0x0 585 #define SMUSBI_HS_TIMING__HS_SETUP_TIME_OVERRIDE__SHIFT 0x8 586 #define SMUSBI_HS_TIMING__HS_HOLD_TIME__SHIFT 0x10 587 #define SMUSBI_HS_TIMING__HS_HOLD_TIME_OVERRIDE__SHIFT 0x18 588 #define SMUSBI_HS_TIMING__HS_SETUP_TIME_MASK 0x0000003FL 589 #define SMUSBI_HS_TIMING__HS_SETUP_TIME_OVERRIDE_MASK 0x00000100L 590 #define SMUSBI_HS_TIMING__HS_HOLD_TIME_MASK 0x00FF0000L 591 #define SMUSBI_HS_TIMING__HS_HOLD_TIME_OVERRIDE_MASK 0x01000000L 592 //SBTSI_REMOTE_TEMP 593 #define SBTSI_REMOTE_TEMP__RemoteTcenSensor__SHIFT 0x0 594 #define SBTSI_REMOTE_TEMP__RemoteTcenSensorId__SHIFT 0xb 595 #define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid__SHIFT 0x13 596 #define SBTSI_REMOTE_TEMP__RemoteTcenSensor_MASK 0x000007FFL 597 #define SBTSI_REMOTE_TEMP__RemoteTcenSensorId_MASK 0x0007F800L 598 #define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid_MASK 0x00080000L 599 //SBRMI_CONTROL 600 #define SBRMI_CONTROL__READ_CMD_INT_DIS__SHIFT 0x0 601 #define SBRMI_CONTROL__DPD__SHIFT 0x1 602 #define SBRMI_CONTROL__DbrdySts__SHIFT 0x2 603 #define SBRMI_CONTROL__READ_CMD_INT_DIS_MASK 0x00000001L 604 #define SBRMI_CONTROL__DPD_MASK 0x00000002L 605 #define SBRMI_CONTROL__DbrdySts_MASK 0x00000004L 606 //SBRMI_COMMAND 607 #define SBRMI_COMMAND__Command__SHIFT 0x0 608 #define SBRMI_COMMAND__WrDataLen__SHIFT 0x8 609 #define SBRMI_COMMAND__RdDataLen__SHIFT 0x10 610 #define SBRMI_COMMAND__CommandSent__SHIFT 0x18 611 #define SBRMI_COMMAND__CommandNotSupported__SHIFT 0x19 612 #define SBRMI_COMMAND__CommandAborted__SHIFT 0x1a 613 #define SBRMI_COMMAND__Status__SHIFT 0x1c 614 #define SBRMI_COMMAND__Command_MASK 0x000000FFL 615 #define SBRMI_COMMAND__WrDataLen_MASK 0x0000FF00L 616 #define SBRMI_COMMAND__RdDataLen_MASK 0x00FF0000L 617 #define SBRMI_COMMAND__CommandSent_MASK 0x01000000L 618 #define SBRMI_COMMAND__CommandNotSupported_MASK 0x02000000L 619 #define SBRMI_COMMAND__CommandAborted_MASK 0x04000000L 620 #define SBRMI_COMMAND__Status_MASK 0xF0000000L 621 //SBRMI_WRITE_DATA0 622 #define SBRMI_WRITE_DATA0__WrByte0__SHIFT 0x0 623 #define SBRMI_WRITE_DATA0__WrByte1__SHIFT 0x8 624 #define SBRMI_WRITE_DATA0__WrByte2__SHIFT 0x10 625 #define SBRMI_WRITE_DATA0__WrByte3__SHIFT 0x18 626 #define SBRMI_WRITE_DATA0__WrByte0_MASK 0x000000FFL 627 #define SBRMI_WRITE_DATA0__WrByte1_MASK 0x0000FF00L 628 #define SBRMI_WRITE_DATA0__WrByte2_MASK 0x00FF0000L 629 #define SBRMI_WRITE_DATA0__WrByte3_MASK 0xFF000000L 630 //SBRMI_WRITE_DATA1 631 #define SBRMI_WRITE_DATA1__WrByte4__SHIFT 0x0 632 #define SBRMI_WRITE_DATA1__WrByte5__SHIFT 0x8 633 #define SBRMI_WRITE_DATA1__WrByte6__SHIFT 0x10 634 #define SBRMI_WRITE_DATA1__WrByte7__SHIFT 0x18 635 #define SBRMI_WRITE_DATA1__WrByte4_MASK 0x000000FFL 636 #define SBRMI_WRITE_DATA1__WrByte5_MASK 0x0000FF00L 637 #define SBRMI_WRITE_DATA1__WrByte6_MASK 0x00FF0000L 638 #define SBRMI_WRITE_DATA1__WrByte7_MASK 0xFF000000L 639 //SBRMI_WRITE_DATA2 640 #define SBRMI_WRITE_DATA2__WrByte8__SHIFT 0x0 641 #define SBRMI_WRITE_DATA2__WrByte9__SHIFT 0x8 642 #define SBRMI_WRITE_DATA2__WrByte10__SHIFT 0x10 643 #define SBRMI_WRITE_DATA2__WrByte11__SHIFT 0x18 644 #define SBRMI_WRITE_DATA2__WrByte8_MASK 0x000000FFL 645 #define SBRMI_WRITE_DATA2__WrByte9_MASK 0x0000FF00L 646 #define SBRMI_WRITE_DATA2__WrByte10_MASK 0x00FF0000L 647 #define SBRMI_WRITE_DATA2__WrByte11_MASK 0xFF000000L 648 //SBRMI_READ_DATA0 649 #define SBRMI_READ_DATA0__RdByte0__SHIFT 0x0 650 #define SBRMI_READ_DATA0__RdByte1__SHIFT 0x8 651 #define SBRMI_READ_DATA0__RdByte2__SHIFT 0x10 652 #define SBRMI_READ_DATA0__RdByte3__SHIFT 0x18 653 #define SBRMI_READ_DATA0__RdByte0_MASK 0x000000FFL 654 #define SBRMI_READ_DATA0__RdByte1_MASK 0x0000FF00L 655 #define SBRMI_READ_DATA0__RdByte2_MASK 0x00FF0000L 656 #define SBRMI_READ_DATA0__RdByte3_MASK 0xFF000000L 657 //SBRMI_READ_DATA1 658 #define SBRMI_READ_DATA1__RdByte4__SHIFT 0x0 659 #define SBRMI_READ_DATA1__RdByte5__SHIFT 0x8 660 #define SBRMI_READ_DATA1__RdByte6__SHIFT 0x10 661 #define SBRMI_READ_DATA1__RdByte7__SHIFT 0x18 662 #define SBRMI_READ_DATA1__RdByte4_MASK 0x000000FFL 663 #define SBRMI_READ_DATA1__RdByte5_MASK 0x0000FF00L 664 #define SBRMI_READ_DATA1__RdByte6_MASK 0x00FF0000L 665 #define SBRMI_READ_DATA1__RdByte7_MASK 0xFF000000L 666 //SBRMI_CORE_EN_NUMBER 667 #define SBRMI_CORE_EN_NUMBER__EnabledCoreNum__SHIFT 0x0 668 #define SBRMI_CORE_EN_NUMBER__EnabledCoreNum_MASK 0x0000007FL 669 //SBRMI_CORE_EN_STATUS0 670 #define SBRMI_CORE_EN_STATUS0__CoreEnStat0__SHIFT 0x0 671 #define SBRMI_CORE_EN_STATUS0__CoreEnStat0_MASK 0xFFFFFFFFL 672 //SBRMI_CORE_EN_STATUS1 673 #define SBRMI_CORE_EN_STATUS1__CoreEnStat1__SHIFT 0x0 674 #define SBRMI_CORE_EN_STATUS1__CoreEnStat1_MASK 0xFFFFFFFFL 675 //SBRMI_APIC_STATUS0 676 #define SBRMI_APIC_STATUS0__APICStat0__SHIFT 0x0 677 #define SBRMI_APIC_STATUS0__APICStat0_MASK 0xFFFFFFFFL 678 //SBRMI_APIC_STATUS1 679 #define SBRMI_APIC_STATUS1__APICStat1__SHIFT 0x0 680 #define SBRMI_APIC_STATUS1__APICStat1_MASK 0xFFFFFFFFL 681 //SBRMI_MCE_STATUS0 682 #define SBRMI_MCE_STATUS0__MceStat0__SHIFT 0x0 683 #define SBRMI_MCE_STATUS0__MceStat0_MASK 0xFFFFFFFFL 684 //SBRMI_MCE_STATUS1 685 #define SBRMI_MCE_STATUS1__MceStat1__SHIFT 0x0 686 #define SBRMI_MCE_STATUS1__MceStat1_MASK 0xFFFFFFFFL 687 //SMBUS_CNTL0 688 #define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE__SHIFT 0x0 689 #define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR__SHIFT 0x1 690 #define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE__SHIFT 0x8 691 #define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES__SHIFT 0x10 692 #define SMBUS_CNTL0__THM_READY__SHIFT 0x14 693 #define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE_MASK 0x00000001L 694 #define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_MASK 0x000000FEL 695 #define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE_MASK 0x0000FF00L 696 #define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES_MASK 0x00070000L 697 #define SMBUS_CNTL0__THM_READY_MASK 0x00100000L 698 //SMBUS_CNTL1 699 #define SMBUS_CNTL1__SMB_TIMEOUT_EN__SHIFT 0x0 700 #define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN__SHIFT 0x1 701 #define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN__SHIFT 0x9 702 #define SMBUS_CNTL1__SMB_TIMEOUT_EN_MASK 0x00000001L 703 #define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN_MASK 0x000001FEL 704 #define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN_MASK 0x0001FE00L 705 //SMBUS_BLKWR_CMD_CTRL0 706 #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0__SHIFT 0x0 707 #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1__SHIFT 0x8 708 #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2__SHIFT 0x10 709 #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3__SHIFT 0x18 710 #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0_MASK 0x000000FFL 711 #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1_MASK 0x0000FF00L 712 #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2_MASK 0x00FF0000L 713 #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3_MASK 0xFF000000L 714 //SMBUS_BLKWR_CMD_CTRL1 715 #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4__SHIFT 0x0 716 #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5__SHIFT 0x8 717 #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6__SHIFT 0x10 718 #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7__SHIFT 0x18 719 #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4_MASK 0x000000FFL 720 #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5_MASK 0x0000FF00L 721 #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6_MASK 0x00FF0000L 722 #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7_MASK 0xFF000000L 723 //SMBUS_BLKRD_CMD_CTRL0 724 #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0__SHIFT 0x0 725 #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1__SHIFT 0x8 726 #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2__SHIFT 0x10 727 #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3__SHIFT 0x18 728 #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0_MASK 0x000000FFL 729 #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1_MASK 0x0000FF00L 730 #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2_MASK 0x00FF0000L 731 #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3_MASK 0xFF000000L 732 //SMBUS_BLKRD_CMD_CTRL1 733 #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4__SHIFT 0x0 734 #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5__SHIFT 0x8 735 #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6__SHIFT 0x10 736 #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7__SHIFT 0x18 737 #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4_MASK 0x000000FFL 738 #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5_MASK 0x0000FF00L 739 #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6_MASK 0x00FF0000L 740 #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7_MASK 0xFF000000L 741 //SMBUS_TIMING_CNTL0 742 #define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN__SHIFT 0x0 743 #define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN__SHIFT 0x16 744 #define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN_MASK 0x003FFFFFL 745 #define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN_MASK 0x3FC00000L 746 //SMBUS_TIMING_CNTL1 747 #define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN__SHIFT 0x0 748 #define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN__SHIFT 0x5 749 #define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN__SHIFT 0xb 750 #define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN__SHIFT 0x14 751 #define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN_MASK 0x0000001FL 752 #define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN_MASK 0x000007E0L 753 #define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN_MASK 0x000FF800L 754 #define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN_MASK 0x3FF00000L 755 //SMBUS_TIMING_CNTL2 756 #define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN__SHIFT 0x0 757 #define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN__SHIFT 0xd 758 #define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN_MASK 0x00001FFFL 759 #define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN_MASK 0x07FFE000L 760 //SMBUS_TRIGGER_CNTL 761 #define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER__SHIFT 0x0 762 #define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER__SHIFT 0x8 763 #define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER_MASK 0x00000001L 764 #define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER_MASK 0x00000100L 765 //SMBUS_UDID_CNTL0 766 #define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED__SHIFT 0x0 767 #define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN__SHIFT 0x1f 768 #define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED_MASK 0x7FFFFFFFL 769 #define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN_MASK 0x80000000L 770 //SMBUS_UDID_CNTL1 771 #define SMBUS_UDID_CNTL1__SMB_UDID_31_0__SHIFT 0x0 772 #define SMBUS_UDID_CNTL1__SMB_UDID_31_0_MASK 0xFFFFFFFFL 773 //SMBUS_UDID_CNTL2 774 #define SMBUS_UDID_CNTL2__PEC_SUPPORTED__SHIFT 0x0 775 #define SMBUS_UDID_CNTL2__UDID_VERSION__SHIFT 0x1 776 #define SMBUS_UDID_CNTL2__SMBUS_VERSION__SHIFT 0x4 777 #define SMBUS_UDID_CNTL2__OEM__SHIFT 0x8 778 #define SMBUS_UDID_CNTL2__ASF__SHIFT 0x9 779 #define SMBUS_UDID_CNTL2__IPMI__SHIFT 0xa 780 #define SMBUS_UDID_CNTL2__PEC_SUPPORTED_MASK 0x00000001L 781 #define SMBUS_UDID_CNTL2__UDID_VERSION_MASK 0x0000000EL 782 #define SMBUS_UDID_CNTL2__SMBUS_VERSION_MASK 0x000000F0L 783 #define SMBUS_UDID_CNTL2__OEM_MASK 0x00000100L 784 #define SMBUS_UDID_CNTL2__ASF_MASK 0x00000200L 785 #define SMBUS_UDID_CNTL2__IPMI_MASK 0x00000400L 786 //SMUSBI_SMBUS 787 #define SMUSBI_SMBUS__Spare0__SHIFT 0x0 788 #define SMUSBI_SMBUS__Spare1__SHIFT 0x1 789 #define SMUSBI_SMBUS__ResBiasEn__SHIFT 0x2 790 #define SMUSBI_SMBUS__CompSel__SHIFT 0x3 791 #define SMUSBI_SMBUS__NG__SHIFT 0x4 792 #define SMUSBI_SMBUS__I2cRxSel__SHIFT 0x8 793 #define SMUSBI_SMBUS__PdEn0__SHIFT 0xa 794 #define SMUSBI_SMBUS__PdEn1__SHIFT 0xb 795 #define SMUSBI_SMBUS__FallSlewSel__SHIFT 0xc 796 #define SMUSBI_SMBUS__Slewn__SHIFT 0xe 797 #define SMUSBI_SMBUS__SpikeRcEn__SHIFT 0xf 798 #define SMUSBI_SMBUS__SpikeRcSel__SHIFT 0x10 799 #define SMUSBI_SMBUS__CSel0p9__SHIFT 0x11 800 #define SMUSBI_SMBUS__CSel1p1__SHIFT 0x12 801 #define SMUSBI_SMBUS__RSel0p9__SHIFT 0x13 802 #define SMUSBI_SMBUS__RSel1p1__SHIFT 0x14 803 #define SMUSBI_SMBUS__BiasCrtEn__SHIFT 0x15 804 #define SMUSBI_SMBUS__DI2C0__SHIFT 0x16 805 #define SMUSBI_SMBUS__DI2C1__SHIFT 0x17 806 #define SMUSBI_SMBUS__DI2C0_OVERRIDE__SHIFT 0x18 807 #define SMUSBI_SMBUS__DI2C1_OVERRIDE__SHIFT 0x19 808 #define SMUSBI_SMBUS__Y0__SHIFT 0x1e 809 #define SMUSBI_SMBUS__Y1__SHIFT 0x1f 810 #define SMUSBI_SMBUS__Spare0_MASK 0x00000001L 811 #define SMUSBI_SMBUS__Spare1_MASK 0x00000002L 812 #define SMUSBI_SMBUS__ResBiasEn_MASK 0x00000004L 813 #define SMUSBI_SMBUS__CompSel_MASK 0x00000008L 814 #define SMUSBI_SMBUS__NG_MASK 0x000000F0L 815 #define SMUSBI_SMBUS__I2cRxSel_MASK 0x00000300L 816 #define SMUSBI_SMBUS__PdEn0_MASK 0x00000400L 817 #define SMUSBI_SMBUS__PdEn1_MASK 0x00000800L 818 #define SMUSBI_SMBUS__FallSlewSel_MASK 0x00003000L 819 #define SMUSBI_SMBUS__Slewn_MASK 0x00004000L 820 #define SMUSBI_SMBUS__SpikeRcEn_MASK 0x00008000L 821 #define SMUSBI_SMBUS__SpikeRcSel_MASK 0x00010000L 822 #define SMUSBI_SMBUS__CSel0p9_MASK 0x00020000L 823 #define SMUSBI_SMBUS__CSel1p1_MASK 0x00040000L 824 #define SMUSBI_SMBUS__RSel0p9_MASK 0x00080000L 825 #define SMUSBI_SMBUS__RSel1p1_MASK 0x00100000L 826 #define SMUSBI_SMBUS__BiasCrtEn_MASK 0x00200000L 827 #define SMUSBI_SMBUS__DI2C0_MASK 0x00400000L 828 #define SMUSBI_SMBUS__DI2C1_MASK 0x00800000L 829 #define SMUSBI_SMBUS__DI2C0_OVERRIDE_MASK 0x01000000L 830 #define SMUSBI_SMBUS__DI2C1_OVERRIDE_MASK 0x02000000L 831 #define SMUSBI_SMBUS__Y0_MASK 0x40000000L 832 #define SMUSBI_SMBUS__Y1_MASK 0x80000000L 833 //SMUSBI_ALERT 834 #define SMUSBI_ALERT__TXIMPSEL__SHIFT 0x0 835 #define SMUSBI_ALERT__PD__SHIFT 0x1 836 #define SMUSBI_ALERT__PU__SHIFT 0x2 837 #define SMUSBI_ALERT__SCHMEN__SHIFT 0x3 838 #define SMUSBI_ALERT__S0__SHIFT 0x4 839 #define SMUSBI_ALERT__S1__SHIFT 0x5 840 #define SMUSBI_ALERT__RXEN__SHIFT 0x6 841 #define SMUSBI_ALERT__RXSEL0__SHIFT 0x7 842 #define SMUSBI_ALERT__RXSEL1__SHIFT 0x8 843 #define SMUSBI_ALERT__OE_OVERRIDE__SHIFT 0x10 844 #define SMUSBI_ALERT__OE__SHIFT 0x11 845 #define SMUSBI_ALERT__A_OVERRIDE__SHIFT 0x12 846 #define SMUSBI_ALERT__A__SHIFT 0x13 847 #define SMUSBI_ALERT__Y__SHIFT 0x1f 848 #define SMUSBI_ALERT__TXIMPSEL_MASK 0x00000001L 849 #define SMUSBI_ALERT__PD_MASK 0x00000002L 850 #define SMUSBI_ALERT__PU_MASK 0x00000004L 851 #define SMUSBI_ALERT__SCHMEN_MASK 0x00000008L 852 #define SMUSBI_ALERT__S0_MASK 0x00000010L 853 #define SMUSBI_ALERT__S1_MASK 0x00000020L 854 #define SMUSBI_ALERT__RXEN_MASK 0x00000040L 855 #define SMUSBI_ALERT__RXSEL0_MASK 0x00000080L 856 #define SMUSBI_ALERT__RXSEL1_MASK 0x00000100L 857 #define SMUSBI_ALERT__OE_OVERRIDE_MASK 0x00010000L 858 #define SMUSBI_ALERT__OE_MASK 0x00020000L 859 #define SMUSBI_ALERT__A_OVERRIDE_MASK 0x00040000L 860 #define SMUSBI_ALERT__A_MASK 0x00080000L 861 #define SMUSBI_ALERT__Y_MASK 0x80000000L 862 //THM_TMON0_REMOTE_START 863 #define THM_TMON0_REMOTE_START__DATA__SHIFT 0x0 864 #define THM_TMON0_REMOTE_START__DATA_MASK 0xFFFFFFFFL 865 //THM_TMON0_REMOTE_END 866 #define THM_TMON0_REMOTE_END__DATA__SHIFT 0x0 867 #define THM_TMON0_REMOTE_END__DATA_MASK 0xFFFFFFFFL 868 //THM_TMON1_REMOTE_START 869 #define THM_TMON1_REMOTE_START__DATA__SHIFT 0x0 870 #define THM_TMON1_REMOTE_START__DATA_MASK 0xFFFFFFFFL 871 //THM_TMON1_REMOTE_END 872 #define THM_TMON1_REMOTE_END__DATA__SHIFT 0x0 873 #define THM_TMON1_REMOTE_END__DATA_MASK 0xFFFFFFFFL 874 //THM_TMON2_REMOTE_START 875 #define THM_TMON2_REMOTE_START__DATA__SHIFT 0x0 876 #define THM_TMON2_REMOTE_START__DATA_MASK 0xFFFFFFFFL 877 //THM_TMON2_REMOTE_END 878 #define THM_TMON2_REMOTE_END__DATA__SHIFT 0x0 879 #define THM_TMON2_REMOTE_END__DATA_MASK 0xFFFFFFFFL 880 //THM_TMON3_REMOTE_START 881 #define THM_TMON3_REMOTE_START__DATA__SHIFT 0x0 882 #define THM_TMON3_REMOTE_START__DATA_MASK 0xFFFFFFFFL 883 //THM_TMON3_REMOTE_END 884 #define THM_TMON3_REMOTE_END__DATA__SHIFT 0x0 885 #define THM_TMON3_REMOTE_END__DATA_MASK 0xFFFFFFFFL 886 887 #endif 888