1 /* $NetBSD: mp_10_0_sh_mask.h,v 1.2 2021/12/18 23:45:17 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _mp_10_0_SH_MASK_HEADER 24 #define _mp_10_0_SH_MASK_HEADER 25 26 27 // addressBlock: mp_SmuMp0_SmnDec 28 //MP0_SMN_C2PMSG_32 29 #define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 30 #define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL 31 //MP0_SMN_C2PMSG_33 32 #define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 33 #define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL 34 //MP0_SMN_C2PMSG_34 35 #define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 36 #define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL 37 //MP0_SMN_C2PMSG_35 38 #define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 39 #define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL 40 //MP0_SMN_C2PMSG_36 41 #define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 42 #define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL 43 //MP0_SMN_C2PMSG_37 44 #define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 45 #define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL 46 //MP0_SMN_C2PMSG_38 47 #define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 48 #define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL 49 //MP0_SMN_C2PMSG_39 50 #define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 51 #define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL 52 //MP0_SMN_C2PMSG_40 53 #define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 54 #define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL 55 //MP0_SMN_C2PMSG_41 56 #define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 57 #define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL 58 //MP0_SMN_C2PMSG_42 59 #define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 60 #define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL 61 //MP0_SMN_C2PMSG_43 62 #define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 63 #define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL 64 //MP0_SMN_C2PMSG_44 65 #define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 66 #define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL 67 //MP0_SMN_C2PMSG_45 68 #define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 69 #define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL 70 //MP0_SMN_C2PMSG_46 71 #define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 72 #define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL 73 //MP0_SMN_C2PMSG_47 74 #define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 75 #define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL 76 //MP0_SMN_C2PMSG_48 77 #define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 78 #define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL 79 //MP0_SMN_C2PMSG_49 80 #define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 81 #define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL 82 //MP0_SMN_C2PMSG_50 83 #define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 84 #define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL 85 //MP0_SMN_C2PMSG_51 86 #define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 87 #define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL 88 //MP0_SMN_C2PMSG_52 89 #define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 90 #define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL 91 //MP0_SMN_C2PMSG_53 92 #define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 93 #define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL 94 //MP0_SMN_C2PMSG_54 95 #define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 96 #define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL 97 //MP0_SMN_C2PMSG_55 98 #define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 99 #define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL 100 //MP0_SMN_C2PMSG_56 101 #define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 102 #define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL 103 //MP0_SMN_C2PMSG_57 104 #define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 105 #define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL 106 //MP0_SMN_C2PMSG_58 107 #define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 108 #define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL 109 //MP0_SMN_C2PMSG_59 110 #define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 111 #define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL 112 //MP0_SMN_C2PMSG_60 113 #define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 114 #define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL 115 //MP0_SMN_C2PMSG_61 116 #define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 117 #define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL 118 //MP0_SMN_C2PMSG_62 119 #define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 120 #define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL 121 //MP0_SMN_C2PMSG_63 122 #define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 123 #define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL 124 //MP0_SMN_C2PMSG_64 125 #define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 126 #define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL 127 //MP0_SMN_C2PMSG_65 128 #define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 129 #define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL 130 //MP0_SMN_C2PMSG_66 131 #define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 132 #define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL 133 //MP0_SMN_C2PMSG_67 134 #define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 135 #define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL 136 //MP0_SMN_C2PMSG_68 137 #define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 138 #define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL 139 //MP0_SMN_C2PMSG_69 140 #define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 141 #define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL 142 //MP0_SMN_C2PMSG_70 143 #define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 144 #define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL 145 //MP0_SMN_C2PMSG_71 146 #define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 147 #define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL 148 //MP0_SMN_C2PMSG_72 149 #define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 150 #define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL 151 //MP0_SMN_C2PMSG_73 152 #define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 153 #define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL 154 //MP0_SMN_C2PMSG_74 155 #define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 156 #define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL 157 //MP0_SMN_C2PMSG_75 158 #define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 159 #define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL 160 //MP0_SMN_C2PMSG_76 161 #define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 162 #define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL 163 //MP0_SMN_C2PMSG_77 164 #define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 165 #define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL 166 //MP0_SMN_C2PMSG_78 167 #define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 168 #define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL 169 //MP0_SMN_C2PMSG_79 170 #define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 171 #define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL 172 //MP0_SMN_C2PMSG_80 173 #define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 174 #define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL 175 //MP0_SMN_C2PMSG_81 176 #define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 177 #define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL 178 //MP0_SMN_C2PMSG_82 179 #define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 180 #define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL 181 //MP0_SMN_C2PMSG_83 182 #define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 183 #define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL 184 //MP0_SMN_C2PMSG_84 185 #define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 186 #define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL 187 //MP0_SMN_C2PMSG_85 188 #define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 189 #define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL 190 //MP0_SMN_C2PMSG_86 191 #define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 192 #define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL 193 //MP0_SMN_C2PMSG_87 194 #define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 195 #define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL 196 //MP0_SMN_C2PMSG_88 197 #define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 198 #define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL 199 //MP0_SMN_C2PMSG_89 200 #define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 201 #define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL 202 //MP0_SMN_C2PMSG_90 203 #define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 204 #define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL 205 //MP0_SMN_C2PMSG_91 206 #define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 207 #define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL 208 //MP0_SMN_C2PMSG_92 209 #define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 210 #define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL 211 //MP0_SMN_C2PMSG_93 212 #define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 213 #define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL 214 //MP0_SMN_C2PMSG_94 215 #define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 216 #define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL 217 //MP0_SMN_C2PMSG_95 218 #define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 219 #define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL 220 //MP0_SMN_C2PMSG_96 221 #define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 222 #define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL 223 //MP0_SMN_C2PMSG_97 224 #define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 225 #define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL 226 //MP0_SMN_C2PMSG_98 227 #define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 228 #define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL 229 //MP0_SMN_C2PMSG_99 230 #define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 231 #define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL 232 //MP0_SMN_C2PMSG_100 233 #define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 234 #define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL 235 //MP0_SMN_C2PMSG_101 236 #define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 237 #define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL 238 //MP0_SMN_C2PMSG_102 239 #define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 240 #define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL 241 //MP0_SMN_C2PMSG_103 242 #define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 243 #define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL 244 //MP0_SMN_IH_CREDIT 245 #define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 246 #define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 247 #define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 248 #define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L 249 //MP0_SMN_IH_SW_INT 250 #define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x0 251 #define MP0_SMN_IH_SW_INT__ID__SHIFT 0x1 252 #define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000001L 253 #define MP0_SMN_IH_SW_INT__ID_MASK 0x000001FEL 254 //MP0_SMN_IH_SW_INT_CTRL 255 #define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0 256 #define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8 257 #define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L 258 #define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L 259 260 261 // addressBlock: mp_SmuMp1_SmnDec 262 //MP1_SMN_C2PMSG_32 263 #define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 264 #define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL 265 //MP1_SMN_C2PMSG_33 266 #define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 267 #define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL 268 //MP1_SMN_C2PMSG_34 269 #define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 270 #define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL 271 //MP1_SMN_C2PMSG_35 272 #define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 273 #define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL 274 //MP1_SMN_C2PMSG_36 275 #define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 276 #define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL 277 //MP1_SMN_C2PMSG_37 278 #define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 279 #define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL 280 //MP1_SMN_C2PMSG_38 281 #define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 282 #define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL 283 //MP1_SMN_C2PMSG_39 284 #define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 285 #define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL 286 //MP1_SMN_C2PMSG_40 287 #define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 288 #define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL 289 //MP1_SMN_C2PMSG_41 290 #define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 291 #define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL 292 //MP1_SMN_C2PMSG_42 293 #define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 294 #define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL 295 //MP1_SMN_C2PMSG_43 296 #define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 297 #define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL 298 //MP1_SMN_C2PMSG_44 299 #define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 300 #define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL 301 //MP1_SMN_C2PMSG_45 302 #define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 303 #define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL 304 //MP1_SMN_C2PMSG_46 305 #define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 306 #define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL 307 //MP1_SMN_C2PMSG_47 308 #define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 309 #define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL 310 //MP1_SMN_C2PMSG_48 311 #define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 312 #define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL 313 //MP1_SMN_C2PMSG_49 314 #define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 315 #define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL 316 //MP1_SMN_C2PMSG_50 317 #define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 318 #define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL 319 //MP1_SMN_C2PMSG_51 320 #define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 321 #define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL 322 //MP1_SMN_C2PMSG_52 323 #define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 324 #define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL 325 //MP1_SMN_C2PMSG_53 326 #define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 327 #define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL 328 //MP1_SMN_C2PMSG_54 329 #define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 330 #define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL 331 //MP1_SMN_C2PMSG_55 332 #define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 333 #define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL 334 //MP1_SMN_C2PMSG_56 335 #define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 336 #define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL 337 //MP1_SMN_C2PMSG_57 338 #define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 339 #define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL 340 //MP1_SMN_C2PMSG_58 341 #define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 342 #define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL 343 //MP1_SMN_C2PMSG_59 344 #define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 345 #define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL 346 //MP1_SMN_C2PMSG_60 347 #define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 348 #define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL 349 //MP1_SMN_C2PMSG_61 350 #define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 351 #define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL 352 //MP1_SMN_C2PMSG_62 353 #define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 354 #define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL 355 //MP1_SMN_C2PMSG_63 356 #define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 357 #define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL 358 //MP1_SMN_C2PMSG_64 359 #define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 360 #define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL 361 //MP1_SMN_C2PMSG_65 362 #define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 363 #define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL 364 //MP1_SMN_C2PMSG_66 365 #define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 366 #define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL 367 //MP1_SMN_C2PMSG_67 368 #define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 369 #define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL 370 //MP1_SMN_C2PMSG_68 371 #define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 372 #define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL 373 //MP1_SMN_C2PMSG_69 374 #define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 375 #define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL 376 //MP1_SMN_C2PMSG_70 377 #define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 378 #define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL 379 //MP1_SMN_C2PMSG_71 380 #define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 381 #define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL 382 //MP1_SMN_C2PMSG_72 383 #define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 384 #define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL 385 //MP1_SMN_C2PMSG_73 386 #define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 387 #define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL 388 //MP1_SMN_C2PMSG_74 389 #define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 390 #define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL 391 //MP1_SMN_C2PMSG_75 392 #define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 393 #define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL 394 //MP1_SMN_C2PMSG_76 395 #define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 396 #define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL 397 //MP1_SMN_C2PMSG_77 398 #define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 399 #define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL 400 //MP1_SMN_C2PMSG_78 401 #define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 402 #define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL 403 //MP1_SMN_C2PMSG_79 404 #define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 405 #define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL 406 //MP1_SMN_C2PMSG_80 407 #define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 408 #define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL 409 //MP1_SMN_C2PMSG_81 410 #define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 411 #define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL 412 //MP1_SMN_C2PMSG_82 413 #define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 414 #define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL 415 //MP1_SMN_C2PMSG_83 416 #define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 417 #define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL 418 //MP1_SMN_C2PMSG_84 419 #define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 420 #define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL 421 //MP1_SMN_C2PMSG_85 422 #define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 423 #define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL 424 //MP1_SMN_C2PMSG_86 425 #define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 426 #define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL 427 //MP1_SMN_C2PMSG_87 428 #define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 429 #define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL 430 //MP1_SMN_C2PMSG_88 431 #define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 432 #define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL 433 //MP1_SMN_C2PMSG_89 434 #define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 435 #define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL 436 //MP1_SMN_C2PMSG_90 437 #define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 438 #define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL 439 //MP1_SMN_C2PMSG_91 440 #define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 441 #define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL 442 //MP1_SMN_C2PMSG_92 443 #define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 444 #define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL 445 //MP1_SMN_C2PMSG_93 446 #define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 447 #define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL 448 //MP1_SMN_C2PMSG_94 449 #define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 450 #define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL 451 //MP1_SMN_C2PMSG_95 452 #define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 453 #define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL 454 //MP1_SMN_C2PMSG_96 455 #define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 456 #define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL 457 //MP1_SMN_C2PMSG_97 458 #define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 459 #define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL 460 //MP1_SMN_C2PMSG_98 461 #define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 462 #define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL 463 //MP1_SMN_C2PMSG_99 464 #define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 465 #define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL 466 //MP1_SMN_C2PMSG_100 467 #define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 468 #define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL 469 //MP1_SMN_C2PMSG_101 470 #define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 471 #define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL 472 //MP1_SMN_C2PMSG_102 473 #define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 474 #define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL 475 //MP1_SMN_C2PMSG_103 476 #define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 477 #define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL 478 //MP1_SMN_IH_CREDIT 479 #define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 480 #define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 481 #define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 482 #define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L 483 //MP1_SMN_IH_SW_INT 484 #define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x0 485 #define MP1_SMN_IH_SW_INT__ID__SHIFT 0x1 486 #define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000001L 487 #define MP1_SMN_IH_SW_INT__ID_MASK 0x000001FEL 488 //MP1_SMN_IH_SW_INT_CTRL 489 #define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0 490 #define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8 491 #define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L 492 #define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L 493 //MP1_SMN_FPS_CNT 494 #define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 495 #define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL 496 497 498 // addressBlock: mp_SmuMp0Pub_CruDec 499 //MP0_ACTIVE_FCN_ID 500 #define MP0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 501 #define MP0_ACTIVE_FCN_ID__VF__SHIFT 0x1f 502 #define MP0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 503 #define MP0_ACTIVE_FCN_ID__VF_MASK 0x80000000L 504 //MP0_IH_CREDIT 505 #define MP0_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 506 #define MP0_IH_CREDIT__CLIENT_ID__SHIFT 0x10 507 #define MP0_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 508 #define MP0_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L 509 //MP0_IH_SW_INT 510 #define MP0_IH_SW_INT__ID__SHIFT 0x0 511 #define MP0_IH_SW_INT__VALID__SHIFT 0x8 512 #define MP0_IH_SW_INT__ID_MASK 0x000000FFL 513 #define MP0_IH_SW_INT__VALID_MASK 0x00000100L 514 //MP0_IH_SW_INT_CTRL 515 #define MP0_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 516 #define MP0_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 517 #define MP0_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L 518 #define MP0_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L 519 520 521 // addressBlock: mp_SmuMp1Pub_CruDec 522 //MP1_FIRMWARE_FLAGS 523 #define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 524 #define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 525 #define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L 526 #define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL 527 //MP1_C2PMSG_0 528 #define MP1_C2PMSG_0__CONTENT__SHIFT 0x0 529 #define MP1_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL 530 //MP1_C2PMSG_1 531 #define MP1_C2PMSG_1__CONTENT__SHIFT 0x0 532 #define MP1_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL 533 //MP1_C2PMSG_2 534 #define MP1_C2PMSG_2__CONTENT__SHIFT 0x0 535 #define MP1_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL 536 //MP1_C2PMSG_3 537 #define MP1_C2PMSG_3__CONTENT__SHIFT 0x0 538 #define MP1_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL 539 //MP1_C2PMSG_4 540 #define MP1_C2PMSG_4__CONTENT__SHIFT 0x0 541 #define MP1_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL 542 //MP1_C2PMSG_5 543 #define MP1_C2PMSG_5__CONTENT__SHIFT 0x0 544 #define MP1_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL 545 //MP1_C2PMSG_6 546 #define MP1_C2PMSG_6__CONTENT__SHIFT 0x0 547 #define MP1_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL 548 //MP1_C2PMSG_7 549 #define MP1_C2PMSG_7__CONTENT__SHIFT 0x0 550 #define MP1_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL 551 //MP1_C2PMSG_8 552 #define MP1_C2PMSG_8__CONTENT__SHIFT 0x0 553 #define MP1_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL 554 //MP1_C2PMSG_9 555 #define MP1_C2PMSG_9__CONTENT__SHIFT 0x0 556 #define MP1_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL 557 //MP1_C2PMSG_10 558 #define MP1_C2PMSG_10__CONTENT__SHIFT 0x0 559 #define MP1_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL 560 //MP1_C2PMSG_11 561 #define MP1_C2PMSG_11__CONTENT__SHIFT 0x0 562 #define MP1_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL 563 //MP1_C2PMSG_12 564 #define MP1_C2PMSG_12__CONTENT__SHIFT 0x0 565 #define MP1_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL 566 //MP1_C2PMSG_13 567 #define MP1_C2PMSG_13__CONTENT__SHIFT 0x0 568 #define MP1_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL 569 //MP1_C2PMSG_14 570 #define MP1_C2PMSG_14__CONTENT__SHIFT 0x0 571 #define MP1_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL 572 //MP1_C2PMSG_15 573 #define MP1_C2PMSG_15__CONTENT__SHIFT 0x0 574 #define MP1_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL 575 //MP1_C2PMSG_16 576 #define MP1_C2PMSG_16__CONTENT__SHIFT 0x0 577 #define MP1_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL 578 //MP1_C2PMSG_17 579 #define MP1_C2PMSG_17__CONTENT__SHIFT 0x0 580 #define MP1_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL 581 //MP1_C2PMSG_18 582 #define MP1_C2PMSG_18__CONTENT__SHIFT 0x0 583 #define MP1_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL 584 //MP1_C2PMSG_19 585 #define MP1_C2PMSG_19__CONTENT__SHIFT 0x0 586 #define MP1_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL 587 //MP1_C2PMSG_20 588 #define MP1_C2PMSG_20__CONTENT__SHIFT 0x0 589 #define MP1_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL 590 //MP1_C2PMSG_21 591 #define MP1_C2PMSG_21__CONTENT__SHIFT 0x0 592 #define MP1_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL 593 //MP1_C2PMSG_22 594 #define MP1_C2PMSG_22__CONTENT__SHIFT 0x0 595 #define MP1_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL 596 //MP1_C2PMSG_23 597 #define MP1_C2PMSG_23__CONTENT__SHIFT 0x0 598 #define MP1_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL 599 //MP1_C2PMSG_24 600 #define MP1_C2PMSG_24__CONTENT__SHIFT 0x0 601 #define MP1_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL 602 //MP1_C2PMSG_25 603 #define MP1_C2PMSG_25__CONTENT__SHIFT 0x0 604 #define MP1_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL 605 //MP1_C2PMSG_26 606 #define MP1_C2PMSG_26__CONTENT__SHIFT 0x0 607 #define MP1_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL 608 //MP1_C2PMSG_27 609 #define MP1_C2PMSG_27__CONTENT__SHIFT 0x0 610 #define MP1_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL 611 //MP1_C2PMSG_28 612 #define MP1_C2PMSG_28__CONTENT__SHIFT 0x0 613 #define MP1_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL 614 //MP1_C2PMSG_29 615 #define MP1_C2PMSG_29__CONTENT__SHIFT 0x0 616 #define MP1_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL 617 //MP1_C2PMSG_30 618 #define MP1_C2PMSG_30__CONTENT__SHIFT 0x0 619 #define MP1_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL 620 //MP1_C2PMSG_31 621 #define MP1_C2PMSG_31__CONTENT__SHIFT 0x0 622 #define MP1_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL 623 //MP1_P2CMSG_0 624 #define MP1_P2CMSG_0__CONTENT__SHIFT 0x0 625 #define MP1_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL 626 //MP1_P2CMSG_1 627 #define MP1_P2CMSG_1__CONTENT__SHIFT 0x0 628 #define MP1_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL 629 //MP1_P2CMSG_2 630 #define MP1_P2CMSG_2__CONTENT__SHIFT 0x0 631 #define MP1_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL 632 //MP1_P2CMSG_3 633 #define MP1_P2CMSG_3__CONTENT__SHIFT 0x0 634 #define MP1_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL 635 //MP1_P2CMSG_INTEN 636 #define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x0 637 #define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000FL 638 //MP1_P2CMSG_INTSTS 639 #define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0 640 #define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1 641 #define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2 642 #define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3 643 #define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L 644 #define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L 645 #define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L 646 #define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L 647 //MP1_C2PMSG_32 648 #define MP1_C2PMSG_32__CONTENT__SHIFT 0x0 649 #define MP1_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL 650 //MP1_C2PMSG_33 651 #define MP1_C2PMSG_33__CONTENT__SHIFT 0x0 652 #define MP1_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL 653 //MP1_C2PMSG_34 654 #define MP1_C2PMSG_34__CONTENT__SHIFT 0x0 655 #define MP1_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL 656 //MP1_C2PMSG_35 657 #define MP1_C2PMSG_35__CONTENT__SHIFT 0x0 658 #define MP1_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL 659 //MP1_C2PMSG_36 660 #define MP1_C2PMSG_36__CONTENT__SHIFT 0x0 661 #define MP1_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL 662 //MP1_C2PMSG_37 663 #define MP1_C2PMSG_37__CONTENT__SHIFT 0x0 664 #define MP1_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL 665 //MP1_C2PMSG_38 666 #define MP1_C2PMSG_38__CONTENT__SHIFT 0x0 667 #define MP1_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL 668 //MP1_C2PMSG_39 669 #define MP1_C2PMSG_39__CONTENT__SHIFT 0x0 670 #define MP1_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL 671 //MP1_C2PMSG_40 672 #define MP1_C2PMSG_40__CONTENT__SHIFT 0x0 673 #define MP1_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL 674 //MP1_C2PMSG_41 675 #define MP1_C2PMSG_41__CONTENT__SHIFT 0x0 676 #define MP1_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL 677 //MP1_C2PMSG_42 678 #define MP1_C2PMSG_42__CONTENT__SHIFT 0x0 679 #define MP1_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL 680 //MP1_C2PMSG_43 681 #define MP1_C2PMSG_43__CONTENT__SHIFT 0x0 682 #define MP1_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL 683 //MP1_C2PMSG_44 684 #define MP1_C2PMSG_44__CONTENT__SHIFT 0x0 685 #define MP1_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL 686 //MP1_C2PMSG_45 687 #define MP1_C2PMSG_45__CONTENT__SHIFT 0x0 688 #define MP1_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL 689 //MP1_C2PMSG_46 690 #define MP1_C2PMSG_46__CONTENT__SHIFT 0x0 691 #define MP1_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL 692 //MP1_C2PMSG_47 693 #define MP1_C2PMSG_47__CONTENT__SHIFT 0x0 694 #define MP1_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL 695 //MP1_C2PMSG_48 696 #define MP1_C2PMSG_48__CONTENT__SHIFT 0x0 697 #define MP1_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL 698 //MP1_C2PMSG_49 699 #define MP1_C2PMSG_49__CONTENT__SHIFT 0x0 700 #define MP1_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL 701 //MP1_C2PMSG_50 702 #define MP1_C2PMSG_50__CONTENT__SHIFT 0x0 703 #define MP1_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL 704 //MP1_C2PMSG_51 705 #define MP1_C2PMSG_51__CONTENT__SHIFT 0x0 706 #define MP1_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL 707 //MP1_C2PMSG_52 708 #define MP1_C2PMSG_52__CONTENT__SHIFT 0x0 709 #define MP1_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL 710 //MP1_C2PMSG_53 711 #define MP1_C2PMSG_53__CONTENT__SHIFT 0x0 712 #define MP1_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL 713 //MP1_C2PMSG_54 714 #define MP1_C2PMSG_54__CONTENT__SHIFT 0x0 715 #define MP1_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL 716 //MP1_C2PMSG_55 717 #define MP1_C2PMSG_55__CONTENT__SHIFT 0x0 718 #define MP1_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL 719 //MP1_C2PMSG_56 720 #define MP1_C2PMSG_56__CONTENT__SHIFT 0x0 721 #define MP1_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL 722 //MP1_C2PMSG_57 723 #define MP1_C2PMSG_57__CONTENT__SHIFT 0x0 724 #define MP1_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL 725 //MP1_C2PMSG_58 726 #define MP1_C2PMSG_58__CONTENT__SHIFT 0x0 727 #define MP1_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL 728 //MP1_C2PMSG_59 729 #define MP1_C2PMSG_59__CONTENT__SHIFT 0x0 730 #define MP1_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL 731 //MP1_C2PMSG_60 732 #define MP1_C2PMSG_60__CONTENT__SHIFT 0x0 733 #define MP1_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL 734 //MP1_C2PMSG_61 735 #define MP1_C2PMSG_61__CONTENT__SHIFT 0x0 736 #define MP1_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL 737 //MP1_C2PMSG_62 738 #define MP1_C2PMSG_62__CONTENT__SHIFT 0x0 739 #define MP1_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL 740 //MP1_C2PMSG_63 741 #define MP1_C2PMSG_63__CONTENT__SHIFT 0x0 742 #define MP1_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL 743 //MP1_C2PMSG_64 744 #define MP1_C2PMSG_64__CONTENT__SHIFT 0x0 745 #define MP1_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL 746 //MP1_C2PMSG_65 747 #define MP1_C2PMSG_65__CONTENT__SHIFT 0x0 748 #define MP1_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL 749 //MP1_C2PMSG_66 750 #define MP1_C2PMSG_66__CONTENT__SHIFT 0x0 751 #define MP1_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL 752 //MP1_C2PMSG_67 753 #define MP1_C2PMSG_67__CONTENT__SHIFT 0x0 754 #define MP1_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL 755 //MP1_C2PMSG_68 756 #define MP1_C2PMSG_68__CONTENT__SHIFT 0x0 757 #define MP1_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL 758 //MP1_C2PMSG_69 759 #define MP1_C2PMSG_69__CONTENT__SHIFT 0x0 760 #define MP1_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL 761 //MP1_C2PMSG_70 762 #define MP1_C2PMSG_70__CONTENT__SHIFT 0x0 763 #define MP1_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL 764 //MP1_C2PMSG_71 765 #define MP1_C2PMSG_71__CONTENT__SHIFT 0x0 766 #define MP1_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL 767 //MP1_C2PMSG_72 768 #define MP1_C2PMSG_72__CONTENT__SHIFT 0x0 769 #define MP1_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL 770 //MP1_C2PMSG_73 771 #define MP1_C2PMSG_73__CONTENT__SHIFT 0x0 772 #define MP1_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL 773 //MP1_C2PMSG_74 774 #define MP1_C2PMSG_74__CONTENT__SHIFT 0x0 775 #define MP1_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL 776 //MP1_C2PMSG_75 777 #define MP1_C2PMSG_75__CONTENT__SHIFT 0x0 778 #define MP1_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL 779 //MP1_C2PMSG_76 780 #define MP1_C2PMSG_76__CONTENT__SHIFT 0x0 781 #define MP1_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL 782 //MP1_C2PMSG_77 783 #define MP1_C2PMSG_77__CONTENT__SHIFT 0x0 784 #define MP1_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL 785 //MP1_C2PMSG_78 786 #define MP1_C2PMSG_78__CONTENT__SHIFT 0x0 787 #define MP1_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL 788 //MP1_C2PMSG_79 789 #define MP1_C2PMSG_79__CONTENT__SHIFT 0x0 790 #define MP1_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL 791 //MP1_C2PMSG_80 792 #define MP1_C2PMSG_80__CONTENT__SHIFT 0x0 793 #define MP1_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL 794 //MP1_C2PMSG_81 795 #define MP1_C2PMSG_81__CONTENT__SHIFT 0x0 796 #define MP1_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL 797 //MP1_C2PMSG_82 798 #define MP1_C2PMSG_82__CONTENT__SHIFT 0x0 799 #define MP1_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL 800 //MP1_C2PMSG_83 801 #define MP1_C2PMSG_83__CONTENT__SHIFT 0x0 802 #define MP1_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL 803 //MP1_C2PMSG_84 804 #define MP1_C2PMSG_84__CONTENT__SHIFT 0x0 805 #define MP1_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL 806 //MP1_C2PMSG_85 807 #define MP1_C2PMSG_85__CONTENT__SHIFT 0x0 808 #define MP1_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL 809 //MP1_C2PMSG_86 810 #define MP1_C2PMSG_86__CONTENT__SHIFT 0x0 811 #define MP1_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL 812 //MP1_C2PMSG_87 813 #define MP1_C2PMSG_87__CONTENT__SHIFT 0x0 814 #define MP1_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL 815 //MP1_C2PMSG_88 816 #define MP1_C2PMSG_88__CONTENT__SHIFT 0x0 817 #define MP1_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL 818 //MP1_C2PMSG_89 819 #define MP1_C2PMSG_89__CONTENT__SHIFT 0x0 820 #define MP1_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL 821 //MP1_C2PMSG_90 822 #define MP1_C2PMSG_90__CONTENT__SHIFT 0x0 823 #define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL 824 //MP1_C2PMSG_91 825 #define MP1_C2PMSG_91__CONTENT__SHIFT 0x0 826 #define MP1_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL 827 //MP1_C2PMSG_92 828 #define MP1_C2PMSG_92__CONTENT__SHIFT 0x0 829 #define MP1_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL 830 //MP1_C2PMSG_93 831 #define MP1_C2PMSG_93__CONTENT__SHIFT 0x0 832 #define MP1_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL 833 //MP1_C2PMSG_94 834 #define MP1_C2PMSG_94__CONTENT__SHIFT 0x0 835 #define MP1_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL 836 //MP1_C2PMSG_95 837 #define MP1_C2PMSG_95__CONTENT__SHIFT 0x0 838 #define MP1_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL 839 //MP1_C2PMSG_96 840 #define MP1_C2PMSG_96__CONTENT__SHIFT 0x0 841 #define MP1_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL 842 //MP1_C2PMSG_97 843 #define MP1_C2PMSG_97__CONTENT__SHIFT 0x0 844 #define MP1_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL 845 //MP1_C2PMSG_98 846 #define MP1_C2PMSG_98__CONTENT__SHIFT 0x0 847 #define MP1_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL 848 //MP1_C2PMSG_99 849 #define MP1_C2PMSG_99__CONTENT__SHIFT 0x0 850 #define MP1_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL 851 //MP1_C2PMSG_100 852 #define MP1_C2PMSG_100__CONTENT__SHIFT 0x0 853 #define MP1_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL 854 //MP1_C2PMSG_101 855 #define MP1_C2PMSG_101__CONTENT__SHIFT 0x0 856 #define MP1_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL 857 //MP1_C2PMSG_102 858 #define MP1_C2PMSG_102__CONTENT__SHIFT 0x0 859 #define MP1_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL 860 //MP1_C2PMSG_103 861 #define MP1_C2PMSG_103__CONTENT__SHIFT 0x0 862 #define MP1_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL 863 //MP1_ACTIVE_FCN_ID 864 #define MP1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 865 #define MP1_ACTIVE_FCN_ID__VF__SHIFT 0x1f 866 #define MP1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 867 #define MP1_ACTIVE_FCN_ID__VF_MASK 0x80000000L 868 //MP1_IH_CREDIT 869 #define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 870 #define MP1_IH_CREDIT__CLIENT_ID__SHIFT 0x10 871 #define MP1_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 872 #define MP1_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L 873 //MP1_IH_SW_INT 874 #define MP1_IH_SW_INT__ID__SHIFT 0x0 875 #define MP1_IH_SW_INT__VALID__SHIFT 0x8 876 #define MP1_IH_SW_INT__ID_MASK 0x000000FFL 877 #define MP1_IH_SW_INT__VALID_MASK 0x00000100L 878 //MP1_IH_SW_INT_CTRL 879 #define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 880 #define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 881 #define MP1_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L 882 #define MP1_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L 883 //MP1_FPS_CNT 884 #define MP1_FPS_CNT__COUNT__SHIFT 0x0 885 #define MP1_FPS_CNT__COUNT_MASK 0xFFFFFFFFL 886 887 888 #endif 889