1 /* $Id: imx23_usbphyreg.h,v 1.1 2013/10/07 17:36:40 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2013 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ARM_IMX_IMX23_USBPHYREG_H_ 33 #define _ARM_IMX_IMX23_USBPHYREG_H_ 34 35 #include <sys/cdefs.h> 36 37 #define HW_USBPHY_BASE 0x8007C000 38 #define HW_USBPHY_SIZE 0x2000 /* 8 kB */ 39 40 /* 41 * USB PHY Power-Down Register. 42 */ 43 #define HW_USBPHY_PWD 0x000 44 #define HW_USBPHY_PWD_SET 0x004 45 #define HW_USBPHY_PWD_CLR 0x008 46 #define HW_USBPHY_PWD_TOG 0x00c 47 48 #define HW_USBPHY_PWD_RSVD2 __BITS(31, 21) 49 #define HW_USBPHY_PWD_RXPWDRX __BIT(20) 50 #define HW_USBPHY_PWD_RXPWDDIFF __BIT(19) 51 #define HW_USBPHY_PWD_RXPWD1PT1 __BIT(18) 52 #define HW_USBPHY_PWD_RXPWDENV __BIT(17) 53 #define HW_USBPHY_PWD_RSVD1 __BITS(16, 13) 54 #define HW_USBPHY_PWD_TXPWDV2I __BIT(12) 55 #define HW_USBPHY_PWD_TXPWDIBIAS __BIT(11) 56 #define HW_USBPHY_PWD_TXPWDFS __BIT(10) 57 #define HW_USBPHY_PWD_RSVD0 __BITS(9, 0) 58 59 /* 60 * USB PHY Transmitter Control Register. 61 */ 62 #define HW_USBPHY_TX 0x010 63 #define HW_USBPHY_TX_SET 0x014 64 #define HW_USBPHY_TX_CLR 0x018 65 #define HW_USBPHY_TX_TOG 0x01c 66 67 #define HW_USBPHY_TX_RSVD5 __BITS(31, 29) 68 #define HW_USBPHY_TX_USBPHY_TX_EDGECTRL __BITS(28, 26) 69 #define HW_USBPHY_TX_USBPHY_TX_SYNC_INVERT __BIT(25) 70 #define HW_USBPHY_TX_USBPHY_TX_SYNC_MUX __BIT(24) 71 #define HW_USBPHY_TX_RSVD4 __BITS(23, 22) 72 #define HW_USBPHY_TX_TXENCAL45DP __BIT(21) 73 #define HW_USBPHY_TX_RSVD3 __BIT(20) 74 #define HW_USBPHY_TX_TXCAL45DP __BITS(19, 16) 75 #define HW_USBPHY_TX_RSVD2 __BITS(15, 14) 76 #define HW_USBPHY_TX_TXENCAL45DN __BIT(13) 77 #define HW_USBPHY_TX_RSVD1 __BIT(12) 78 #define HW_USBPHY_TX_TXCAL45DN __BITS(11, 8) 79 #define HW_USBPHY_TX_RSVD0 __BITS(7, 3) 80 #define HW_USBPHY_TX_D_CAL __BITS(3, 0) 81 82 /* 83 * USB PHY Receiver Control Register. 84 */ 85 #define HW_USBPHY_RX 0x020 86 #define HW_USBPHY_RX_SET 0x024 87 #define HW_USBPHY_RX_CLR 0x028 88 #define HW_USBPHY_RX_TOG 0x02c 89 90 #define HW_USBPHY_RX_RSVD2 __BITS(31, 23) 91 #define HW_USBPHY_RX_RXDBYPASS __BIT(22) 92 #define HW_USBPHY_RX_RSVD1 __BITS(21, 7) 93 #define HW_USBPHY_RX_DISCONADJ __BITS(6, 4) 94 #define HW_USBPHY_RX_RSVD0 __BIT(3) 95 #define HW_USBPHY_RX_ENVADJ __BITS(2, 0) 96 97 /* 98 * USB PHY General Control Register. 99 */ 100 #define HW_USBPHY_CTRL 0x030 101 #define HW_USBPHY_CTRL_SET 0x034 102 #define HW_USBPHY_CTRL_CLR 0x038 103 #define HW_USBPHY_CTRL_TOG 0x03c 104 105 #define HW_USBPHY_CTRL_SFTRST __BIT(31) 106 #define HW_USBPHY_CTRL_CLKGATE __BIT(30) 107 #define HW_USBPHY_CTRL_UTMI_SUSPENDM __BIT(29) 108 #define HW_USBPHY_CTRL_HOST_FORCE_LS_SE0 __BIT(28) 109 #define HW_USBPHY_CTRL_RSVD3 _ _BITS(27, 14) 110 #define HW_USBPHY_CTRL_DATA_ON_LRADC __BIT(13) 111 #define HW_USBPHY_CTRL_DEVPLUGIN_IRQ __BIT(12) 112 #define HW_USBPHY_CTRL_ENIRQDEVPLUGIN __BIT(11) 113 #define HW_USBPHY_CTRL_RESUME_IRQ __BIT(10) 114 #define HW_USBPHY_CTRL_ENIRQRESUMEDETECT __BIT(9) 115 #define HW_USBPHY_CTRL_RSVD2 __BIT(8) 116 #define HW_USBPHY_CTRL_ENOTGIDDETECT __BIT(7) 117 #define HW_USBPHY_CTRL_RSVD1 __BIT(6) 118 #define HW_USBPHY_CTRL_DEVPLUGIN_POLARITY __BIT(5) 119 #define HW_USBPHY_CTRL_ENDEVPLUGINDETECT __BIT(4) 120 #define HW_USBPHY_CTRL_HOSTDISCONDETECT_IRQ __BIT(3) 121 #define HW_USBPHY_CTRL_ENIRQHOSTDISCON __BIT(2) 122 #define HW_USBPHY_CTRL_ENHOSTDISCONDETECT __BIT(1) 123 #define HW_USBPHY_CTRL_RSVD0 __BIT(0) 124 125 /* 126 * USB PHY Status Register. 127 */ 128 #define HW_USBPHY_STATUS 0x040 129 130 #define HW_USBPHY_STATUS_RSVD4 __BITS(31, 11) 131 #define HW_USBPHY_STATUS_RESUME_STATUS __BIT(10) 132 #define HW_USBPHY_STATUS_RSVD3 __BIT(9) 133 #define HW_USBPHY_STATUS_OTGID_STATUS __BIT(8) 134 #define HW_USBPHY_STATUS_RSVD2 __BIT(7) 135 #define HW_USBPHY_STATUS_DEVPLUGIN_STATUS __BIT(6) 136 #define HW_USBPHY_STATUS_RSVD1 __BITS(5, 4) 137 #define HW_USBPHY_STATUS_HOSTDISCONDETECT_STATUS __BIT(3) 138 #define HW_USBPHY_STATUS_RSVD0 __BITS(2, 0) 139 140 /* 141 * USB PHY Debug Register. 142 */ 143 #define HW_USBPHY_DEBUG 0x050 144 #define HW_USBPHY_DEBUG_SET 0x054 145 #define HW_USBPHY_DEBUG_CLR 0x058 146 #define HW_USBPHY_DEBUG_TOG 0x05c 147 148 #define HW_USBPHY_DEBUG_RSVD3 __BIT(31) 149 #define HW_USBPHY_DEBUG_CLKGATE __BIT(30) 150 #define HW_USBPHY_DEBUG_HOST_RESUME_DEBUG __BIT(29) 151 #define HW_USBPHY_DEBUG_SQUELCHRESETLENGTH __BITS(28, 25) 152 #define HW_USBPHY_DEBUG_ENSQUELCHRESET __BIT(24) 153 #define HW_USBPHY_DEBUG_RSVD2 __BITS(23, 21) 154 #define HW_USBPHY_DEBUG_SQUELCHRESETCOUNT __BITS(20, 16) 155 #define HW_USBPHY_DEBUG_RSVD1 __BITS(15, 13) 156 #define HW_USBPHY_DEBUG_ENTX2RXCOUNT __BIT(12) 157 #define HW_USBPHY_DEBUG_TX2RXCOUNT __BITS(11, 8) 158 #define HW_USBPHY_DEBUG_RSVD0 __BITS(7, 6) 159 #define HW_USBPHY_DEBUG_ENHSTPULLDOWN __BITS(5, 4) 160 #define HW_USBPHY_DEBUG_HSTPULLDOWN __BITS(3, 2) 161 #define HW_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD __BIT(1) 162 #define HW_USBPHY_DEBUG_OTGIDPIOLOCK __BIT(0) 163 164 /* 165 * UTMI Debug Status Register 0. 166 */ 167 #define HW_USBPHY_DEBUG0_STATUS 0x060 168 169 #define HW_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT __BITS(31, 26) 170 #define HW_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT __BITS(25, 16) 171 #define HW_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT __BITS(15, 0) 172 173 /* 174 * UTMI Debug Status Register 1. 175 */ 176 #define HW_USBPHY_DEBUG1 0x070 177 #define HW_USBPHY_DEBUG1_SET 0x074 178 #define HW_USBPHY_DEBUG1_CLR 0x078 179 #define HW_USBPHY_DEBUG1_TOG 0x07c 180 181 #define HW_USBPHY_DEBUG1_RSVD1 __BITS(31, 15) 182 #define HW_USBPHY_DEBUG1_ENTAILADJVD __BITS(14, 13) 183 #define HW_USBPHY_DEBUG1_ENTX2TX __BIT(12) 184 #define HW_USBPHY_DEBUG1_RSVD0 __BITS(11, 4) 185 #define HW_USBPHY_DEBUG1_DBG_ADDRESS __BITS(3, 0) 186 187 /* 188 * UTMI RTL Version. 189 */ 190 #define HW_USBPHY_VERSION 0x080 191 192 #define HW_USBPHY_VERSION_MAJOR __BITS(31, 24) 193 #define HW_USBPHY_VERSION_MINOR __BITS(23, 16) 194 #define HW_USBPHY_VERSION_STEP __BITS(15, 0) 195 196 /* 197 * USB PHY IP Block Register. 198 */ 199 #define HW_USBPHY_IP 0x090 200 #define HW_USBPHY_IP_SET 0x094 201 #define HW_USBPHY_IP_CLR 0x098 202 #define HW_USBPHY_IP_TOG 0x09c 203 204 #define HW_USBPHY_IP_RSVD1 __BITS(31, 25) 205 #define HW_USBPHY_IP_DIV_SEL __BITS(24, 23) 206 #define HW_USBPHY_IP_LFR_SEL __BITS(22, 21) 207 #define HW_USBPHY_IP_CP_SEL __BITS(20, 19) 208 #define HW_USBPHY_IP_TSTI_TX_DP __BIT(18) 209 #define HW_USBPHY_IP_TSTI_TX_DM __BIT(17) 210 #define HW_USBPHY_IP_ANALOG_TESTMODE __BIT(16) 211 #define HW_USBPHY_IP_RSVD0 __BITS(15, 3) 212 #define HW_USBPHY_IP_EN_USB_CLKS __BIT(2) 213 #define HW_USBPHY_IP_PLL_LOCKED __BIT(1) 214 #define HW_USBPHY_IP_PLL_POWER __BIT(0) 215 216 #endif /* !_ARM_IMX_IMX23_USBPHYREG_H_ */ 217