1 /* $Id: imx23_uartdbgreg.h,v 1.1 2012/11/20 19:06:14 jkunz Exp $ */ 2 3 /* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ARM_IMX_IMX23_UARTDBGREG_H_ 33 #define _ARM_IMX_IMX23_UARTDBGREG_H_ 34 35 #ifdef _LOCORE 36 #include <machine/asm.h> 37 #else 38 #include <sys/cdefs.h> 39 #endif /* !_LOCORE */ 40 41 #define HW_UARTDBG_BASE 0x80070000 42 #define HW_UARTDBG_SIZE 0x00002000 /* 8kB */ 43 44 /* 45 * UART Data Register. 46 */ 47 #define HW_UARTDBGDR 0x000 48 49 #define HW_UARTDBGDR_UNAVAILABLE __BITS(31, 16) 50 #define HW_UARTDBGDR_RESERVED __BITS(15, 12) 51 #define HW_UARTDBGDR_OE __BIT(11) 52 #define HW_UARTDBGDR_BE __BIT(10) 53 #define HW_UARTDBGDR_PE __BIT(9) 54 #define HW_UARTDBGDR_FE __BIT(8) 55 #define HW_UARTDBGDR_DATA __BITS(7,0) 56 57 /* 58 * UART Receive Status Register. 59 */ 60 #define HW_UARTDBGRSR_ECR 0x004 61 62 #define HW_UARTDBGRSR_ECR_UNAVAILABLE __BITS(31, 8) 63 #define HW_UARTDBGRSR_ECR_EC __BITS(7, 4) 64 #define HW_UARTDBGRSR_ECR_OE __BIT(3) 65 #define HW_UARTDBGRSR_ECR_BE __BIT(2) 66 #define HW_UARTDBGRSR_ECR_PE __BIT(1) 67 #define HW_UARTDBGRSR_ECR_FE __BIT(0) 68 69 /* 70 * UART Flag Register. 71 */ 72 #define HW_UARTDBGFR 0x018 73 74 #define HW_UARTDBGFR_RUNAVAILABLE __BITS(31, 16) 75 #define HW_UARTDBGFR_RESERVED __BITS(15, 9) 76 #define HW_UARTDBGFR_RI __BIT(8) 77 #define HW_UARTDBGFR_TXFE __BIT(7) 78 #define HW_UARTDBGFR_RXFF __BIT(6) 79 #define HW_UARTDBGFR_TXFF __BIT(5) 80 #define HW_UARTDBGFR_RXFE __BIT(4) 81 #define HW_UARTDBGFR_BUSY __BIT(3) 82 #define HW_UARTDBGFR_DCD __BIT(2) 83 #define HW_UARTDBGFR_DSR __BIT(1) 84 #define HW_UARTDBGFR_CTS __BIT(0) 85 86 /* 87 * UART IrDA Low-Power Counter Register. 88 */ 89 #define HW_UARTDBGILPR 0x020 90 91 #define HW_UARTDBGILPR_UNAVAILABLE __BITS(31, 8) 92 #define HW_UARTDBGILPR_ILPDVSR __BIT(7, 0) 93 94 /* 95 * UART Integer Baud Rate Divisor Register. 96 */ 97 #define HW_UARTDBGIBRD 0x024 98 99 #define HW_UARTDBGIBRD_UNAVAILABLE __BITS(31, 16) 100 #define HW_UARTDBGIBRD_BAUD_DIVINT __BITS(15, 0) 101 102 /* 103 * UART Fractional Baud Rate Divisor Register. 104 */ 105 #define HW_UARTDBGFBRD 0x028 106 107 #define HW_UARTDBGFBRD_UNAVAILABLE __BITS(31, 8) 108 #define HW_UARTDBGFBRD_RESERVED __BITS(7, 6) 109 #define HW_UARTDBGFBRD_BAUD_DIVFRAC __BITS(5, 0) 110 111 /* 112 * UART Line Control Register. 113 */ 114 #define HW_UARTDBGLCR_H 0x02C 115 116 #define HW_UARTDBGLCR_H_UNAVAILABLE __BITS(31, 16) 117 #define HW_UARTDBGLCR_H_RESERVED __BITS(15, 8) 118 #define HW_UARTDBGLCR_H_SPS __BIT(7) 119 #define HW_UARTDBGLCR_H_WLEN __BITS(6, 5) 120 #define HW_UARTDBGLCR_H_FEN __BIT(4) 121 #define HW_UARTDBGLCR_H_STP2 __BIT(3) 122 #define HW_UARTDBGLCR_H_EPS __BIT(2) 123 #define HW_UARTDBGLCR_H_PEN __BIT(1) 124 #define HW_UARTDBGLCR_H_BRK __BIT(0) 125 126 /* 127 * UART Control Register. 128 */ 129 #define HW_UARTDBGCR 0x030 130 131 #define HW_UARTDBGCR_UNAVAILABLE __BITS(31, 16) 132 #define HW_UARTDBGCR_CTSEN __BIT(15) 133 #define HW_UARTDBGCR_RTSEN __BIT(14) 134 #define HW_UARTDBGCR_OUT2 __BIT(13) 135 #define HW_UARTDBGCR_OUT1 __BIT(12) 136 #define HW_UARTDBGCR_RTS __BIT(11) 137 #define HW_UARTDBGCR_DTR __BIT(10) 138 #define HW_UARTDBGCR_RXE __BIT(9) 139 #define HW_UARTDBGCR_TXE __BIT(8) 140 #define HW_UARTDBGCR_LBE __BIT(7) 141 #define HW_UARTDBGCR_RESERVED __BITS(6, 3) 142 #define HW_UARTDBGCR_SIRLP __BIT(2) 143 #define HW_UARTDBGCR_SIREN __BIT(1) 144 #define HW_UARTDBGCR_UARTEN __BIT(0) 145 146 /* 147 * UART Interrupt FIFO Level Select Register. 148 */ 149 #define HW_UARTDBGIFLS 0x034 150 151 #define HW_UARTDBGIFLS_UNAVAILABLE __BITS(31, 16) 152 #define HW_UARTDBGIFLS_RESERVED __BITS(15, 6) 153 #define HW_UARTDBGIFLS_RXIFLSEL __BITS(5, 3) 154 #define HW_UARTDBGIFLS_TXIFLSEL __BITS(2, 0) 155 156 /* 157 * UART Interrupt Mask Set/Clear Register. 158 */ 159 #define HW_UARTDBGIMSC 0x038 160 161 #define HW_UARTDBGIMSC_UNAVAILABLE __BITS(31, 16) 162 #define HW_UARTDBGIMSC_RESERVED __BITS(15, 11) 163 #define HW_UARTDBGIMSC_OEIM __BIT(10) 164 #define HW_UARTDBGIMSC_BEIM __BIT(9) 165 #define HW_UARTDBGIMSC_PEIM __BIT(8) 166 #define HW_UARTDBGIMSC_FEIM __BIT(7) 167 #define HW_UARTDBGIMSC_RTIM __BIT(6) 168 #define HW_UARTDBGIMSC_TXIM __BIT(5) 169 #define HW_UARTDBGIMSC_RXIM __BIT(4) 170 #define HW_UARTDBGIMSC_DSRMIM __BIT(3) 171 #define HW_UARTDBGIMSC_DCDMIM __BIT(2) 172 #define HW_UARTDBGIMSC_CTSMIM __BIT(1) 173 #define HW_UARTDBGIMSC_RIMIM __BIT(0) 174 175 /* 176 * UART Raw Interrupt Status Register. 177 */ 178 #define HW_UARTDBGRIS 0x03C 179 180 #define HW_UARTDBGRIS_UNAVAILABLE __BITS(31, 16) 181 #define HW_UARTDBGRIS_RESERVED __BITS(15, 11) 182 #define HW_UARTDBGRIS_OERIS __BIT(10) 183 #define HW_UARTDBGRIS_BERIS __BIT(9) 184 #define HW_UARTDBGRIS_PERIS __BIT(8) 185 #define HW_UARTDBGRIS_FERIS __BIT(7) 186 #define HW_UARTDBGRIS_RTRIS __BIT(6) 187 #define HW_UARTDBGRIS_TXRIS __BIT(5) 188 #define HW_UARTDBGRIS_RXRIS __BIT(4) 189 #define HW_UARTDBGRIS_DSRRMIS __BIT(3) 190 #define HW_UARTDBGRIS_DCDRMIS __BIT(2) 191 #define HW_UARTDBGRIS_CTSRMIS __BIT(1) 192 #define HW_UARTDBGRIS_RIRMIS __BIT(0) 193 194 /* 195 * UART Masked Interrupt Status Register. 196 */ 197 #define HW_UARTDBGMIS 0x040 198 199 #define HW_UARTDBGMIS_UNAVAILABLE __BITS(31, 16) 200 #define HW_UARTDBGMIS_RESERVED __BITS(15, 11) 201 #define HW_UARTDBGMIS_OEMIS __BIT(10) 202 #define HW_UARTDBGMIS_BEMIS __BIT(9) 203 #define HW_UARTDBGMIS_PEMIS __BIT(8) 204 #define HW_UARTDBGMIS_FEMIS __BIT(7) 205 #define HW_UARTDBGMIS_RTMIS __BIT(6) 206 #define HW_UARTDBGMIS_TXMIS __BIT(5) 207 #define HW_UARTDBGMIS_RXMIS __BIT(4) 208 #define HW_UARTDBGMIS_DSRMMIS __BIT(3) 209 #define HW_UARTDBGMIS_DCDMMIS __BIT(2) 210 #define HW_UARTDBGMIS_CTSMMIS __BIT(1) 211 #define HW_UARTDBGMIS_RIMMIS __BIT(0) 212 213 /* 214 * UART Interrupt Clear Register. 215 */ 216 #define HW_UARTDBGICR 0x044 217 218 #define HW_UARTDBGICR_UNAVAILABLE __BITS(31, 16) 219 #define HW_UARTDBGICR_RESERVED __BITS(15, 11) 220 #define HW_UARTDBGICR_OEIC __BIT(10) 221 #define HW_UARTDBGICR_BEIC __BIT(9) 222 #define HW_UARTDBGICR_PEIC __BIT(8) 223 #define HW_UARTDBGICR_FEIC __BIT(7) 224 #define HW_UARTDBGICR_RTIC __BIT(6) 225 #define HW_UARTDBGICR_TXIC __BIT(5) 226 #define HW_UARTDBGICR_RXIC __BIT(4) 227 #define HW_UARTDBGICR_DSRMIC __BIT(3) 228 #define HW_UARTDBGICR_DCDMIC __BIT(2) 229 #define HW_UARTDBGICR_CTSMIC __BIT(1) 230 #define HW_UARTDBGICR_RIMIC __BIT(0) 231 232 /* 233 * UART DMA Control Register. 234 */ 235 #define HW_UARTDBGDMACR 0x048 236 237 #define HW_UARTDBGDMACR_UNAVAILABLE __BITS(31, 16) 238 #define HW_UARTDBGDMACR_RESERVED __BITS(15, 3) 239 #define HW_UARTDBGDMACR_DMAONERR __BIT(2) 240 #define HW_UARTDBGDMACR_TXDMAE __BIT(1) 241 #define HW_UARTDBGDMACR_RXDMAE __BIT(0) 242 243 #endif /* !_ARM_IMX_IMX23_UARTDBGREG_H_ */ 244