1 /* cpufunc.h,v 1.40.22.4 2007/11/08 10:59:33 matt Exp */ 2 3 /* 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 */ 41 42 #ifndef _ARM_CPUFUNC_PROTO_H_ 43 #define _ARM_CPUFUNC_PROTO_H_ 44 45 #ifdef _KERNEL 46 47 #if !defined(_MODULE) && defined(_KERNEL_OPT) 48 # include "opt_multiprocessor.h" 49 #endif 50 51 #include <sys/types.h> 52 #include <arm/armreg.h> 53 #include <arm/cpuconf.h> 54 55 #if defined(CPU_ARM6) || defined(CPU_ARM7) 56 void arm67_setttb (u_int, bool); 57 void arm67_tlb_flush (void); 58 void arm67_tlb_purge (vaddr_t); 59 void arm67_cache_flush (void); 60 void arm67_context_switch (u_int); 61 #endif /* CPU_ARM6 || CPU_ARM7 */ 62 63 #ifdef CPU_ARM6 64 void arm6_setup (char *); 65 #endif /* CPU_ARM6 */ 66 67 #ifdef CPU_ARM7 68 void arm7_setup (char *); 69 #endif /* CPU_ARM7 */ 70 71 #ifdef CPU_ARM7TDMI 72 int arm7_dataabt_fixup (void *); 73 void arm7tdmi_setup (char *); 74 void arm7tdmi_setttb (u_int, bool); 75 void arm7tdmi_tlb_flushID (void); 76 void arm7tdmi_tlb_flushID_SE (vaddr_t); 77 void arm7tdmi_cache_flushID (void); 78 void arm7tdmi_context_switch (u_int); 79 #endif /* CPU_ARM7TDMI */ 80 81 #ifdef CPU_ARM8 82 void arm8_setttb (u_int, bool); 83 void arm8_tlb_flushID (void); 84 void arm8_tlb_flushID_SE (vaddr_t); 85 void arm8_cache_flushID (void); 86 void arm8_cache_flushID_E (u_int); 87 void arm8_cache_cleanID (void); 88 void arm8_cache_cleanID_E (u_int); 89 void arm8_cache_purgeID (void); 90 void arm8_cache_purgeID_E (u_int entry); 91 92 void arm8_cache_syncI (void); 93 void arm8_cache_cleanID_rng (vaddr_t, vsize_t); 94 void arm8_cache_cleanD_rng (vaddr_t, vsize_t); 95 void arm8_cache_purgeID_rng (vaddr_t, vsize_t); 96 void arm8_cache_purgeD_rng (vaddr_t, vsize_t); 97 void arm8_cache_syncI_rng (vaddr_t, vsize_t); 98 99 void arm8_context_switch (u_int); 100 101 void arm8_setup (char *); 102 103 u_int arm8_clock_config (u_int, u_int); 104 #endif 105 106 #ifdef CPU_FA526 107 void fa526_setup (char *); 108 void fa526_setttb (u_int, bool); 109 void fa526_context_switch (u_int); 110 void fa526_cpu_sleep (int); 111 void fa526_tlb_flushI_SE (vaddr_t); 112 void fa526_tlb_flushID_SE (vaddr_t); 113 void fa526_flush_prefetchbuf (void); 114 void fa526_flush_brnchtgt_E (u_int); 115 116 void fa526_icache_sync_all (void); 117 void fa526_icache_sync_range(vaddr_t, vsize_t); 118 void fa526_dcache_wbinv_all (void); 119 void fa526_dcache_wbinv_range(vaddr_t, vsize_t); 120 void fa526_dcache_inv_range (vaddr_t, vsize_t); 121 void fa526_dcache_wb_range (vaddr_t, vsize_t); 122 void fa526_idcache_wbinv_all(void); 123 void fa526_idcache_wbinv_range(vaddr_t, vsize_t); 124 #endif 125 126 #ifdef CPU_SA110 127 void sa110_setup (char *); 128 void sa110_context_switch (u_int); 129 #endif /* CPU_SA110 */ 130 131 #if defined(CPU_SA1100) || defined(CPU_SA1110) 132 void sa11x0_drain_readbuf (void); 133 134 void sa11x0_context_switch (u_int); 135 void sa11x0_cpu_sleep (int); 136 137 void sa11x0_setup (char *); 138 #endif 139 140 #if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) 141 void sa1_setttb (u_int, bool); 142 143 void sa1_tlb_flushID_SE (vaddr_t); 144 145 void sa1_cache_flushID (void); 146 void sa1_cache_flushI (void); 147 void sa1_cache_flushD (void); 148 void sa1_cache_flushD_SE (vaddr_t); 149 150 void sa1_cache_cleanID (void); 151 void sa1_cache_cleanD (void); 152 void sa1_cache_cleanD_E (u_int); 153 154 void sa1_cache_purgeID (void); 155 void sa1_cache_purgeID_E (u_int); 156 void sa1_cache_purgeD (void); 157 void sa1_cache_purgeD_E (u_int); 158 159 void sa1_cache_syncI (void); 160 void sa1_cache_cleanID_rng (vaddr_t, vsize_t); 161 void sa1_cache_cleanD_rng (vaddr_t, vsize_t); 162 void sa1_cache_purgeID_rng (vaddr_t, vsize_t); 163 void sa1_cache_purgeD_rng (vaddr_t, vsize_t); 164 void sa1_cache_syncI_rng (vaddr_t, vsize_t); 165 166 #endif 167 168 #ifdef CPU_ARM9 169 void arm9_setttb (u_int, bool); 170 171 void arm9_tlb_flushID_SE (vaddr_t); 172 173 void arm9_icache_sync_all (void); 174 void arm9_icache_sync_range (vaddr_t, vsize_t); 175 176 void arm9_dcache_wbinv_all (void); 177 void arm9_dcache_wbinv_range (vaddr_t, vsize_t); 178 void arm9_dcache_inv_range (vaddr_t, vsize_t); 179 void arm9_dcache_wb_range (vaddr_t, vsize_t); 180 181 void arm9_idcache_wbinv_all (void); 182 void arm9_idcache_wbinv_range (vaddr_t, vsize_t); 183 184 void arm9_context_switch (u_int); 185 186 void arm9_setup (char *); 187 188 extern unsigned arm9_dcache_sets_max; 189 extern unsigned arm9_dcache_sets_inc; 190 extern unsigned arm9_dcache_index_max; 191 extern unsigned arm9_dcache_index_inc; 192 #endif 193 194 #if defined(CPU_ARM9E) || defined(CPU_ARM10) || defined(CPU_SHEEVA) 195 void arm10_tlb_flushID_SE (vaddr_t); 196 void arm10_tlb_flushI_SE (vaddr_t); 197 198 void arm10_context_switch (u_int); 199 200 void arm10_setup (char *); 201 #endif 202 203 #if defined(CPU_ARM9E) || defined (CPU_ARM10) || defined(CPU_SHEEVA) 204 void armv5_ec_setttb (u_int, bool); 205 206 void armv5_ec_icache_sync_all (void); 207 void armv5_ec_icache_sync_range (vaddr_t, vsize_t); 208 209 void armv5_ec_dcache_wbinv_all (void); 210 void armv5_ec_dcache_wbinv_range (vaddr_t, vsize_t); 211 void armv5_ec_dcache_inv_range (vaddr_t, vsize_t); 212 void armv5_ec_dcache_wb_range (vaddr_t, vsize_t); 213 214 void armv5_ec_idcache_wbinv_all (void); 215 void armv5_ec_idcache_wbinv_range (vaddr_t, vsize_t); 216 #endif 217 218 #if defined (CPU_ARM10) || defined (CPU_ARM11MPCORE) 219 void armv5_setttb (u_int, bool); 220 221 void armv5_icache_sync_all (void); 222 void armv5_icache_sync_range (vaddr_t, vsize_t); 223 224 void armv5_dcache_wbinv_all (void); 225 void armv5_dcache_wbinv_range (vaddr_t, vsize_t); 226 void armv5_dcache_inv_range (vaddr_t, vsize_t); 227 void armv5_dcache_wb_range (vaddr_t, vsize_t); 228 229 void armv5_idcache_wbinv_all (void); 230 void armv5_idcache_wbinv_range (vaddr_t, vsize_t); 231 232 extern unsigned armv5_dcache_sets_max; 233 extern unsigned armv5_dcache_sets_inc; 234 extern unsigned armv5_dcache_index_max; 235 extern unsigned armv5_dcache_index_inc; 236 #endif 237 238 #if defined(CPU_ARM11MPCORE) 239 void arm11mpcore_setup (char *); 240 #endif 241 242 #if defined(CPU_ARM11) 243 #if defined(ARM_MMU_EXTENDED) 244 void arm11_setttb (u_int, tlb_asid_t); 245 void arm11_context_switch (u_int, tlb_asid_t); 246 #else 247 void arm11_setttb (u_int, bool); 248 void arm11_context_switch (u_int); 249 #endif 250 251 void arm11_cpu_sleep (int); 252 void arm11_setup (char *string); 253 void arm11_tlb_flushID (void); 254 void arm11_tlb_flushI (void); 255 void arm11_tlb_flushD (void); 256 void arm11_tlb_flushID_SE (vaddr_t); 257 void arm11_tlb_flushI_SE (vaddr_t); 258 void arm11_tlb_flushD_SE (vaddr_t); 259 260 void armv11_dcache_wbinv_all (void); 261 void armv11_idcache_wbinv_all(void); 262 263 void arm11_drain_writebuf (void); 264 void arm11_sleep (int); 265 266 void armv6_setttb (u_int, bool); 267 268 void armv6_icache_sync_all (void); 269 void armv6_icache_sync_range (vaddr_t, vsize_t); 270 271 void armv6_dcache_wbinv_all (void); 272 void armv6_dcache_wbinv_range (vaddr_t, vsize_t); 273 void armv6_dcache_inv_range (vaddr_t, vsize_t); 274 void armv6_dcache_wb_range (vaddr_t, vsize_t); 275 276 void armv6_idcache_wbinv_all (void); 277 void armv6_idcache_wbinv_range (vaddr_t, vsize_t); 278 #endif 279 280 #if defined(CPU_ARMV7) 281 #if defined(ARM_MMU_EXTENDED) 282 void armv7_setttb(u_int, tlb_asid_t); 283 void armv7_context_switch(u_int, tlb_asid_t); 284 #else 285 void armv7_setttb(u_int, bool); 286 void armv7_context_switch(u_int); 287 #endif 288 289 void armv7_icache_sync_range(vaddr_t, vsize_t); 290 void armv7_icache_sync_all(void); 291 292 void armv7_dcache_inv_range(vaddr_t, vsize_t); 293 void armv7_dcache_wb_range(vaddr_t, vsize_t); 294 void armv7_dcache_wbinv_range(vaddr_t, vsize_t); 295 void armv7_dcache_wbinv_all(void); 296 297 void armv7_idcache_wbinv_range(vaddr_t, vsize_t); 298 void armv7_idcache_wbinv_all(void); 299 300 void armv7up_tlb_flushID(void); 301 void armv7up_tlb_flushI(void); 302 void armv7up_tlb_flushD(void); 303 304 void armv7up_tlb_flushID_SE(vaddr_t); 305 void armv7up_tlb_flushI_SE(vaddr_t); 306 void armv7up_tlb_flushD_SE(vaddr_t); 307 308 #ifdef MULTIPROCESSOR 309 void armv7mp_tlb_flushID(void); 310 void armv7mp_tlb_flushI(void); 311 void armv7mp_tlb_flushD(void); 312 313 void armv7mp_tlb_flushID_SE(vaddr_t); 314 void armv7mp_tlb_flushI_SE(vaddr_t); 315 void armv7mp_tlb_flushD_SE(vaddr_t); 316 #endif 317 318 void armv7_cpu_sleep(int); 319 void armv7_drain_writebuf(void); 320 void armv7_setup(char *string); 321 #endif /* CPU_ARMV7 */ 322 323 #if defined(CPU_PJ4B) 324 void pj4b_cpu_sleep(int); 325 void pj4bv7_setup(char *string); 326 void pj4b_config(void); 327 void pj4b_io_coherency_barrier(vaddr_t, paddr_t, vsize_t); 328 void pj4b_dcache_cfu_inv_range(vaddr_t, vsize_t); 329 void pj4b_dcache_cfu_wb_range(vaddr_t, vsize_t); 330 void pj4b_dcache_cfu_wbinv_range(vaddr_t, vsize_t); 331 #endif /* CPU_PJ4B */ 332 333 #if defined(CPU_ARM1136) || defined(CPU_ARM1176) 334 void arm11x6_idcache_wbinv_all (void); 335 void arm11x6_dcache_wbinv_all (void); 336 void arm11x6_icache_sync_all (void); 337 void arm11x6_flush_prefetchbuf (void); 338 void arm11x6_icache_sync_range (vaddr_t, vsize_t); 339 void arm11x6_idcache_wbinv_range (vaddr_t, vsize_t); 340 void arm11x6_setup (char *string); 341 void arm11x6_sleep (int); /* no ref. for errata */ 342 #endif 343 #if defined(CPU_ARM1136) 344 void arm1136_sleep_rev0 (int); /* for errata 336501 */ 345 #endif 346 347 348 #if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 349 defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ 350 defined(CPU_FA526) || defined(CPU_XSCALE) || defined(CPU_SHEEVA) 351 352 void armv4_tlb_flushID (void); 353 void armv4_tlb_flushI (void); 354 void armv4_tlb_flushD (void); 355 void armv4_tlb_flushD_SE (vaddr_t); 356 357 void armv4_drain_writebuf (void); 358 #endif 359 360 #if defined(CPU_IXP12X0) 361 void ixp12x0_drain_readbuf (void); 362 void ixp12x0_context_switch (u_int); 363 void ixp12x0_setup (char *); 364 #endif 365 366 #if defined(CPU_XSCALE) 367 void xscale_cpwait (void); 368 369 void xscale_cpu_sleep (int); 370 371 u_int xscale_control (u_int, u_int); 372 373 void xscale_setttb (u_int, bool); 374 375 void xscale_tlb_flushID_SE (vaddr_t); 376 377 void xscale_cache_flushID (void); 378 void xscale_cache_flushI (void); 379 void xscale_cache_flushD (void); 380 void xscale_cache_flushD_SE (vaddr_t); 381 382 void xscale_cache_cleanID (void); 383 void xscale_cache_cleanD (void); 384 void xscale_cache_cleanD_E (u_int); 385 386 void xscale_cache_clean_minidata (void); 387 388 void xscale_cache_purgeID (void); 389 void xscale_cache_purgeID_E (u_int); 390 void xscale_cache_purgeD (void); 391 void xscale_cache_purgeD_E (u_int); 392 393 void xscale_cache_syncI (void); 394 void xscale_cache_cleanID_rng (vaddr_t, vsize_t); 395 void xscale_cache_cleanD_rng (vaddr_t, vsize_t); 396 void xscale_cache_purgeID_rng (vaddr_t, vsize_t); 397 void xscale_cache_purgeD_rng (vaddr_t, vsize_t); 398 void xscale_cache_syncI_rng (vaddr_t, vsize_t); 399 void xscale_cache_flushD_rng (vaddr_t, vsize_t); 400 401 void xscale_context_switch (u_int); 402 403 void xscale_setup (char *); 404 #endif /* CPU_XSCALE */ 405 406 #if defined(CPU_SHEEVA) 407 void sheeva_dcache_wbinv_range (vaddr_t, vsize_t); 408 void sheeva_dcache_inv_range (vaddr_t, vsize_t); 409 void sheeva_dcache_wb_range (vaddr_t, vsize_t); 410 void sheeva_idcache_wbinv_range (vaddr_t, vsize_t); 411 void sheeva_setup(char *); 412 void sheeva_cpu_sleep(int); 413 414 void sheeva_sdcache_inv_range(vaddr_t, paddr_t, vsize_t); 415 void sheeva_sdcache_wb_range(vaddr_t, paddr_t, vsize_t); 416 void sheeva_sdcache_wbinv_range(vaddr_t, paddr_t, vsize_t); 417 void sheeva_sdcache_wbinv_all(void); 418 #endif 419 420 #endif /* _KERNEL */ 421 422 #endif /* _ARM_CPUFUNC_PROTO_H_ */ 423