1 /*
2 * omap3530 SoC (e.g. beagleboard) architecture-specific stuff
3 *
4 * errata: usb port 3 cannot operate in ulpi mode, only serial or
5 * utmi tll mode
6 */
7
8 #include "u.h"
9 #include "../port/lib.h"
10 #include "mem.h"
11 #include "dat.h"
12 #include "fns.h"
13 #include "../port/error.h"
14 #include "io.h"
15 #include "arm.h"
16
17 #include "../port/netif.h"
18 #include "etherif.h"
19 #include "../port/flashif.h"
20 #include "../port/usb.h"
21 #include "../port/portusbehci.h"
22 #include "usbehci.h"
23
24 #define FREQSEL(x) ((x) << 4)
25
26 typedef struct Cm Cm;
27 typedef struct Cntrl Cntrl;
28 typedef struct Gen Gen;
29 typedef struct Gpio Gpio;
30 typedef struct L3agent L3agent;
31 typedef struct L3protreg L3protreg;
32 typedef struct L3regs L3regs;
33 typedef struct Prm Prm;
34 typedef struct Usbotg Usbotg;
35 typedef struct Usbtll Usbtll;
36
37 /* omap3 non-standard usb stuff */
38 struct Usbotg {
39 uchar faddr;
40 uchar power;
41 ushort intrtx;
42 ushort intrrx;
43 ushort intrtxe;
44 ushort intrrxe;
45 uchar intrusb;
46 uchar intrusbe;
47 ushort frame;
48 uchar index;
49 uchar testmode;
50
51 /* indexed registers follow; ignore for now */
52 uchar _pad0[0x400 - 0x10];
53
54 ulong otgrev;
55 ulong otgsyscfg;
56 ulong otgsyssts;
57 ulong otgifcsel; /* interface selection */
58 uchar _pad1[0x414 - 0x410];
59 ulong otgforcestdby;
60 };
61
62 enum {
63 /* power bits */
64 Hsen = 1<<5, /* high-speed enable */
65
66 /* testmode bits */
67 Forcehost = 1<<7, /* force host (vs peripheral) mode */
68 Forcehs = 1<<4, /* force high-speed at reset */
69
70 /* otgsyscfg bits */
71 Midle = 1<<12, /* no standby mode */
72 Sidle = 1<<3, /* no idle mode */
73 // Softreset = 1<<1,
74
75 /* otgsyssts bits, per sysstatus */
76 };
77
78 struct Usbtll {
79 ulong revision; /* ro */
80 uchar _pad0[0x10-0x4];
81 ulong sysconfig;
82 ulong sysstatus; /* ro */
83
84 ulong irqstatus;
85 ulong irqenable;
86 };
87
88 enum {
89 /* sysconfig bits */
90 Softreset = 1<<1,
91
92 /* sysstatus bits */
93 Resetdone = 1<<0,
94 /* only in uhh->sysstatus */
95 Ehci_resetdone = 1<<2,
96 Ohci_resetdone = 1<<1,
97 };
98
99 /*
100 * an array of these structs is preceded by error_log at 0x20, control,
101 * error_clear_single, error_clear_multi. first struct is at offset 0x48.
102 */
103 struct L3protreg { /* hw: an L3 protection region */
104 uvlong req_info_perm;
105 uvlong read_perm;
106 uvlong write_perm;
107 uvlong addr_match; /* ro? write this one last, then flush */
108 };
109
110 // TODO: set these permission bits (e.g., for usb)?
111 enum {
112 Permusbhost = 1<<9,
113 Permusbotg = 1<<4,
114 Permsysdma = 1<<3,
115 Permmpu = 1<<1,
116 };
117
118 struct L3agent { /* hw registers */
119 uchar _pad0[0x20];
120 uvlong ctl;
121 uvlong sts;
122 uchar _pad1[0x58 - 0x30];
123 uvlong errlog;
124 uvlong errlogaddr;
125 };
126
127 struct L3regs {
128 L3protreg *base; /* base of array */
129 int upper; /* index maximum */
130 char *name;
131 };
132 L3regs l3regs[] = {
133 (L3protreg *)(PHYSL3GPMCPM+0x48), 7, "gpmc", /* known to be first */
134 (L3protreg *)(PHYSL3PMRT+0x48), 1, "rt", /* l3 config */
135 (L3protreg *)(PHYSL3OCTRAM+0x48), 7, "ocm ram",
136 (L3protreg *)(PHYSL3OCTROM+0x48), 1, "ocm rom",
137 (L3protreg *)(PHYSL3MAD2D+0x48), 7, "mad2d", /* die-to-die */
138 (L3protreg *)(PHYSL3IVA+0x48), 3, "iva2.2", /* a/v */
139 };
140
141 /*
142 * PRM_CLKSEL (0x48306d40) low 3 bits are system clock speed, assuming
143 * units of MHz: 0 = 12, 1 = 13, 2 = 19.2, 3 = 26, 4 = 38.4, 5 = 16.8
144 */
145
146 struct Cm { /* clock management */
147 ulong fclken; /* ``functional'' clock enable */
148 ulong fclken2;
149 ulong fclken3;
150 uchar _pad0[0x10 - 0xc];
151
152 ulong iclken; /* ``interface'' clock enable */
153 ulong iclken2;
154 ulong iclken3;
155 uchar _pad1[0x20 - 0x1c];
156
157 ulong idlest; /* idle status */
158 ulong idlest2;
159 ulong idlest3;
160 uchar _pad2[0x30 - 0x2c];
161
162 ulong autoidle;
163 ulong autoidle2;
164 ulong autoidle3;
165 uchar _pad3[0x40 - 0x3c];
166
167 union {
168 ulong clksel[5];
169 struct unused {
170 ulong sleepdep;
171 ulong clkstctrl;
172 ulong clkstst;
173 };
174 uchar _pad4[0x70 - 0x40];
175 };
176 ulong clkoutctrl;
177 };
178
179 struct Prm { /* power & reset management */
180 uchar _pad[0x50];
181 ulong rstctrl;
182 };
183
184 struct Gpio {
185 ulong _pad0[4];
186 ulong sysconfig;
187 ulong sysstatus;
188
189 ulong irqsts1; /* for mpu */
190 ulong irqen1;
191 ulong wkupen;
192 ulong _pad1;
193 ulong irqsts2; /* for iva */
194 ulong irqen2;
195
196 ulong ctrl;
197
198 ulong oe;
199 ulong datain;
200 ulong dataout;
201
202 ulong lvldet0;
203 ulong lvldet1;
204 ulong risingdet;
205 ulong fallingdet;
206
207 /* rest are uninteresting */
208 ulong deben; /* debouncing enable */
209 ulong debtime;
210 ulong _pad2[2];
211
212 ulong clrirqen1;
213 ulong setirqen1;
214 ulong _pad3[2];
215
216 ulong clrirqen2;
217 ulong setirqen2;
218 ulong _pad4[2];
219
220 ulong clrwkupen;
221 ulong setwkupen;
222 ulong _pad5[2];
223
224 ulong clrdataout;
225 ulong setdataout;
226 };
227
228 enum {
229 /* clock enable & idle status bits */
230 Wkusimocp = 1 << 9, /* SIM card: uses 120MHz clock */
231 Wkwdt2 = 1 << 5, /* wdt2 clock enable bit for wakeup */
232 Wkgpio1 = 1 << 3, /* gpio1 " */
233 Wkgpt1 = 1 << 0, /* gpt1 " */
234
235 Dssl3l4 = 1 << 0, /* dss l3, l4 i clks */
236 Dsstv = 1 << 2, /* dss tv f clock */
237 Dss2 = 1 << 1, /* dss clock 2 */
238 Dss1 = 1 << 0, /* dss clock 1 */
239
240 Pergpio6 = 1 << 17,
241 Pergpio5 = 1 << 16,
242 Pergpio4 = 1 << 15,
243 Pergpio3 = 1 << 14,
244 Pergpio2 = 1 << 13,
245 Perwdt3 = 1 << 12, /* wdt3 clock enable bit for periphs */
246 Peruart3 = 1 << 11, /* console uart */
247 Pergpt9 = 1 << 10,
248 Pergpt8 = 1 << 9,
249 Pergpt7 = 1 << 8,
250 Pergpt6 = 1 << 7,
251 Pergpt5 = 1 << 6,
252 Pergpt4 = 1 << 5,
253 Pergpt3 = 1 << 4,
254 Pergpt2 = 1 << 3, /* gpt2 clock enable bit for periphs */
255
256 Perenable = Pergpio6 | Pergpio5 | Perwdt3 | Pergpt2 | Peruart3,
257
258 Usbhost2 = 1 << 1, /* 120MHz clock enable */
259 Usbhost1 = 1 << 0, /* 48MHz clock enable */
260 Usbhost = Usbhost1, /* iclock enable */
261 Usbhostidle = 1 << 1,
262 Usbhoststdby = 1 << 0,
263
264 Coreusbhsotg = 1 << 4, /* usb hs otg enable bit */
265 Core3usbtll = 1 << 2, /* usb tll enable bit */
266
267 /* core->idlest bits */
268 Coreusbhsotgidle = 1 << 5,
269 Coreusbhsotgstdby= 1 << 4,
270
271 Dplllock = 7,
272
273 /* mpu->idlest2 bits */
274 Dplllocked = 1,
275 Dpllbypassed = 0,
276
277 /* wkup->idlest bits */
278 Gpio1idle = 1 << 3,
279
280 /* dss->idlest bits */
281 Dssidle = 1 << 1,
282
283 Gpio1vidmagic = 1<<24 | 1<<8 | 1<<5, /* gpio 1 pins for video */
284 };
285 enum {
286 Rstgs = 1 << 1, /* global sw. reset */
287
288 /* fp control regs. most are read-only */
289 Fpsid = 0,
290 Fpscr, /* rw */
291 Mvfr1 = 6,
292 Mvfr0,
293 Fpexc, /* rw */
294 };
295
296 /* see ether9221.c for explanation */
297 enum {
298 Ethergpio = 176,
299 Etherchanbit = 1 << (Ethergpio % 32),
300 };
301
302 /*
303 * these shift values are for the Cortex-A8 L1 cache (A=2, L=6) and
304 * the Cortex-A8 L2 cache (A=3, L=6).
305 * A = log2(# of ways), L = log2(bytes per cache line).
306 * see armv7 arch ref p. 1403.
307 *
308 * #define L1WAYSH 30
309 * #define L1SETSH 6
310 * #define L2WAYSH 29
311 * #define L2SETSH 6
312 */
313 enum {
314 /*
315 * cache capabilities. write-back vs write-through is controlled
316 * by the Buffered bit in PTEs.
317 */
318 Cawt = 1 << 31,
319 Cawb = 1 << 30,
320 Cara = 1 << 29,
321 Cawa = 1 << 28,
322 };
323
324 struct Gen {
325 ulong padconf_off;
326 ulong devconf0;
327 uchar _pad0[0x68 - 8];
328 ulong devconf1;
329 };
330
331 struct Cntrl {
332 ulong _pad0;
333 ulong id;
334 ulong _pad1;
335 ulong skuid;
336 };
337
338
339 static char *
devidstr(ulong)340 devidstr(ulong)
341 {
342 return "ARM Cortex-A8";
343 }
344
345 void
archomaplink(void)346 archomaplink(void)
347 {
348 }
349
350 int
ispow2(uvlong ul)351 ispow2(uvlong ul)
352 {
353 /* see Hacker's Delight if this isn't obvious */
354 return (ul & (ul - 1)) == 0;
355 }
356
357 /*
358 * return exponent of smallest power of 2 ≥ n
359 */
360 int
log2(ulong n)361 log2(ulong n)
362 {
363 int i;
364
365 i = 31 - clz(n);
366 if (n == 0 || !ispow2(n))
367 i++;
368 return i;
369 }
370
371 void
archconfinit(void)372 archconfinit(void)
373 {
374 char *p;
375 ulong mhz;
376
377 assert(m != nil);
378 m->cpuhz = 500 * Mhz; /* beagle speed */
379 p = getconf("*cpumhz");
380 if (p) {
381 mhz = atoi(p) * Mhz;
382 if (mhz >= 100*Mhz && mhz <= 3000UL*Mhz)
383 m->cpuhz = mhz;
384 }
385 m->delayloop = m->cpuhz/2000; /* initial estimate */
386 }
387
388 static void
prperm(uvlong perm)389 prperm(uvlong perm)
390 {
391 if (perm == MASK(16))
392 print("all");
393 else
394 print("%#llux", perm);
395 }
396
397 static void
prl3region(L3protreg * pr,int r)398 prl3region(L3protreg *pr, int r)
399 {
400 int level, size, addrspace;
401 uvlong am, base;
402
403 if (r == 0)
404 am = 0;
405 else
406 am = pr->addr_match;
407 size = (am >> 3) & MASK(5);
408 if (r > 0 && size == 0) /* disabled? */
409 return;
410
411 print(" %d: perms req ", r);
412 prperm(pr->req_info_perm);
413 if (pr->read_perm == pr->write_perm && pr->read_perm == MASK(16))
414 print(" rw all");
415 else {
416 print(" read ");
417 prperm(pr->read_perm);
418 print(" write ");
419 prperm(pr->write_perm);
420 }
421 if (r == 0)
422 print(", all addrs level 0");
423 else {
424 size = 1 << size; /* 2^size */
425 level = (am >> 9) & 1;
426 if (r == 1)
427 level = 3;
428 else
429 level++;
430 addrspace = am & 7;
431 base = am & ~MASK(10);
432 print(", base %#llux size %dKB level %d addrspace %d",
433 base, size, level, addrspace);
434 }
435 print("\n");
436 delay(100);
437 }
438
439
440 /*
441 * dump the l3 interconnect firewall settings by protection region.
442 * mpu, sys dma and both usbs (0x21a) should be set in all read & write
443 * permission registers.
444 */
445 static void
dumpl3pr(void)446 dumpl3pr(void)
447 {
448 int r;
449 L3regs *reg;
450 L3protreg *pr;
451
452 for (reg = l3regs; reg < l3regs + nelem(l3regs); reg++) {
453 print("%#p (%s) enabled l3 regions:\n", reg->base, reg->name);
454 for (r = 0; r <= reg->upper; r++)
455 prl3region(reg->base + r, r);
456 }
457 if (0) { // TODO
458 /* touch up gpmc perms */
459 reg = l3regs; /* first entry is gpmc */
460 for (r = 0; r <= reg->upper; r++) {
461 pr = reg->base + r;
462 // TODO
463 }
464 print("%#p (%s) modified l3 regions:\n", reg->base, reg->name);
465 for (r = 0; r <= reg->upper; r++)
466 prl3region(reg->base + r, r);
467 }
468 }
469
470 static void
p16(uchar * p,ulong v)471 p16(uchar *p, ulong v)
472 {
473 *p++ = v>>8;
474 *p = v;
475 }
476
477 static void
p32(uchar * p,ulong v)478 p32(uchar *p, ulong v)
479 {
480 *p++ = v>>24;
481 *p++ = v>>16;
482 *p++ = v>>8;
483 *p = v;
484 }
485
486 int
archether(unsigned ctlrno,Ether * ether)487 archether(unsigned ctlrno, Ether *ether)
488 {
489 switch(ctlrno) {
490 case 0:
491 /* there's no built-in ether on the beagle but igepv2 has 1 */
492 ether->type = "9221";
493 ether->ctlrno = ctlrno;
494 ether->irq = 34;
495 ether->nopt = 0;
496 ether->mbps = 100;
497 return 1;
498 }
499 return -1;
500 }
501
502 /*
503 * turn on all the necessary clocks on the SoC.
504 *
505 * a ``functional'' clock drives a device; an ``interface'' clock drives
506 * its communication with the rest of the system. so the interface
507 * clock must be enabled to reach the device's registers.
508 *
509 * dplls: 1 mpu, 2 iva2, 3 core, 4 per, 5 per2.
510 */
511
512 static void
configmpu(void)513 configmpu(void)
514 {
515 ulong clk, mhz, nmhz, maxmhz;
516 Cm *mpu = (Cm *)PHYSSCMMPU;
517 Cntrl *id = (Cntrl *)PHYSCNTRL;
518
519 if ((id->skuid & MASK(4)) == 8)
520 maxmhz = 720;
521 else
522 maxmhz = 600;
523 iprint("cpu capable of %ldMHz operation", maxmhz);
524
525 clk = mpu->clksel[0];
526 mhz = (clk >> 8) & MASK(11); /* configured speed */
527 // iprint("\tfclk src %ld; dpll1 mult %ld (MHz) div %ld",
528 // (clk >> 19) & MASK(3), mhz, clk & MASK(7));
529 iprint("; at %ldMHz", mhz);
530 nmhz = m->cpuhz / Mhz; /* nominal speed */
531 if (mhz == nmhz) {
532 iprint("\n");
533 return;
534 }
535
536 mhz = nmhz;
537 if (mhz > maxmhz) {
538 mhz = maxmhz;
539 iprint("; limiting operation to %ldMHz", mhz);
540 }
541
542 /* disable dpll1 lock mode; put into low-power bypass mode */
543 mpu->fclken2 = mpu->fclken2 & ~MASK(3) | 5;
544 coherence();
545 while (mpu->idlest2 != Dpllbypassed)
546 ;
547
548 /*
549 * there's a dance to change processor speed,
550 * prescribed in spruf98d §4.7.6.9.
551 */
552
553 /* just change multiplier; leave divider alone at 12 (meaning 13?) */
554 mpu->clksel[0] = clk & ~(MASK(11) << 8) | mhz << 8;
555 coherence();
556
557 /* set output divider (M2) in clksel[1]: leave at 1 */
558
559 /*
560 * u-boot calls us with just freqsel 3 (~1MHz) & dpll1 lock mode.
561 */
562 /* set FREQSEL */
563 mpu->fclken2 = mpu->fclken2 & ~FREQSEL(MASK(4)) | FREQSEL(3);
564 coherence();
565
566 /* set ramp-up delay to `fast' */
567 mpu->fclken2 = mpu->fclken2 & ~(MASK(2) << 8) | 3 << 8;
568 coherence();
569
570 /* set auto-recalibration (off) */
571 mpu->fclken2 &= ~(1 << 3);
572 coherence();
573
574 /* disable auto-idle: ? */
575 /* unmask clock intr: later */
576
577 /* enable dpll lock mode */
578 mpu->fclken2 |= Dplllock;
579 coherence();
580 while (mpu->idlest2 != Dplllocked)
581 ;
582 delay(200); /* allow time for speed to ramp up */
583
584 if (((mpu->clksel[0] >> 8) & MASK(11)) != mhz)
585 panic("mpu clock speed change didn't stick");
586 iprint("; now at %ldMHz\n", mhz);
587 }
588
589 static void
configpll(void)590 configpll(void)
591 {
592 int i;
593 Cm *pll = (Cm *)PHYSSCMPLL;
594
595 pll->clkoutctrl |= 1 << 7; /* enable sys_clkout2 */
596 coherence();
597 delay(10);
598
599 /*
600 * u-boot calls us with just freqsel 3 (~1MHz) & lock mode
601 * for both dplls (3 & 4). ensure that.
602 */
603 if ((pll->idlest & 3) != 3) {
604 /* put dpll[34] into low-power bypass mode */
605 pll->fclken = pll->fclken & ~(MASK(3) << 16 | MASK(3)) |
606 1 << 16 | 5;
607 coherence();
608 while (pll->idlest & 3) /* wait for both to bypass or stop */
609 ;
610
611 pll->fclken = (FREQSEL(3) | Dplllock) << 16 |
612 FREQSEL(3) | Dplllock;
613 coherence();
614 while ((pll->idlest & 3) != 3) /* wait for both to lock */
615 ;
616 }
617
618 /*
619 * u-boot calls us with just freqsel 1 (default but undefined)
620 * & stop mode for dpll5. try to lock it at 120MHz.
621 */
622 if (!(pll->idlest2 & Dplllocked)) {
623 /* force dpll5 into low-power bypass mode */
624 pll->fclken2 = 3 << 8 | FREQSEL(1) | 1;
625 coherence();
626 for (i = 0; pll->idlest2 & Dplllocked && i < 20; i++)
627 delay(50);
628 if (i >= 20)
629 iprint(" [dpll5 failed to stop]");
630
631 /*
632 * CORE_CLK is 26MHz.
633 */
634 pll->clksel[4-1] = 120 << 8 | 12; /* M=120, N=12+1 */
635 /* M2 divisor: 120MHz clock is exactly the DPLL5 clock */
636 pll->clksel[5-1] = 1;
637 coherence();
638
639 pll->fclken2 = 3 << 8 | FREQSEL(1) | Dplllock; /* def. freq */
640 coherence();
641
642 for (i = 0; !(pll->idlest2 & Dplllocked) && i < 20; i++)
643 delay(50);
644 if (i >= 20)
645 iprint(" [dpll5 failed to lock]");
646 }
647 if (!(pll->idlest2 & (1<<1)))
648 iprint(" [no 120MHz clock]");
649 if (!(pll->idlest2 & (1<<3)))
650 iprint(" [no dpll5 120MHz clock output]");
651 }
652
653 static void
configper(void)654 configper(void)
655 {
656 Cm *per = (Cm *)PHYSSCMPER;
657
658 per->clksel[0] &= ~MASK(8); /* select 32kHz clock for GPTIMER2-9 */
659
660 per->iclken |= Perenable;
661 coherence();
662 per->fclken |= Perenable;
663 coherence();
664 while (per->idlest & Perenable)
665 ;
666
667 per->autoidle = 0;
668 coherence();
669 }
670
671 static void
configwkup(void)672 configwkup(void)
673 {
674 Cm *wkup = (Cm *)PHYSSCMWKUP;
675
676 /* select 32kHz clock (not system clock) for GPTIMER1 */
677 wkup->clksel[0] &= ~1;
678
679 wkup->iclken |= Wkusimocp | Wkwdt2 | Wkgpt1;
680 coherence();
681 wkup->fclken |= Wkusimocp | Wkwdt2 | Wkgpt1;
682 coherence();
683 while (wkup->idlest & (Wkusimocp | Wkwdt2 | Wkgpt1))
684 ;
685 }
686
687 static void
configusb(void)688 configusb(void)
689 {
690 int i;
691 Cm *usb = (Cm *)PHYSSCMUSB;
692
693 /*
694 * make the usb registers accessible without address faults,
695 * notably uhh, ochi & ehci. tll seems to be separate & otg is okay.
696 */
697 usb->iclken |= Usbhost;
698 coherence();
699 usb->fclken |= Usbhost1 | Usbhost2; /* includes 120MHz clock */
700 coherence();
701 for (i = 0; usb->idlest & Usbhostidle && i < 20; i++)
702 delay(50);
703 if (i >= 20)
704 iprint(" [usb inaccessible]");
705 }
706
707 static void
configcore(void)708 configcore(void)
709 {
710 Cm *core = (Cm *)PHYSSCMCORE;
711
712 /*
713 * make the usb tll registers accessible.
714 */
715 core->iclken |= Coreusbhsotg;
716 core->iclken3 |= Core3usbtll;
717 coherence();
718 core->fclken3 |= Core3usbtll;
719 coherence();
720 delay(100);
721 while (core->idlest & Coreusbhsotgidle)
722 ;
723 if (core->idlest3 & Core3usbtll)
724 iprint(" [no usb tll]");
725 }
726
727 static void
configclks(void)728 configclks(void)
729 {
730 int s;
731 Gen *gen = (Gen *)PHYSSCMPCONF;
732
733 delay(20);
734 s = splhi();
735 configmpu(); /* sets cpu clock rate, turns on dplls 1 & 2 */
736
737 /*
738 * the main goal is to get enough clocks running, in the right order,
739 * so that usb has all the necessary clock signals.
740 */
741 iprint("clocks:");
742 iprint(" usb");
743 configusb(); /* starts usb clocks & 120MHz clock */
744 iprint(", pll");
745 configpll(); /* starts dplls 3, 4 & 5 & 120MHz clock */
746 iprint(", wakeup");
747 configwkup(); /* starts timer clocks and usim clock */
748 iprint(", per");
749 configper(); /* starts timer & gpio (ether) clocks */
750 iprint(", core");
751 configcore(); /* starts usb tll */
752 iprint("\n");
753
754 gen->devconf0 |= 1 << 1 | 1 << 0; /* dmareq[01] edge sensitive */
755 /* make dmareq[2-6] edge sensitive */
756 gen->devconf1 |= 1 << 23 | 1 << 22 | 1 << 21 | 1 << 8 | 1 << 7;
757 coherence();
758 splx(s);
759 delay(20);
760 }
761
762 static void
resetwait(ulong * reg)763 resetwait(ulong *reg)
764 {
765 long bound;
766
767 for (bound = 400*Mhz; !(*reg & Resetdone) && bound > 0; bound--)
768 ;
769 if (bound <= 0)
770 iprint("archomap: Resetdone didn't come ready\n");
771 }
772
773 /*
774 * gpio irq 1 goes to the mpu intr ctlr; irq 2 goes to the iva's.
775 * this stuff is magic and without it, we won't get irq 34 interrupts
776 * from the 9221 ethernet controller.
777 */
778 static void
configgpio(void)779 configgpio(void)
780 {
781 Gpio *gpio = (Gpio *)PHYSGPIO6;
782
783 gpio->sysconfig = Softreset;
784 coherence();
785 resetwait(&gpio->sysstatus);
786
787 gpio->ctrl = 1<<1 | 0; /* enable this gpio module, gating ratio 1 */
788 gpio->oe |= Etherchanbit; /* cfg ether pin as input */
789 coherence();
790
791 gpio->irqen1 = Etherchanbit; /* channel # == pin # */
792 gpio->irqen2 = 0;
793
794 gpio->lvldet0 = Etherchanbit; /* enable irq ass'n on low det'n */
795 gpio->lvldet1 = 0; /* disable irq ass'n on high det'n */
796 gpio->risingdet = 0; /* enable irq rising edge det'n */
797 gpio->fallingdet = 0; /* disable irq falling edge det'n */
798
799 gpio->wkupen = 0;
800
801 gpio->deben = 0; /* no de-bouncing */
802 gpio->debtime = 0;
803 coherence();
804
805 gpio->irqsts1 = ~0; /* dismiss all outstanding intrs */
806 gpio->irqsts2 = ~0;
807 coherence();
808 }
809
810 void
configscreengpio(void)811 configscreengpio(void)
812 {
813 Cm *wkup = (Cm *)PHYSSCMWKUP;
814 Gpio *gpio = (Gpio *)PHYSGPIO1;
815
816 /* no clocksel needed */
817 wkup->iclken |= Wkgpio1;
818 coherence();
819 wkup->fclken |= Wkgpio1; /* turn gpio clock on */
820 coherence();
821 // wkup->autoidle |= Wkgpio1; /* set gpio clock on auto */
822 wkup->autoidle = 0;
823 coherence();
824 while (wkup->idlest & Gpio1idle)
825 ;
826
827 /*
828 * 0 bits in oe are output signals.
829 * enable output for gpio 1 (first gpio) video magic pins.
830 */
831 gpio->oe &= ~Gpio1vidmagic;
832 coherence();
833 gpio->dataout |= Gpio1vidmagic; /* set output pins to 1 */
834 coherence();
835 delay(50);
836 }
837
838 void
screenclockson(void)839 screenclockson(void)
840 {
841 Cm *dss = (Cm *)PHYSSCMDSS;
842
843 dss->iclken |= Dssl3l4;
844 coherence();
845 dss->fclken = Dsstv | Dss2 | Dss1;
846 coherence();
847 /* tv fclk is dpll4 clk; dpll4 m4 divide factor for dss1 fclk is 2 */
848 dss->clksel[0] = 1<<12 | 2;
849 coherence();
850 delay(50);
851 while (dss->idlest & Dssidle)
852 ;
853 }
854
855 void
gpioirqclr(void)856 gpioirqclr(void)
857 {
858 Gpio *gpio = (Gpio *)PHYSGPIO6;
859
860 gpio->irqsts1 = gpio->irqsts1;
861 coherence();
862 }
863
864 static char *
l1iptype(uint type)865 l1iptype(uint type)
866 {
867 static char *types[] = {
868 "reserved",
869 "asid-tagged VIVT",
870 "VIPT",
871 "PIPT",
872 };
873
874 if (type >= nelem(types) || types[type] == nil)
875 return "GOK";
876 return types[type];
877 }
878
879 void
cacheinfo(int level,Memcache * cp)880 cacheinfo(int level, Memcache *cp)
881 {
882 ulong setsways;
883
884 /* select cache level */
885 cpwrsc(CpIDcssel, CpID, CpIDid, 0, (level - 1) << 1);
886
887 setsways = cprdsc(CpIDcsize, CpID, CpIDid, 0);
888 cp->l1ip = cprdsc(0, CpID, CpIDidct, CpIDct);
889 cp->level = level;
890 cp->nways = ((setsways >> 3) & MASK(10)) + 1;
891 cp->nsets = ((setsways >> 13) & MASK(15)) + 1;
892 cp->log2linelen = (setsways & MASK(2)) + 2 + 2;
893 cp->linelen = 1 << cp->log2linelen;
894 cp->setsways = setsways;
895
896 cp->setsh = cp->log2linelen;
897 cp->waysh = 32 - log2(cp->nways);
898 }
899
900 static void
prcachecfg(void)901 prcachecfg(void)
902 {
903 int cache;
904 Memcache mc;
905
906 for (cache = 1; cache <= 2; cache++) {
907 cacheinfo(cache, &mc);
908 iprint("l%d: %d ways %d sets %d bytes/line",
909 mc.level, mc.nways, mc.nsets, mc.linelen);
910 if (mc.linelen != CACHELINESZ)
911 iprint(" *should* be %d", CACHELINESZ);
912 if (mc.setsways & Cawt)
913 iprint("; can WT");
914 if (mc.setsways & Cawb)
915 iprint("; can WB");
916 #ifdef COMPULSIVE /* both caches can do this */
917 if (mc.setsways & Cara)
918 iprint("; can read-allocate");
919 #endif
920 if (mc.setsways & Cawa)
921 iprint("; can write-allocate");
922 if (cache == 1)
923 iprint("; l1 I policy %s",
924 l1iptype((mc.l1ip >> 14) & MASK(2)));
925 iprint("\n");
926 }
927 }
928
929 static char *
subarch(int impl,uint sa)930 subarch(int impl, uint sa)
931 {
932 static char *armarchs[] = {
933 "VFPv1 (pre-armv7)",
934 "VFPv2 (pre-armv7)",
935 "VFPv3+ with common VFP subarch v2",
936 "VFPv3+ with null subarch",
937 "VFPv3+ with common VFP subarch v3",
938 };
939
940 if (impl != 'A' || sa >= nelem(armarchs))
941 return "GOK";
942 else
943 return armarchs[sa];
944 }
945
946 /*
947 * padconf bits in a short, 2 per long register
948 * 15 wakeupevent
949 * 14 wakeupenable
950 * 13 offpulltypeselect
951 * 12 offpulludenable
952 * 11 offoutvalue
953 * 10 offoutenable
954 * 9 offenable
955 * 8 inputenable
956 * 4 pulltypeselect
957 * 3 pulludenable
958 * 2-0 muxmode
959 *
960 * see table 7-5 in §7.4.4.3 of spruf98d
961 */
962
963 enum {
964 /* pad config register bits */
965 Inena = 1 << 8, /* input enable */
966 Indis = 0 << 8, /* input disable */
967 Ptup = 1 << 4, /* pull type up */
968 Ptdown = 0 << 4, /* pull type down */
969 Ptena = 1 << 3, /* pull type selection is active */
970 Ptdis = 0 << 3, /* pull type selection is inactive */
971 Muxmode = MASK(3),
972
973 /* pad config registers relevant to flash */
974 GpmcA1 = 0x4800207A,
975 GpmcA2 = 0x4800207C,
976 GpmcA3 = 0x4800207E,
977 GpmcA4 = 0x48002080,
978 GpmcA5 = 0x48002082,
979 GpmcA6 = 0x48002084,
980 GpmcA7 = 0x48002086,
981 GpmcA8 = 0x48002088,
982 GpmcA9 = 0x4800208A,
983 GpmcA10 = 0x4800208C,
984 GpmcD0 = 0x4800208E,
985 GpmcD1 = 0x48002090,
986 GpmcD2 = 0x48002092,
987 GpmcD3 = 0x48002094,
988 GpmcD4 = 0x48002096,
989 GpmcD5 = 0x48002098,
990 GpmcD6 = 0x4800209A,
991 GpmcD7 = 0x4800209C,
992 GpmcD8 = 0x4800209E,
993 GpmcD9 = 0x480020A0,
994 GpmcD10 = 0x480020A2,
995 GpmcD11 = 0x480020A4,
996 GpmcD12 = 0x480020A6,
997 GpmcD13 = 0x480020A8,
998 GpmcD14 = 0x480020AA,
999 GpmcD15 = 0x480020AC,
1000 GpmcNCS0 = 0x480020AE,
1001 GpmcNCS1 = 0x480020B0,
1002 GpmcNCS2 = 0x480020B2,
1003 GpmcNCS3 = 0x480020B4,
1004 GpmcNCS4 = 0x480020B6,
1005 GpmcNCS5 = 0x480020B8,
1006 GpmcNCS6 = 0x480020BA,
1007 GpmcNCS7 = 0x480020BC,
1008 GpmcCLK = 0x480020BE,
1009 GpmcNADV_ALE = 0x480020C0,
1010 GpmcNOE = 0x480020C2,
1011 GpmcNWE = 0x480020C4,
1012 GpmcNBE0_CLE = 0x480020C6,
1013 GpmcNBE1 = 0x480020C8,
1014 GpmcNWP = 0x480020CA,
1015 GpmcWAIT0 = 0x480020CC,
1016 GpmcWAIT1 = 0x480020CE,
1017 GpmcWAIT2 = 0x480020D0,
1018 GpmcWAIT3 = 0x480020D2,
1019 };
1020
1021 /* set SCM pad config mux mode */
1022 void
setmuxmode(ulong addr,int shorts,int mode)1023 setmuxmode(ulong addr, int shorts, int mode)
1024 {
1025 int omode;
1026 ushort *ptr;
1027
1028 mode &= Muxmode;
1029 for (ptr = (ushort *)addr; shorts-- > 0; ptr++) {
1030 omode = *ptr & Muxmode;
1031 if (omode != mode)
1032 *ptr = *ptr & ~Muxmode | mode;
1033 }
1034 coherence();
1035 }
1036
1037 static void
setpadmodes(void)1038 setpadmodes(void)
1039 {
1040 int off;
1041
1042 /* set scm pad modes for usb; hasn't made any difference yet */
1043 setmuxmode(0x48002166, 7, 5); /* hsusb3_tll* in mode 5; is mode 4 */
1044 setmuxmode(0x48002180, 1, 5); /* hsusb3_tll_clk; is mode 4 */
1045 setmuxmode(0x48002184, 4, 5); /* hsusb3_tll_data?; is mode 1 */
1046 setmuxmode(0x480021a2, 12, 0); /* hsusb0 (console) in mode 0 */
1047 setmuxmode(0x480021d4, 6, 2); /* hsusb2_tll* (ehci port 2) in mode 2 */
1048 /* mode 3 is hsusb2_data* */
1049 setmuxmode(0x480025d8, 18, 6); /* hsusb[12]_tll*; mode 3 is */
1050 /* hsusb1_data*, hsusb2* */
1051
1052 setmuxmode(0x480020e4, 2, 5); /* uart3_rx_* in mode 5 */
1053 setmuxmode(0x4800219a, 4, 0); /* uart3_* in mode 0 */
1054 /* uart3_* in mode 2; TODO: conflicts with hsusb0 */
1055 setmuxmode(0x480021aa, 4, 2);
1056 setmuxmode(0x48002240, 2, 3); /* uart3_* in mode 3 */
1057
1058 /*
1059 * igep/gumstix only: mode 4 of 21d2 is gpio_176 (smsc9221 ether irq).
1060 * see ether9221.c for more.
1061 */
1062 *(ushort *)0x480021d2 = Inena | Ptup | Ptena | 4;
1063
1064 /* magic from u-boot for flash */
1065 *(ushort *)GpmcA1 = Indis | Ptup | Ptena | 0;
1066 *(ushort *)GpmcA2 = Indis | Ptup | Ptena | 0;
1067 *(ushort *)GpmcA3 = Indis | Ptup | Ptena | 0;
1068 *(ushort *)GpmcA4 = Indis | Ptup | Ptena | 0;
1069 *(ushort *)GpmcA5 = Indis | Ptup | Ptena | 0;
1070 *(ushort *)GpmcA6 = Indis | Ptup | Ptena | 0;
1071 *(ushort *)GpmcA7 = Indis | Ptup | Ptena | 0;
1072 *(ushort *)GpmcA8 = Indis | Ptup | Ptena | 0;
1073 *(ushort *)GpmcA9 = Indis | Ptup | Ptena | 0;
1074 *(ushort *)GpmcA10 = Indis | Ptup | Ptena | 0;
1075
1076 *(ushort *)GpmcD0 = Inena | Ptup | Ptena | 0;
1077 *(ushort *)GpmcD1 = Inena | Ptup | Ptena | 0;
1078 *(ushort *)GpmcD2 = Inena | Ptup | Ptena | 0;
1079 *(ushort *)GpmcD3 = Inena | Ptup | Ptena | 0;
1080 *(ushort *)GpmcD4 = Inena | Ptup | Ptena | 0;
1081 *(ushort *)GpmcD5 = Inena | Ptup | Ptena | 0;
1082 *(ushort *)GpmcD6 = Inena | Ptup | Ptena | 0;
1083 *(ushort *)GpmcD7 = Inena | Ptup | Ptena | 0;
1084 *(ushort *)GpmcD8 = Inena | Ptup | Ptena | 0;
1085 *(ushort *)GpmcD9 = Inena | Ptup | Ptena | 0;
1086 *(ushort *)GpmcD10 = Inena | Ptup | Ptena | 0;
1087 *(ushort *)GpmcD11 = Inena | Ptup | Ptena | 0;
1088 *(ushort *)GpmcD12 = Inena | Ptup | Ptena | 0;
1089 *(ushort *)GpmcD13 = Inena | Ptup | Ptena | 0;
1090 *(ushort *)GpmcD14 = Inena | Ptup | Ptena | 0;
1091 *(ushort *)GpmcD15 = Inena | Ptup | Ptena | 0;
1092
1093 *(ushort *)GpmcNCS0 = Indis | Ptup | Ptena | 0;
1094 *(ushort *)GpmcNCS1 = Indis | Ptup | Ptena | 0;
1095 *(ushort *)GpmcNCS2 = Indis | Ptup | Ptena | 0;
1096 *(ushort *)GpmcNCS3 = Indis | Ptup | Ptena | 0;
1097 *(ushort *)GpmcNCS4 = Indis | Ptup | Ptena | 0;
1098 *(ushort *)GpmcNCS5 = Indis | Ptup | Ptena | 0;
1099 *(ushort *)GpmcNCS6 = Indis | Ptup | Ptena | 0;
1100
1101 *(ushort *)GpmcNOE = Indis | Ptdown | Ptdis | 0;
1102 *(ushort *)GpmcNWE = Indis | Ptdown | Ptdis | 0;
1103
1104 *(ushort *)GpmcWAIT2 = Inena | Ptup | Ptena | 4; /* GPIO_64 -ETH_NRESET */
1105 *(ushort *)GpmcNCS7 = Inena | Ptup | Ptena | 1; /* SYS_nDMA_REQ3 */
1106
1107 *(ushort *)GpmcCLK = Indis | Ptdown | Ptdis | 0;
1108
1109 *(ushort *)GpmcNBE1 = Inena | Ptdown | Ptdis | 0;
1110
1111 *(ushort *)GpmcNADV_ALE = Indis | Ptdown | Ptdis | 0;
1112 *(ushort *)GpmcNBE0_CLE = Indis | Ptdown | Ptdis | 0;
1113
1114 *(ushort *)GpmcNWP = Inena | Ptdown | Ptdis | 0;
1115
1116 *(ushort *)GpmcWAIT0 = Inena | Ptup | Ptena | 0;
1117 *(ushort *)GpmcWAIT1 = Inena | Ptup | Ptena | 0;
1118 *(ushort *)GpmcWAIT3 = Inena | Ptup | Ptena | 0;
1119
1120 /*
1121 * magic from u-boot: set 0xe00 bits in gpmc_(nwe|noe|nadv_ale)
1122 * to enable `off' mode for each.
1123 */
1124 for (off = 0xc0; off <= 0xc4; off += sizeof(short))
1125 *((ushort *)(PHYSSCM + off)) |= 0xe00;
1126 coherence();
1127 }
1128
1129 static char *
implement(uchar impl)1130 implement(uchar impl)
1131 {
1132 if (impl == 'A')
1133 return "arm";
1134 else
1135 return "unknown";
1136 }
1137
1138 static void
fpon(void)1139 fpon(void)
1140 {
1141 int gotfp, impl;
1142 ulong acc, scr;
1143
1144 gotfp = 1 << CpFP | 1 << CpDFP;
1145 cpwrsc(0, CpCONTROL, 0, CpCPaccess, MASK(28));
1146 acc = cprdsc(0, CpCONTROL, 0, CpCPaccess);
1147 if ((acc & (MASK(2) << (2*CpFP))) == 0) {
1148 gotfp &= ~(1 << CpFP);
1149 print("fpon: no single FP coprocessor\n");
1150 }
1151 if ((acc & (MASK(2) << (2*CpDFP))) == 0) {
1152 gotfp &= ~(1 << CpDFP);
1153 print("fpon: no double FP coprocessor\n");
1154 }
1155 if (!gotfp) {
1156 print("fpon: no FP coprocessors\n");
1157 return;
1158 }
1159
1160 /* enable fp. must be first operation on the FPUs. */
1161 fpwr(Fpexc, fprd(Fpexc) | 1 << 30);
1162
1163 scr = fprd(Fpsid);
1164 impl = scr >> 24;
1165 print("fp: %s arch %s", implement(impl),
1166 subarch(impl, (scr >> 16) & MASK(7)));
1167
1168 scr = fprd(Fpscr);
1169 // TODO configure Fpscr further
1170 scr |= 1 << 9; /* div-by-0 exception */
1171 scr &= ~(MASK(2) << 20 | MASK(3) << 16); /* all ops are scalar */
1172 fpwr(Fpscr, scr);
1173 print("\n");
1174 /* we should now be able to execute VFP-style FP instr'ns natively */
1175 }
1176
1177 static void
resetusb(void)1178 resetusb(void)
1179 {
1180 int bound;
1181 Uhh *uhh;
1182 Usbotg *otg;
1183 Usbtll *tll;
1184
1185 iprint("resetting usb: otg...");
1186 otg = (Usbotg *)PHYSUSBOTG;
1187 otg->otgsyscfg = Softreset; /* see omap35x errata 3.1.1.144 */
1188 coherence();
1189 resetwait(&otg->otgsyssts);
1190 otg->otgsyscfg |= Sidle | Midle;
1191 coherence();
1192
1193 iprint("uhh...");
1194 uhh = (Uhh *)PHYSUHH;
1195 uhh->sysconfig |= Softreset;
1196 coherence();
1197 resetwait(&uhh->sysstatus);
1198 for (bound = 400*Mhz; !(uhh->sysstatus & Resetdone) && bound > 0;
1199 bound--)
1200 ;
1201 uhh->sysconfig |= Sidle | Midle;
1202
1203 /*
1204 * using the TLL seems to be an optimisation when talking
1205 * to another identical SoC, thus not very useful, so
1206 * force PHY (ULPI) mode.
1207 */
1208 /* this bit is normally off when we get here */
1209 uhh->hostconfig &= ~P1ulpi_bypass;
1210 coherence();
1211 if (uhh->hostconfig & P1ulpi_bypass)
1212 iprint("utmi (tll) mode..."); /* via tll */
1213 else
1214 /* external transceiver (phy), no tll */
1215 iprint("ulpi (phy) mode...");
1216
1217 tll = (Usbtll *)PHYSUSBTLL;
1218 if (probeaddr(PHYSUSBTLL) >= 0) {
1219 iprint("tll...");
1220 tll->sysconfig |= Softreset;
1221 coherence();
1222 resetwait(&tll->sysstatus);
1223 tll->sysconfig |= Sidle;
1224 coherence();
1225 } else
1226 iprint("no tll...");
1227 iprint("\n");
1228 }
1229
1230 /*
1231 * there are secure sdrc registers at 0x48002460
1232 * sdrc regs at PHYSSDRC; see spruf98c §1.2.8.2.
1233 * set or dump l4 prot regs at PHYSL4?
1234 */
1235 void
archreset(void)1236 archreset(void)
1237 {
1238 static int beenhere;
1239
1240 if (beenhere)
1241 return;
1242 beenhere = 1;
1243
1244 /* conservative temporary values until archconfinit runs */
1245 m->cpuhz = 500 * Mhz; /* beagle speed */
1246 m->delayloop = m->cpuhz/2000; /* initial estimate */
1247
1248 // dumpl3pr();
1249 prcachecfg();
1250 /* fight omap35x errata 2.0.1.104 */
1251 memset((void *)PHYSSWBOOTCFG, 0, 240);
1252 coherence();
1253
1254 setpadmodes();
1255 configclks(); /* may change cpu speed */
1256 configgpio();
1257
1258 archconfinit();
1259
1260 resetusb();
1261 fpon();
1262 }
1263
1264 void
archreboot(void)1265 archreboot(void)
1266 {
1267 Prm *prm = (Prm *)PHYSPRMGLBL;
1268
1269 iprint("archreboot: reset!\n");
1270 delay(20);
1271
1272 prm->rstctrl |= Rstgs;
1273 coherence();
1274 delay(500);
1275
1276 /* shouldn't get here */
1277 splhi();
1278 iprint("awaiting reset");
1279 for(;;) {
1280 delay(1000);
1281 print(".");
1282 }
1283 }
1284
1285 void
kbdinit(void)1286 kbdinit(void)
1287 {
1288 }
1289
1290 void
lastresortprint(char * buf,long bp)1291 lastresortprint(char *buf, long bp)
1292 {
1293 iprint("%.*s", (int)bp, buf); /* nothing else seems to work */
1294 }
1295
1296 static void
scmdump(ulong addr,int shorts)1297 scmdump(ulong addr, int shorts)
1298 {
1299 ushort reg;
1300 ushort *ptr;
1301
1302 ptr = (ushort *)addr;
1303 print("scm regs:\n");
1304 while (shorts-- > 0) {
1305 reg = *ptr++;
1306 print("%#p: %#ux\tinputenable %d pulltypeselect %d "
1307 "pulludenable %d muxmode %d\n",
1308 ptr, reg, (reg>>8) & 1, (reg>>4) & 1, (reg>>3) & 1,
1309 reg & 7);
1310 }
1311 }
1312
1313 char *cputype2name(char *buf, int size);
1314
1315 void
cpuidprint(void)1316 cpuidprint(void)
1317 {
1318 char name[64];
1319
1320 cputype2name(name, sizeof name);
1321 delay(250); /* let uart catch up */
1322 iprint("cpu%d: %lldMHz ARM %s\n", m->machno, m->cpuhz / Mhz, name);
1323 }
1324
1325 static void
missing(ulong addr,char * name)1326 missing(ulong addr, char *name)
1327 {
1328 static int firstmiss = 1;
1329
1330 if (probeaddr(addr) >= 0)
1331 return;
1332 if (firstmiss) {
1333 iprint("missing:");
1334 firstmiss = 0;
1335 } else
1336 iprint(",\n\t");
1337 iprint(" %s at %#lux", name, addr);
1338 }
1339
1340 /* verify that all the necessary device registers are accessible */
1341 void
chkmissing(void)1342 chkmissing(void)
1343 {
1344 delay(20);
1345 missing(PHYSSCM, "scm");
1346 missing(KZERO, "dram");
1347 missing(PHYSL3, "l3 config");
1348 missing(PHYSINTC, "intr ctlr");
1349 missing(PHYSTIMER1, "timer1");
1350 missing(PHYSCONS, "console uart2");
1351 missing(PHYSUART0, "uart0");
1352 missing(PHYSUART1, "uart1");
1353 missing(PHYSETHER, "smc9221"); /* not on beagle */
1354 missing(PHYSUSBOTG, "usb otg");
1355 missing(PHYSUHH, "usb uhh");
1356 missing(PHYSOHCI, "usb ohci");
1357 missing(PHYSEHCI, "usb ehci");
1358 missing(PHYSSDMA, "dma");
1359 missing(PHYSWDOG, "watchdog timer");
1360 missing(PHYSUSBTLL, "usb tll");
1361 iprint("\n");
1362 delay(20);
1363 }
1364
1365 void
archflashwp(Flash *,int)1366 archflashwp(Flash*, int)
1367 {
1368 }
1369
1370 /*
1371 * for ../port/devflash.c:/^flashreset
1372 * retrieve flash type, virtual base and length and return 0;
1373 * return -1 on error (no flash)
1374 */
1375 int
archflashreset(int bank,Flash * f)1376 archflashreset(int bank, Flash *f)
1377 {
1378 if(bank != 0)
1379 return -1;
1380 /*
1381 * this is set up for the igepv2 board.
1382 * if the beagleboard ever works, we'll have to sort this out.
1383 */
1384 f->type = "onenand";
1385 f->addr = (void*)PHYSNAND; /* mapped here by archreset */
1386 f->size = 0; /* done by probe */
1387 f->width = 1;
1388 f->interleave = 0;
1389 return 0;
1390 }
1391