1 /* 2 * values for Brightstar Engineering ipEngine 3 */ 4 enum { 5 /* CS assignment */ 6 BOOTCS = 0, /* flash */ 7 FPGACS = 1, /* 8Mb FPGA space */ 8 DRAMCS = 2, 9 FPGACONFCS = 3, /* FPGA config */ 10 CLOCKCS = 4, /* clock synth reg */ 11 }; 12 13 enum { 14 /* port A pins */ 15 VCLK= SIBIT(5), 16 BCLK= SIBIT(4), 17 18 /* port B */ 19 EnableVCLK= IBIT(30), 20 EnableEnet= IBIT(29), 21 EnableRS232= IBIT(28), 22 EnetFullDuplex= IBIT(16), 23 24 /* port C */ 25 nCONFIG = SIBIT(13), /* FPGA configuration */ 26 USBFullSpeed= SIBIT(12), 27 PDN= SIBIT(5), /* ? seems to control power to FPGA subsystem? */ 28 EnetLoopback= SIBIT(4), 29 30 /* nSTATUS is ip_b1, conf_done is ip_b0 in PIPR (hardware doc wrongly says ip_b2 and ip_b1) */ 31 32 }; 33