xref: /netbsd-src/sys/arch/x86/pci/lpssreg.h (revision 39de109673255a166c595047c9462821894fa538)
1 /* $NetBSD: lpssreg.h,v 1.1 2017/12/10 17:12:54 bouyer Exp $ */
2 
3 /*-
4  * Copyright (c) 2017 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Manuel Bouyer.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 /* LPSS registers, as found in several functions of Ivy Lake bridge */
33 #define LPSS_RESET	0x204
34 #define LPSS_RESET_DMA		__BIT(2)
35 #define LPSS_RESET_CTRL		__BITS(1,0)
36 #define LPSS_RESET_CTRL_ASSERT		0
37 #define LPSS_RESET_CTRL_REL		0x3
38 
39 #define LPSS_ACTIVELTR	0x210
40 #define LPSS_ACTIVELTR_SSCALE	__BITS(12,10)
41 #define LPSS_ACTIVELTR_SSCALE_1		(0x2 << 10)
42 #define LPSS_ACTIVELTR_SSCALE_32	(0x3 << 10)
43 #define LPSS_ACTIVELTR_SVALUE	__BITS(9,0)
44 
45 #define LPSS_IDLELTR	0x214
46 #define LPSS_IDLELTR_SSCALE	__BITS(12,10)
47 #define LPSS_IDLELTR_SSCALE_1		(0x2 << 10)
48 #define LPSS_IDLELTR_SSCALE_32		(0x3 << 10)
49 #define LPSS_IDLELTR_SVALUE	__BITS(9,0)
50 
51 #define LPSS_TXACK	0x218
52 #define LPSS_TXACK_OVF		__BIT(31)
53 #define LPSS_TXACK_CNT		__BITS(23,0)
54 
55 #define LPSS_RXACK	0x21C
56 #define LPSS_RXACK_OVF		__BIT(31)
57 #define LPSS_RXACK_CNT		__BITS(23,0)
58 
59 #define LPSS_TX_IRQ	0x220
60 #define LPSS_TX_IRQ_MSK		__BIT(1)
61 #define LPSS_TX_IRQ_I		__BIT(0)
62 
63 #define LPSS_TX_IRQ_CLR	0x224
64 #define LPSS_TX_IRQ_CLRI	__BIT(0)
65 
66 #define LPSS_CLKGATE	0x238
67 #define LPSS_CLKGATE_DMA	__BITS(3,2)
68 #define LPSS_CLKGATE_DMA_AUTO		(0x0 << 2)
69 #define LPSS_CLKGATE_DMA_OFF		(0x2 << 2)
70 #define LPSS_CLKGATE_DMA_ON		(0x3 << 2)
71 #define LPSS_CLKGATE_CTRL	__BITS(1,0)
72 #define LPSS_CLKGATE_CTRL_AUTO		(0x0 << 0)
73 #define LPSS_CLKGATE_CTRL_OFF		(0x2 << 0)
74 #define LPSS_CLKGATE_CTRL_ON		(0x3 << 0)
75 
76 #define LPSS_REMAP_LO	0x240
77 
78 #define LPSS_REMAP_HI	0x244
79 
80 #define LPSS_DEVIDLE	0x24c
81 #define LPSS_DEVIDLE_IRQ	__BIT(4)
82 #define LPSS_DEVIDLE_RESTORE	__BIT(3)
83 #define LPSS_DEVIDLE_IDLE	__BIT(2)
84 #define LPSS_DEVIDLE_INPROG	__BIT(0)
85 
86 #define LPSS_CAP	0x2fc
87 #define LPSS_CAP_DMA		__BIT(8)
88 #define LPSS_CAP_TYPE		__BITS(7,4)
89 #define LPSS_CAP_TYPE_I2C		(0x0 << 4)
90 #define LPSS_CAP_TYPE_UART		(0x1 << 4)
91 #define LPSS_CAP_TYPE_SPI		(0x2 << 4)
92 #define LPSS_CAP_INSTANCE	__BITS(3,0)
93