1 /* $NetBSD: dec_3100.c,v 1.54 2014/03/24 19:31:39 christos Exp $ */
2
3 /*
4 * Copyright (c) 1998 Jonathan Stone. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Jonathan Stone for
17 * the NetBSD Project.
18 * 4. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * Copyright (c) 1988 University of Utah.
35 * Copyright (c) 1992, 1993
36 * The Regents of the University of California. All rights reserved.
37 *
38 * This code is derived from software contributed to Berkeley by
39 * the Systems Programming Group of the University of Utah Computer
40 * Science Department, The Mach Operating System project at
41 * Carnegie-Mellon University and Ralph Campbell.
42 *
43 * Redistribution and use in source and binary forms, with or without
44 * modification, are permitted provided that the following conditions
45 * are met:
46 * 1. Redistributions of source code must retain the above copyright
47 * notice, this list of conditions and the following disclaimer.
48 * 2. Redistributions in binary form must reproduce the above copyright
49 * notice, this list of conditions and the following disclaimer in the
50 * documentation and/or other materials provided with the distribution.
51 * 3. Neither the name of the University nor the names of its contributors
52 * may be used to endorse or promote products derived from this software
53 * without specific prior written permission.
54 *
55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
65 * SUCH DAMAGE.
66 *
67 * @(#)machdep.c 8.3 (Berkeley) 1/12/94
68 */
69
70 #define __INTR_PRIVATE
71 #include <sys/cdefs.h>
72 __KERNEL_RCSID(0, "$NetBSD: dec_3100.c,v 1.54 2014/03/24 19:31:39 christos Exp $");
73
74 #include <sys/param.h>
75 #include <sys/cpu.h>
76 #include <sys/device.h>
77 #include <sys/intr.h>
78 #include <sys/lwp.h>
79 #include <sys/systm.h>
80
81 #include <pmax/sysconf.h>
82
83 #include <mips/mips/mips_mcclock.h> /* mcclock CPUspeed estimation */
84
85 #include <dev/tc/tcvar.h> /* tc_addr_t */
86
87 #include <pmax/pmax/machdep.h>
88 #include <pmax/pmax/kn01.h>
89
90 #include <pmax/ibus/ibusvar.h>
91
92 #include <dev/dec/dzreg.h>
93 #include <dev/dec/dzvar.h>
94 #include <dev/dec/dzkbdvar.h>
95 #include <pmax/pmax/cons.h>
96
97 #include "pm.h"
98
99 void dec_3100_init(void); /* XXX */
100 static void dec_3100_bus_reset(void);
101
102 static void dec_3100_cons_init(void);
103 static void dec_3100_errintr(void);
104 static void dec_3100_intr(uint32_t, vaddr_t, uint32_t);
105 static void dec_3100_intr_establish(device_t, void *,
106 int, int (*)(void *), void *);
107
108 #define kn01_wbflush() wbflush() /* XXX to be corrected XXX */
109
110 static const struct ipl_sr_map dec_3100_ipl_sr_map = {
111 .sr_bits = {
112 [IPL_NONE] = 0,
113 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
114 [IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK,
115 [IPL_VM] = MIPS_SPL_0_1_2,
116 [IPL_SCHED] = MIPS_SPLHIGH,
117 [IPL_DDB] = MIPS_SPLHIGH,
118 [IPL_HIGH] = MIPS_SPLHIGH,
119 }
120 };
121
122 void
dec_3100_init(void)123 dec_3100_init(void)
124 {
125 const char *submodel;
126
127 platform.iobus = "baseboard";
128 platform.bus_reset = dec_3100_bus_reset;
129 platform.cons_init = dec_3100_cons_init;
130 platform.iointr = dec_3100_intr;
131 platform.intr_establish = dec_3100_intr_establish;
132 platform.memsize = memsize_scan;
133 /* no high resolution timer available */
134
135 ipl_sr_map = dec_3100_ipl_sr_map;
136
137 /* calibrate cpu_mhz value */
138 mc_cpuspeed(MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK), MIPS_INT_MASK_3);
139
140 if (mips_options.mips_cpu_mhz < 15)
141 submodel = "2100 (PMIN)";
142 else
143 submodel = "3100 (PMAX)";
144 cpu_setmodel("DECstation %s", submodel);
145 }
146
147 /*
148 * Initialize the memory system and I/O buses.
149 */
150 static void
dec_3100_bus_reset(void)151 dec_3100_bus_reset(void)
152 {
153
154 /* nothing to do */
155 kn01_wbflush();
156 }
157
158 static void
dec_3100_cons_init(void)159 dec_3100_cons_init(void)
160 {
161 int kbd, crt, screen;
162
163 kbd = crt = screen = 0;
164 prom_findcons(&kbd, &crt, &screen);
165
166 if (screen > 0) {
167 #if NPM > 0
168 if (pm_cnattach() > 0) {
169 dz_ibus_cnsetup(KN01_SYS_DZ);
170 dzkbd_cnattach(NULL);
171 return;
172 }
173 #endif
174 printf("No framebuffer device configured: ");
175 printf("using serial console\n");
176 }
177 /*
178 * Delay to allow PROM putchars to complete.
179 * FIFO depth * character time,
180 * character time = (1000000 / (defaultrate / 10))
181 */
182 DELAY(160000000 / 9600); /* XXX */
183
184 dz_ibus_cnsetup(KN01_SYS_DZ);
185 dz_ibus_cnattach(kbd);
186 }
187
188 #define CALLINTR(vvv, cp0) \
189 do { \
190 if (ipending & (cp0)) { \
191 intrtab[vvv].ih_count.ev_count++; \
192 (*intrtab[vvv].ih_func)(intrtab[vvv].ih_arg); \
193 } \
194 } while (/*CONSTCOND*/0)
195
196 static void
dec_3100_intr(uint32_t status,vaddr_t pc,uint32_t ipending)197 dec_3100_intr(uint32_t status, vaddr_t pc, uint32_t ipending)
198 {
199
200 /* handle clock interrupts ASAP */
201 if (ipending & MIPS_INT_MASK_3) {
202 struct clockframe cf;
203
204 __asm volatile("lbu $0,48(%0)" ::
205 "r"(MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK)));
206 cf.pc = pc;
207 cf.sr = status;
208 cf.intr = (curcpu()->ci_idepth > 1);
209 hardclock(&cf);
210 pmax_clock_evcnt.ev_count++;
211 }
212
213 CALLINTR(SYS_DEV_SCSI, MIPS_INT_MASK_0);
214 CALLINTR(SYS_DEV_LANCE, MIPS_INT_MASK_1);
215 CALLINTR(SYS_DEV_SCC0, MIPS_INT_MASK_2);
216
217 if (ipending & MIPS_INT_MASK_4) {
218 dec_3100_errintr();
219 pmax_memerr_evcnt.ev_count++;
220 }
221 }
222
223 static void
dec_3100_intr_establish(device_t dev,void * cookie,int level,int (* handler)(void *),void * arg)224 dec_3100_intr_establish(device_t dev, void *cookie, int level,
225 int (*handler)(void *), void *arg)
226 {
227
228 intrtab[(intptr_t)cookie].ih_func = handler;
229 intrtab[(intptr_t)cookie].ih_arg = arg;
230 }
231
232
233 /*
234 * Handle memory errors.
235 */
236 static void
dec_3100_errintr(void)237 dec_3100_errintr(void)
238 {
239 uint16_t csr;
240
241 csr = *(volatile uint16_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CSR);
242
243 if (csr & KN01_CSR_MERR) {
244 printf("Memory error at 0x%x\n",
245 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_ERRADR));
246 panic("Mem error interrupt");
247 }
248 csr = (csr & ~KN01_CSR_MBZ) | 0xff;
249 *(volatile uint16_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CSR) = csr;
250 }
251