1/* $NetBSD: locore_ingenic.S,v 1.1 2017/05/21 06:49:13 skrll Exp $ */ 2 3/*- 4 * Copyright (c) 2017 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#include <mips/asm.h> 33RCSID("$NetBSD: locore_ingenic.S,v 1.1 2017/05/21 06:49:13 skrll Exp $") 34 35#include <mips/cpuregs.h> 36#include <mips/ingenic/ingenic_coreregs.h> 37 38#include "assym.h" 39 40 .set noreorder 41 .set noat 42 .set arch=mips32r2 43 44 .text 45 46/* 47 * uint32_t mips_cp0_corectrl_read(void) 48 * 49 * Return the current value of the CP0 Core Control register. 50 */ 51LEAF(mips_cp0_corectrl_read) 52 mfc0 v0, CP0_CORE_CTRL 53 jr ra 54 nop 55END(mips_cp0_corectrl_read) 56 57/* 58 * void mips_cp0_corectrl_write(uint32_t) 59 * 60 * Set the value of the CP0 Core Control register. 61 */ 62LEAF(mips_cp0_corectrl_write) 63 mtc0 a0, CP0_CORE_CTRL 64 jr.hb ra 65 nop 66END(mips_cp0_corectrl_write) 67 68/* 69 * uint32_t mips_cp0_corestatus_read(void) 70 * 71 * Return the current value of the CP0 Core Status register. 72 */ 73LEAF(mips_cp0_corestatus_read) 74 mfc0 v0, CP0_CORE_STATUS 75 jr ra 76 nop 77END(mips_cp0_corestatus_read) 78 79/* 80 * void mips_cp0_corestatus_write(uint32_t) 81 * 82 * Set the value of the CP0 Core Status register. 83 */ 84LEAF(mips_cp0_corestatus_write) 85 mtc0 a0, CP0_CORE_STATUS 86 jr.hb ra 87 nop 88END(mips_cp0_corestatus_write) 89 90 91/* 92 * uint32_t mips_cp0_corereim_read(void) 93 * 94 * Return the current value of the CP0 Reset Entry & IRQ Mask register. 95 */ 96LEAF(mips_cp0_corereim_read) 97 mfc0 v0, CP0_CORE_REIM 98 jr ra 99 nop 100END(mips_cp0_corereim_read) 101 102/* 103 * void mips_cp0_corereim_write(uint32_t) 104 * 105 * Set the value of the CP0 Core Reset Entry & IRQ Mask register. 106 */ 107LEAF(mips_cp0_corereim_write) 108 mtc0 a0, CP0_CORE_REIM 109 jr.hb ra 110 nop 111END(mips_cp0_corereim_write) 112 113 114/* 115 * uintptr_t mips_cp0_corembox_read(u_int sel) 116 * 117 * Return the current value of the selected CP0 Mailbox register. 118 */ 119LEAF(mips_cp0_corembox_read) 120 sll a0, 2 121 PTR_LA t9, 1f 122 PTR_ADDU t9, a0 123 jr t9 124 nop 1251: 126 jr ra 127 mfc0 v0, CP0_CORE0_MBOX 128 jr ra 129 mfc0 v0, CP0_CORE1_MBOX 130 jr ra 131END(mips_cp0_corembox_read) 132 133/* 134 * void mips_cp0_watchlo_write(u_int sel, uinte32_t val) 135 * 136 * Set the current value of the selected CP0 Mailbox register. 137 */ 138LEAF(mips_cp0_corembox_write) 139 sll a0, 2 140 PTR_LA t9, 1f 141 PTR_ADDU t9, a0 142 jr t9 143 nop 1441: 145 jr.hb ra 146 mtc0 a1, CP0_CORE0_MBOX 147 jr.hb ra 148 mtc0 a1, CP0_CORE1_MBOX 149 jr.hb ra 150END(mips_cp0_corembox_write) 151