1/* $NetBSD: cache_r5k_subr.S,v 1.5 2022/04/08 10:17:54 andvar Exp $ */ 2 3/* 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. Neither the name of the University nor the names of its contributors 13 * may be used to endorse or promote products derived from this software 14 * without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#include <mips/asm.h> 30#include <mips/cpuregs.h> 31#include <mips/cache_r4k.h> 32#include <mips/cache_r5k.h> 33 34#include "assym.h" 35 36 .set mips3 37 .set noreorder 38 39/* 40 * r5k_enable_sdcache: 41 * 42 * Enable and clear out the R5k secondary (unified) cache. 43 */ 44LEAF_NOPROFILE(r5k_enable_sdcache) 45 INT_L t2, _C_LABEL(mips_cache_info)+MCI_SDCACHE_SIZE 46 PTR_LA t1, MIPS_KSEG0_START 47 48 beq t2, zero, 3f # if no sdcache, we can bail now 49 nop 50 51 PTR_ADDU t2, t1, t2 52 53 PTR_LA v0, 1f 54 or v0, MIPS_KSEG1_START 55 56 j v0 # run the rest from uncached space 57 nop 58 591: 60 mfc0 v0, MIPS_COP_0_CONFIG 61 or v1, v0, MIPS3_CONFIG_SE 62 mtc0 v1, MIPS_COP_0_CONFIG # enable the secondary cache 63 nop 64 nop 65 nop 66 672: 68 cache CACHEOP_R5K_Page_Invalidate_S, 0(t1) 69 PTR_ADDU t1, t1, R5K_SC_PAGESIZE 70 71 sltu v0, t1, t2 72 bne v0, zero, 2b 73 nop 74 753: 76 j ra 77 nop 78END(r5k_enable_sdcache) 79