1 /* $NetBSD: if_mc_obio.c,v 1.20 2023/12/20 00:40:43 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 1997 David Huang <khym@azeotrope.org>
5 * All rights reserved.
6 *
7 * Portions of this code are based on code by Denton Gentry <denny1@home.com>
8 * and Yanagisawa Takeshi <yanagisw@aa.ap.titech.ac.jp>.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 */
30
31 /*
32 * Bus attachment and DMA routines for the mc driver (Centris/Quadra
33 * 660av and Quadra 840av onboard ethernet, based on the AMD Am79C940
34 * MACE ethernet chip). Also uses the PSC (Peripheral Subsystem
35 * Controller) for DMA to and from the MACE.
36 */
37
38 #include <sys/cdefs.h>
39 __KERNEL_RCSID(0, "$NetBSD: if_mc_obio.c,v 1.20 2023/12/20 00:40:43 thorpej Exp $");
40
41 #include "opt_ddb.h"
42
43 #include <sys/param.h>
44 #include <sys/device.h>
45 #include <sys/socket.h>
46 #include <sys/systm.h>
47
48 #include <sys/rndsource.h>
49
50 #include <net/if.h>
51 #include <net/if_ether.h>
52
53 #include <uvm/uvm_extern.h>
54
55 #include <machine/bus.h>
56 #include <machine/psc.h>
57
58 #include <mac68k/obio/obiovar.h>
59 #include <mac68k/dev/if_mcreg.h>
60 #include <mac68k/dev/if_mcvar.h>
61
62 #define MACE_REG_BASE 0x50F1C000
63 #define MACE_PROM_BASE 0x50F08000
64
65 hide int mc_obio_match(device_t, cfdata_t, void *);
66 hide void mc_obio_attach(device_t, device_t, void *);
67 hide void mc_obio_init(struct mc_softc *);
68 hide void mc_obio_put(struct mc_softc *, u_int);
69 hide int mc_dmaintr(void *);
70 hide void mc_reset_rxdma(struct mc_softc *);
71 hide void mc_reset_rxdma_set(struct mc_softc *, int);
72 hide void mc_reset_txdma(struct mc_softc *);
73 hide int mc_obio_getaddr(struct mc_softc *, u_int8_t *);
74
75 CFATTACH_DECL_NEW(mc_obio, sizeof(struct mc_softc),
76 mc_obio_match, mc_obio_attach, NULL, NULL);
77
78 hide int
mc_obio_match(device_t parent,cfdata_t cf,void * aux)79 mc_obio_match(device_t parent, cfdata_t cf, void *aux)
80 {
81 struct obio_attach_args *oa = aux;
82 bus_space_handle_t bsh;
83 int found = 0;
84
85 if (current_mac_model->class != MACH_CLASSAV)
86 return 0;
87
88 if (bus_space_map(oa->oa_tag, MACE_REG_BASE, MC_REGSIZE, 0, &bsh))
89 return 0;
90
91 /*
92 * Make sure the MACE's I/O space is readable, and if it is,
93 * try to read the CHIPID register. A MACE will always have
94 * 0x?940, where the ? depends on the chip version.
95 */
96 if (mac68k_bus_space_probe(oa->oa_tag, bsh, 0, 1)) {
97 if ((bus_space_read_1(
98 oa->oa_tag, bsh, MACE_REG(MACE_CHIPIDL)) == 0x40) &&
99 ((bus_space_read_1(
100 oa->oa_tag, bsh, MACE_REG(MACE_CHIPIDH)) & 0xf) == 9))
101 found = 1;
102 }
103
104 bus_space_unmap(oa->oa_tag, bsh, MC_REGSIZE);
105
106 return found;
107 }
108
109 hide void
mc_obio_attach(device_t parent,device_t self,void * aux)110 mc_obio_attach(device_t parent, device_t self, void *aux)
111 {
112 struct obio_attach_args *oa = (struct obio_attach_args *)aux;
113 struct mc_softc *sc = device_private(self);
114 u_int8_t myaddr[ETHER_ADDR_LEN];
115 int rsegs;
116
117 sc->sc_dev = self;
118 sc->sc_regt = oa->oa_tag;
119 sc->sc_biucc = XMTSP_64;
120 sc->sc_fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU |
121 XMTBRST | RCVBRST;
122 sc->sc_plscc = PORTSEL_AUI;
123
124 if (bus_space_map(sc->sc_regt, MACE_REG_BASE, MC_REGSIZE, 0,
125 &sc->sc_regh)) {
126 printf(": failed to map space for MACE regs.\n");
127 return;
128 }
129
130 if (mc_obio_getaddr(sc, myaddr)) {
131 printf(": failed to get MAC address.\n");
132 return;
133 }
134
135 /* allocate memory for transmit and receive DMA buffers */
136 sc->sc_dmat = oa->oa_dmat;
137 if (bus_dmamem_alloc(sc->sc_dmat, 2 * 0x800, 0, 0, &sc->sc_dmasegs_tx,
138 1, &rsegs, BUS_DMA_NOWAIT) != 0) {
139 printf(": failed to allocate TX DMA buffers.\n");
140 return;
141 }
142
143 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_dmasegs_tx, rsegs, 2 * 0x800,
144 (void*)&sc->sc_txbuf, BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) {
145 printf(": failed to map TX DMA buffers.\n");
146 return;
147 }
148
149 if (bus_dmamem_alloc(sc->sc_dmat, MC_RXDMABUFS * 0x800, 0, 0,
150 &sc->sc_dmasegs_rx, 1, &rsegs, BUS_DMA_NOWAIT) != 0) {
151 printf(": failed to allocate RX DMA buffers.\n");
152 return;
153 }
154
155 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_dmasegs_rx, rsegs,
156 MC_RXDMABUFS * 0x800, (void*)&sc->sc_rxbuf,
157 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) {
158 printf(": failed to map RX DMA buffers.\n");
159 return;
160 }
161
162 if (bus_dmamap_create(sc->sc_dmat, 2 * 0x800, 1, 2 * 0x800, 0,
163 BUS_DMA_NOWAIT, &sc->sc_dmam_tx) != 0) {
164 printf(": failed to allocate TX DMA map.\n");
165 return;
166 }
167
168 if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmam_tx, sc->sc_txbuf,
169 2 * 0x800, NULL, BUS_DMA_NOWAIT) != 0) {
170 printf(": failed to map TX DMA mapping.\n");
171 return;
172 }
173
174 if (bus_dmamap_create(sc->sc_dmat, MC_RXDMABUFS * 0x800, 1,
175 MC_RXDMABUFS * 0x800, 0, BUS_DMA_NOWAIT, &sc->sc_dmam_rx) != 0) {
176 printf(": failed to allocate RX DMA map.\n");
177 return;
178 }
179
180 if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmam_rx, sc->sc_rxbuf,
181 MC_RXDMABUFS * 0x800, NULL, BUS_DMA_NOWAIT) != 0) {
182 printf(": failed to map RX DMA mapping.\n");
183 return;
184 }
185
186 sc->sc_txbuf_phys = sc->sc_dmasegs_tx.ds_addr;
187 sc->sc_rxbuf_phys = sc->sc_dmasegs_rx.ds_addr;
188
189 sc->sc_bus_init = mc_obio_init;
190 sc->sc_putpacket = mc_obio_put;
191
192 /* disable receive DMA */
193 psc_reg2(PSC_ENETRD_CTL) = 0x8800;
194 psc_reg2(PSC_ENETRD_CTL) = 0x1000;
195 psc_reg2(PSC_ENETRD_CMD + PSC_SET0) = 0x1100;
196 psc_reg2(PSC_ENETRD_CMD + PSC_SET1) = 0x1100;
197
198 /* disable transmit DMA */
199 psc_reg2(PSC_ENETWR_CTL) = 0x8800;
200 psc_reg2(PSC_ENETWR_CTL) = 0x1000;
201 psc_reg2(PSC_ENETWR_CMD + PSC_SET0) = 0x1100;
202 psc_reg2(PSC_ENETWR_CMD + PSC_SET1) = 0x1100;
203
204 /* install interrupt handlers */
205 add_psc_lev4_intr(PSCINTR_ENET_DMA, mc_dmaintr, sc);
206 add_psc_lev3_intr(mcintr, sc);
207
208 /* enable MACE DMA interrupts */
209 psc_reg1(PSC_LEV4_IER) = 0x80 | (1 << PSCINTR_ENET_DMA);
210
211 /* don't know what this does */
212 psc_reg2(PSC_ENETWR_CTL) = 0x9000;
213 psc_reg2(PSC_ENETRD_CTL) = 0x9000;
214 psc_reg2(PSC_ENETWR_CTL) = 0x0400;
215 psc_reg2(PSC_ENETRD_CTL) = 0x0400;
216
217 /* enable MACE interrupts */
218 psc_reg1(PSC_LEV3_IER) = 0x80 | (1 << PSCINTR_ENET);
219
220 /* mcsetup returns 1 if something fails */
221 if (mcsetup(sc, myaddr)) {
222 /* disable interrupts */
223 psc_reg1(PSC_LEV4_IER) = (1 << PSCINTR_ENET_DMA);
224 psc_reg1(PSC_LEV3_IER) = (1 << PSCINTR_ENET);
225 /* remove interrupt handlers */
226 remove_psc_lev4_intr(PSCINTR_ENET_DMA);
227 remove_psc_lev3_intr();
228
229 bus_space_unmap(sc->sc_regt, sc->sc_regh, MC_REGSIZE);
230 return;
231 }
232 }
233
234 /* Bus-specific initialization */
235 hide void
mc_obio_init(struct mc_softc * sc)236 mc_obio_init(struct mc_softc *sc)
237 {
238 mc_reset_rxdma(sc);
239 mc_reset_txdma(sc);
240 }
241
242 hide void
mc_obio_put(struct mc_softc * sc,u_int len)243 mc_obio_put(struct mc_softc *sc, u_int len)
244 {
245 int offset = sc->sc_txset == 0 ? 0 : 0x800;
246
247 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmam_tx, offset, 0x800,
248 BUS_DMASYNC_PREWRITE);
249 psc_reg4(PSC_ENETWR_ADDR + sc->sc_txset) = sc->sc_txbuf_phys + offset;
250 psc_reg4(PSC_ENETWR_LEN + sc->sc_txset) = len;
251 psc_reg2(PSC_ENETWR_CMD + sc->sc_txset) = 0x9800;
252 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmam_tx, offset, 0x800,
253 BUS_DMASYNC_POSTWRITE);
254
255 sc->sc_txset ^= 0x10;
256 }
257
258 /*
259 * Interrupt handler for the MACE DMA completion interrupts
260 */
261 int
mc_dmaintr(void * arg)262 mc_dmaintr(void *arg)
263 {
264 struct mc_softc *sc = arg;
265 u_int16_t status;
266 u_int32_t bufsleft, which;
267 int head;
268
269 /*
270 * Not sure what this does... figure out if this interrupt is
271 * really ours?
272 */
273 while ((which = psc_reg4(0x804)) != psc_reg4(0x804))
274 ;
275 if ((which & 0x60000000) == 0)
276 return 0;
277
278 /* Get the read channel status */
279 status = psc_reg2(PSC_ENETRD_CTL);
280 if (status & 0x2000) {
281 /* I think this is an exceptional condition. Reset the DMA */
282 mc_reset_rxdma(sc);
283 #ifdef MCDEBUG
284 printf("%s: resetting receive DMA channel (status 0x%04x)\n",
285 device_xname(sc->sc_dev), status);
286 #endif
287 } else if (status & 0x100) {
288 /* We've received some packets from the MACE */
289 int offset;
290
291 /* Clear the interrupt */
292 psc_reg2(PSC_ENETRD_CMD + sc->sc_rxset) = 0x1100;
293
294 /* See how may receive buffers are left */
295 bufsleft = psc_reg4(PSC_ENETRD_LEN + sc->sc_rxset);
296 head = MC_RXDMABUFS - bufsleft;
297
298 #if 0 /* I don't think this should ever happen */
299 if (head == sc->sc_tail) {
300 #ifdef MCDEBUG
301 printf("%s: head == tail: suspending DMA?\n",
302 device_xname(sc->sc_dev));
303 #endif
304 psc_reg2(PSC_ENETRD_CMD + sc->sc_rxset) = 0x9000;
305 }
306 #endif
307
308 /* Loop through, processing each of the packets */
309 for (; sc->sc_tail < head; sc->sc_tail++) {
310 offset = sc->sc_tail * 0x800;
311
312 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmam_rx,
313 PAGE_SIZE + offset, 0x800,
314 BUS_DMASYNC_PREREAD);
315
316 sc->sc_rxframe.rx_rcvcnt = sc->sc_rxbuf[offset];
317 sc->sc_rxframe.rx_rcvsts = sc->sc_rxbuf[offset+2];
318 sc->sc_rxframe.rx_rntpc = sc->sc_rxbuf[offset+4];
319 sc->sc_rxframe.rx_rcvcc = sc->sc_rxbuf[offset+6];
320 sc->sc_rxframe.rx_frame = sc->sc_rxbuf + offset + 16;
321
322 mc_rint(sc);
323
324 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmam_rx,
325 PAGE_SIZE + offset, 0x800,
326 BUS_DMASYNC_POSTREAD);
327 }
328
329 /*
330 * If we're out of buffers, reset this register set
331 * and switch to the other one. Otherwise, reactivate
332 * this set.
333 */
334 if (bufsleft == 0) {
335 mc_reset_rxdma_set(sc, sc->sc_rxset);
336 sc->sc_rxset ^= 0x10;
337 } else
338 psc_reg2(PSC_ENETRD_CMD + sc->sc_rxset) = 0x9800;
339 }
340
341 /* Get the write channel status */
342 status = psc_reg2(PSC_ENETWR_CTL);
343 if (status & 0x2000) {
344 /* I think this is an exceptional condition. Reset the DMA */
345 mc_reset_txdma(sc);
346 #ifdef MCDEBUG
347 printf("%s: resetting transmit DMA channel (status 0x%04x)\n",
348 device_xname(sc->sc_dev), status);
349 #endif
350 } else if (status & 0x100) {
351 /* Clear the interrupt and switch register sets */
352 psc_reg2(PSC_ENETWR_CMD + sc->sc_txseti) = 0x100;
353 sc->sc_txseti ^= 0x10;
354 }
355
356 return 1;
357 }
358
359
360 hide void
mc_reset_rxdma(struct mc_softc * sc)361 mc_reset_rxdma(struct mc_softc *sc)
362 {
363 u_int8_t maccc;
364
365 /* Disable receiver, reset the DMA channels */
366 maccc = NIC_GET(sc, MACE_MACCC);
367 NIC_PUT(sc, MACE_MACCC, maccc & ~ENRCV);
368 psc_reg2(PSC_ENETRD_CTL) = 0x8800;
369 mc_reset_rxdma_set(sc, 0);
370 psc_reg2(PSC_ENETRD_CTL) = 0x400;
371
372 psc_reg2(PSC_ENETRD_CTL) = 0x8800;
373 mc_reset_rxdma_set(sc, 0x10);
374 psc_reg2(PSC_ENETRD_CTL) = 0x400;
375
376 /* Reenable receiver, reenable DMA */
377 NIC_PUT(sc, MACE_MACCC, maccc);
378 sc->sc_rxset = 0;
379
380 psc_reg2(PSC_ENETRD_CMD + PSC_SET0) = 0x9800;
381 psc_reg2(PSC_ENETRD_CMD + PSC_SET1) = 0x9800;
382 }
383
384 hide void
mc_reset_rxdma_set(struct mc_softc * sc,int set)385 mc_reset_rxdma_set(struct mc_softc *sc, int set)
386 {
387 /* disable DMA while modifying the registers, then reenable DMA */
388 psc_reg2(PSC_ENETRD_CMD + set) = 0x0100;
389 psc_reg4(PSC_ENETRD_ADDR + set) = sc->sc_rxbuf_phys;
390 psc_reg4(PSC_ENETRD_LEN + set) = MC_RXDMABUFS;
391 psc_reg2(PSC_ENETRD_CMD + set) = 0x9800;
392 sc->sc_tail = 0;
393 }
394
395 hide void
mc_reset_txdma(struct mc_softc * sc)396 mc_reset_txdma(struct mc_softc *sc)
397 {
398 u_int8_t maccc;
399
400 psc_reg2(PSC_ENETWR_CTL) = 0x8800;
401 maccc = NIC_GET(sc, MACE_MACCC);
402 NIC_PUT(sc, MACE_MACCC, maccc & ~ENXMT);
403 sc->sc_txset = sc->sc_txseti = 0;
404 psc_reg2(PSC_ENETWR_CTL) = 0x400;
405 NIC_PUT(sc, MACE_MACCC, maccc);
406 }
407
408 hide int
mc_obio_getaddr(struct mc_softc * sc,u_int8_t * lladdr)409 mc_obio_getaddr(struct mc_softc *sc, u_int8_t *lladdr)
410 {
411 bus_space_handle_t bsh;
412 u_char csum;
413
414 if (bus_space_map(sc->sc_regt, MACE_PROM_BASE, 8*16, 0, &bsh)) {
415 printf(": failed to map space to read MACE address.\n%s",
416 device_xname(sc->sc_dev));
417 return (-1);
418 }
419
420 if (!mac68k_bus_space_probe(sc->sc_regt, bsh, 0, 1)) {
421 bus_space_unmap(sc->sc_regt, bsh, 8*16);
422 return (-1);
423 }
424
425 csum = mc_get_enaddr(sc->sc_regt, bsh, 1, lladdr);
426 if (csum != 0xff)
427 printf(": ethernet PROM checksum failed (0x%x != 0xff)\n%s",
428 (int)csum, device_xname(sc->sc_dev));
429
430 bus_space_unmap(sc->sc_regt, bsh, 8*16);
431
432 return (csum == 0xff ? 0 : -1);
433 }
434