1 /* $NetBSD: interrupt.c,v 1.28 2024/03/13 12:44:30 riastradh Exp $ */
2
3 /*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.28 2024/03/13 12:44:30 riastradh Exp $");
34
35 #include <sys/param.h>
36 #include <sys/cpu.h>
37 #include <sys/device.h>
38 #include <sys/intr.h>
39
40 #include <mips/locore.h>
41 #include <mips/mips3_clock.h>
42
43 void
intr_init(void)44 intr_init(void)
45 {
46
47 evbmips_intr_init(); /* board specific stuff */
48 }
49
50 void
cpu_intr(int ppl,vaddr_t pc,uint32_t status)51 cpu_intr(int ppl, vaddr_t pc, uint32_t status)
52 {
53 struct cpu_info * const ci = curcpu();
54 uint32_t pending;
55 int ipl;
56 const int mtx_count = ci->ci_mtx_count;
57 const u_int biglock_count = ci->ci_biglock_count;
58 const u_int blcnt = curlwp->l_blcnt;
59
60 KASSERT(ci->ci_cpl == IPL_HIGH);
61 KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
62
63 ci->ci_data.cpu_nintr++;
64
65 while (ppl < (ipl = splintr(&pending))) {
66 KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
67 splx(ipl); /* lower to interrupt level */
68 KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
69
70 KASSERTMSG(ci->ci_cpl == ipl,
71 "%s: cpl (%d) != ipl (%d)", __func__, ci->ci_cpl, ipl);
72 KASSERT(pending != 0);
73
74 struct clockframe cf = {
75 .pc = pc,
76 .sr = status,
77 .intr = (ci->ci_idepth > 1)
78 };
79
80 #ifdef MIPS3_ENABLE_CLOCK_INTR
81 if (pending & MIPS_INT_MASK_5) {
82
83 KASSERTMSG(ipl == IPL_SCHED,
84 "%s: ipl (%d) != IPL_SCHED (%d)",
85 __func__, ipl, IPL_SCHED);
86 /* call the common MIPS3 clock interrupt handler */
87 mips3_clockintr(&cf);
88 pending ^= MIPS_INT_MASK_5;
89 }
90 #endif
91
92 if (pending != 0) {
93 /* Process I/O and error interrupts. */
94 evbmips_iointr(ipl, pending, &cf);
95 }
96 KASSERT(biglock_count == ci->ci_biglock_count);
97 KASSERT(blcnt == curlwp->l_blcnt);
98 KASSERT(mtx_count == ci->ci_mtx_count);
99
100 /*
101 * If even our spl is higher now (due to interrupting while
102 * spin-lock is held and higher IPL spin-lock is locked, it
103 * can no longer be locked so it's safe to lower IPL back
104 * to ppl.
105 */
106 (void) splhigh(); /* disable interrupts */
107 }
108
109 KASSERT(ci->ci_cpl == IPL_HIGH);
110 KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE);
111 }
112