1 /* $NetBSD: dbau1550.c,v 1.13 2014/03/12 22:21:07 mrg Exp $ */
2
3 /*-
4 * Copyright (c) 2006 Itronix Inc.
5 * All rights reserved.
6 *
7 * Written by Garrett D'Amore for Itronix Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of Itronix Inc. may not be used to endorse
18 * or promote products derived from this software without specific
19 * prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
28 * ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include <sys/cdefs.h>
35 __KERNEL_RCSID(0, "$NetBSD: dbau1550.c,v 1.13 2014/03/12 22:21:07 mrg Exp $");
36
37 #include <sys/param.h>
38 #include <sys/bus.h>
39 #include <sys/kernel.h>
40 #include <sys/proc.h>
41 #include <sys/time.h>
42
43 #include <mips/locore.h>
44
45 #include <mips/alchemy/include/aureg.h>
46 #include <mips/alchemy/dev/aupcmciavar.h>
47 #include <mips/alchemy/dev/aupcmciareg.h>
48 #include <mips/alchemy/dev/augpioreg.h>
49 #include <mips/alchemy/dev/auspivar.h>
50
51 #include <evbmips/alchemy/obiovar.h>
52 #include <evbmips/alchemy/board.h>
53 #include <evbmips/alchemy/dbau1550reg.h>
54
55 #include "auspi.h"
56
57 /*
58 * This should be converted to use bus_space routines.
59 */
60 #define GET16(x) \
61 (*((volatile uint16_t *)MIPS_PHYS_TO_KSEG1(x)))
62 #define PUT16(x, v) \
63 (*((volatile uint16_t *)MIPS_PHYS_TO_KSEG1(x)) = (v))
64 #define GET32(x) \
65 (*((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(x)))
66 #define PUT32(x, v) \
67 (*((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(x)) = (v))
68
69 static void dbau1550_init(void);
70 static int dbau1550_pci_intr_map(const struct pci_attach_args *,
71 pci_intr_handle_t *);
72 static void dbau1550_poweroff(void);
73 static void dbau1550_reboot(void);
74 static bus_addr_t dbau1550_slot_offset(int);
75 static int dbau1550_slot_irq(int, int);
76 static void dbau1550_slot_enable(int);
77 static void dbau1550_slot_disable(int);
78 static int dbau1550_slot_status(int);
79 static const char *dbau1550_slot_name(int);
80 static const struct auspi_machdep *dbau1550_spi(bus_addr_t);
81
82 static const struct obiodev dbau1550_devices[] = {
83 { NULL },
84 };
85
86 static struct aupcmcia_machdep dbau1550_pcmcia = {
87 2, /* nslots */
88 dbau1550_slot_offset,
89 dbau1550_slot_irq,
90 dbau1550_slot_enable,
91 dbau1550_slot_disable,
92 dbau1550_slot_status,
93 dbau1550_slot_name,
94 };
95
96 static struct alchemy_board dbau1550_info = {
97 .ab_name = "AMD Alchemy DBAu1550",
98 .ab_devices = dbau1550_devices,
99 .ab_init = dbau1550_init,
100 .ab_pci_intr_map = dbau1550_pci_intr_map,
101 .ab_reboot = dbau1550_reboot,
102 .ab_poweroff = dbau1550_poweroff,
103 .ab_pcmcia = &dbau1550_pcmcia,
104 .ab_spi = dbau1550_spi,
105 };
106
107 const struct alchemy_board *
board_info(void)108 board_info(void)
109 {
110
111 return &dbau1550_info;
112 }
113
114 void
dbau1550_init(void)115 dbau1550_init(void)
116 {
117 uint16_t whoami;
118 uint32_t sysclk;
119 uint32_t pinfunc;
120
121 if (MIPS_PRID_COPTS(mips_options.mips_cpu_id) != MIPS_AU1550)
122 panic("dbau1550: CPU not Au1550");
123
124 /* check the whoami register for a match */
125 whoami = GET16(DBAU1550_WHOAMI);
126
127 if (DBAU1550_WHOAMI_BOARD(whoami) != DBAU1550_WHOAMI_DBAU1550_REV1)
128 panic("dbau1550: WHOAMI (%x) not DBAu1550!", whoami);
129
130 printf("DBAu1550 (cabernet), CPLDv%d, ",
131 DBAU1550_WHOAMI_CPLD(whoami));
132
133 if (DBAU1550_WHOAMI_DAUGHTER(whoami) != 0xf)
134 printf("daughtercard 0x%x\n",
135 DBAU1550_WHOAMI_DAUGHTER(whoami));
136 else
137 printf("no daughtercard\n");
138
139 /* leave console and clocks alone -- YAMON should have got it right! */
140
141 /*
142 * Initialize PSC clocks.
143 *
144 * PSC0 is SPI. Use 48MHz FREQ1.
145 * PSC1 is AC97.
146 * PSC2 is SMBus, and must be 48MHz. (Configured by YAMON)
147 * PSC3 is I2S.
148 *
149 * FREQ2 is 48MHz for USBH/USBD.
150 */
151 sysclk = GET32(SYS_CLKSRC);
152 sysclk &= ~(SCS_MP0(7) | SCS_DP0 | SCS_CP0);
153 sysclk |= SCS_MP0(3);
154 PUT32(SYS_CLKSRC, sysclk);
155
156 /*
157 * Configure pin function for PSC devices.
158 */
159 pinfunc = GET32(SYS_PINFUNC);
160 /* configure PSC0 SYNC1 */
161 pinfunc |= SPF_S0;
162 /* configure PSC2 for SMBus (YAMON default) */
163 pinfunc &= ~SPF_PSC2_MASK;
164 pinfunc |= SPF_PSC2_SMBUS;
165 /* configure PSC3 for I2S (YAMON default) */
166 pinfunc &= ~SPF_PSC3_MASK;
167 pinfunc |= SPF_PSC3_I2S;
168 PUT32(SYS_PINFUNC, pinfunc);
169 }
170
171 int
dbau1550_pci_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ihp)172 dbau1550_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
173 {
174 /*
175 * This platform has one onboard PCI IDE controller, and two
176 * PCI expansion slots.
177 */
178 static const int irqmap[3/*device*/][4/*pin*/] = {
179 { 5, -1, -1, -1 }, /* 11: IDE */
180 { 2, 5, 6, 1 }, /* 12: PCI Slot 2 */
181 { 1, 2, 5, 6 }, /* 13: PCI Slot 3 */
182 };
183 int pin, dev, irq;
184
185 /* if interrupt pin not used... */
186 if ((pin = pa->pa_intrpin) == 0)
187 return 1;
188
189 if (pin > 4) {
190 printf("pci: bad interrupt pin %d\n", pin);
191 return 1;
192 }
193
194 pci_decompose_tag(pa->pa_pc, pa->pa_intrtag, NULL, &dev, NULL);
195 if ((dev < 11) || (dev > 13)) {
196 printf("pci: bad device %d\n", dev);
197 return 1;
198 }
199
200 if ((irq = irqmap[dev - 11][pin - 1]) == -1) {
201 printf("pci: no IRQ routing for device %d pin %d\n", dev, pin);
202 return 1;
203 }
204
205 *ihp = irq;
206 return 0;
207 }
208
209 void
dbau1550_reboot(void)210 dbau1550_reboot(void)
211 {
212 PUT16(DBAU1550_SOFTWARE_RESET, 0);
213 wbflush();
214 delay(100000); /* 100 msec */
215 }
216
217 void
dbau1550_poweroff(void)218 dbau1550_poweroff(void)
219 {
220 printf("\n- poweroff -\n");
221 PUT16(DBAU1550_SOFTWARE_RESET,
222 DBAU1550_SOFTWARE_RESET_PWROFF | DBAU1550_SOFTWARE_RESET_RESET);
223 wbflush();
224 delay(100000); /* 100 msec */
225 }
226
227 int
dbau1550_slot_irq(int slot,int which)228 dbau1550_slot_irq(int slot, int which)
229 {
230 static const int irqmap[2/*slot*/][2/*which*/] = {
231 { 35, 32 }, /* Slot 0: Bottom */
232 { 37, 33 }, /* Slot 1: Top */
233 };
234
235 if ((slot >= 2) || (which >= 2))
236 return -1;
237
238 return (irqmap[slot][which]);
239 }
240
241 bus_addr_t
dbau1550_slot_offset(int slot)242 dbau1550_slot_offset(int slot)
243 {
244 switch (slot) {
245 case 0:
246 return (DBAU1550_PC0_ADDR);
247 case 1:
248 return (DBAU1550_PC1_ADDR);
249 }
250
251 return (bus_addr_t)-1;
252 }
253
254 void
dbau1550_slot_enable(int slot)255 dbau1550_slot_enable(int slot)
256 {
257 uint16_t status;
258 uint16_t vcc, vpp;
259 int shift;
260
261 status = GET16(DBAU1550_STATUS);
262 switch (slot) {
263 case 0:
264 status >>= DBAU1550_STATUS_PCMCIA0_VS_SHIFT;
265 shift = DBAU1550_PCMCIA_PC0_SHIFT;
266 break;
267 case 1:
268 status >>= DBAU1550_STATUS_PCMCIA1_VS_SHIFT;
269 shift = DBAU1550_PCMCIA_PC1_SHIFT;
270 break;
271 default:
272 return;
273 }
274
275 status &= DBAU1550_STATUS_PCMCIA_VS_MASK;
276 switch (status) {
277 case DBAU1550_STATUS_PCMCIA_VS_GND:
278 vcc = DBAU1550_PCMCIA_VCC_GND;
279 vpp = DBAU1550_PCMCIA_VPP_GND;
280 break;
281 case DBAU1550_STATUS_PCMCIA_VS_5V:
282 vcc = DBAU1550_PCMCIA_VCC_5V;
283 vpp = DBAU1550_PCMCIA_VPP_VCC;
284 break;
285 default: /* covers both 3.3v cases */
286 vcc = DBAU1550_PCMCIA_VCC_3V;
287 vpp = DBAU1550_PCMCIA_VPP_VCC;
288 break;
289 }
290
291 status = GET16(DBAU1550_PCMCIA);
292
293 /* this clears all bits for this slot */
294 status &= ~(DBAU1550_PCMCIA_MASK << shift);
295
296 status |= vcc << shift;
297 status |= vpp << shift;
298
299 PUT16(DBAU1550_PCMCIA, status);
300 wbflush();
301 tsleep(&status, PWAIT, "pcmcia_reset_0", mstohz(100));
302
303 status |= (DBAU1550_PCMCIA_DRV_EN << shift);
304 PUT16(DBAU1550_PCMCIA, status);
305 wbflush();
306 tsleep(&status, PWAIT, "pcmcia_reset_start", mstohz(300));
307
308 /* take it out of reset */
309 status |= (DBAU1550_PCMCIA_RST << shift);
310 PUT16(DBAU1550_PCMCIA, status);
311 wbflush();
312
313 /* spec says 20 msec, but experience shows even 200 is not enough */
314 tsleep(&status, PWAIT, "pcmcia_reset_finish", mstohz(1000));
315
316 /* NOTE: WE DO NOT SUPPORT DIFFERENT VCC/VPP LEVELS! */
317 /* This means that 12V cards are not supported! */
318 }
319
320 void
dbau1550_slot_disable(int slot)321 dbau1550_slot_disable(int slot)
322 {
323 uint16_t status;
324
325 status = GET16(DBAU1550_PCMCIA);
326 status &= ~(DBAU1550_PCMCIA_MASK);
327 PUT16(DBAU1550_PCMCIA, status);
328 wbflush();
329 }
330
331 int
dbau1550_slot_status(int slot)332 dbau1550_slot_status(int slot)
333 {
334 uint16_t status, mask;
335 status = GET16(DBAU1550_STATUS);
336 switch (slot) {
337 case 0:
338 mask = DBAU1550_STATUS_PCMCIA0_INSERTED;
339 break;
340 case 1:
341 mask = DBAU1550_STATUS_PCMCIA1_INSERTED;
342 break;
343
344 default:
345 return 0;
346 }
347
348 return ((mask & status) ? 0 : 1);
349 }
350
351 const char *
dbau1550_slot_name(int slot)352 dbau1550_slot_name(int slot)
353 {
354 switch (slot) {
355 case 0:
356 return "bottom slot";
357 case 1:
358 return "top slot";
359 default:
360 return "???";
361 }
362 }
363
364 #if NAUSPI > 0
365
366 static int
dbau1550_spi_select(void * arg,int slave)367 dbau1550_spi_select(void *arg, int slave)
368 {
369 uint16_t status;
370 if ((slave < 0) || (slave > 1))
371 return EINVAL;
372 status = GET16(DBAU1550_BOARD_SPECIFIC);
373
374 if (slave) {
375 status |= DBAU1550_SPI_DEV_SEL;
376 } else {
377 status &= ~DBAU1550_SPI_DEV_SEL;
378 }
379 PUT16(DBAU1550_BOARD_SPECIFIC, status);
380 return 0;
381 }
382
383 const struct auspi_machdep *
dbau1550_spi(bus_addr_t ba)384 dbau1550_spi(bus_addr_t ba)
385 {
386 static const struct auspi_machdep md = {
387 .am_nslaves = 2,
388 .am_cookie = NULL,
389 .am_select = dbau1550_spi_select,
390 };
391
392 /* DBAU1550 only has SPI on PSC0 */
393 if (ba != PSC0_BASE)
394 return NULL;
395
396 return &md;
397 }
398
399 #endif /* NAUSPI > 0 */
400