1 /* $NetBSD: sun5i_a13_ccu.c,v 1.6 2021/01/27 03:10:20 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30
31 __KERNEL_RCSID(1, "$NetBSD: sun5i_a13_ccu.c,v 1.6 2021/01/27 03:10:20 thorpej Exp $");
32
33 #include <sys/param.h>
34 #include <sys/bus.h>
35 #include <sys/device.h>
36 #include <sys/systm.h>
37
38 #include <dev/fdt/fdtvar.h>
39
40 #include <arm/sunxi/sunxi_ccu.h>
41 #include <arm/sunxi/sun5i_a13_ccu.h>
42
43 #define PLL1_CFG_REG 0x000
44 #define PLL2_CFG_REG 0x008
45 #define PLL6_CFG_REG 0x028
46 #define OSC24M_CFG_REG 0x050
47 #define CPU_AHB_APB0_CFG_REG 0x054
48 #define APB1_CLK_DIV_REG 0x058
49 #define AHB_GATING_REG0 0x060
50 #define AHB_GATING_REG1 0x064
51 #define APB0_GATING_REG 0x068
52 #define APB1_GATING_REG 0x06c
53 #define NAND_SCLK_CFG_REG 0x080
54 #define SD0_SCLK_CFG_REG 0x088
55 #define SD1_SCLK_CFG_REG 0x08c
56 #define SD2_SCLK_CFG_REG 0x090
57 #define USBPHY_CFG_REG 0x0cc
58 #define BE_CFG_REG 0x104
59 #define FE_CFG_REG 0x10c
60 #define CSI_CFG_REG 0x134
61 #define VE_CFG_REG 0x13c
62 #define AUDIO_CODEC_SCLK_CFG_REG 0x140
63 #define MALI_CLOCK_CFG_REG 0x154
64 #define IEP_SCLK_CFG_REG 0x160
65
66 static int sun5i_a13_ccu_match(device_t, cfdata_t, void *);
67 static void sun5i_a13_ccu_attach(device_t, device_t, void *);
68
69 static const struct device_compatible_entry compat_data[] = {
70 { .compat = "allwinner,sun5i-a13-ccu" },
71 { .compat = "nextthing,gr8-ccu" },
72 DEVICE_COMPAT_EOL
73 };
74
75 CFATTACH_DECL_NEW(sunxi_a13_ccu, sizeof(struct sunxi_ccu_softc),
76 sun5i_a13_ccu_match, sun5i_a13_ccu_attach, NULL, NULL);
77
78 static struct sunxi_ccu_reset sun5i_a13_ccu_resets[] = {
79 SUNXI_CCU_RESET(A13_RST_USB_PHY0, USBPHY_CFG_REG, 0),
80 SUNXI_CCU_RESET(A13_RST_USB_PHY1, USBPHY_CFG_REG, 1),
81
82 /* Missing: GPS */
83
84 SUNXI_CCU_RESET(A13_RST_DE_BE, BE_CFG_REG, 30),
85
86 SUNXI_CCU_RESET(A13_RST_DE_FE, FE_CFG_REG, 30),
87
88 /* Missing: TVE */
89
90 /* Missing: LCD */
91
92 SUNXI_CCU_RESET(A13_RST_CSI, CSI_CFG_REG, 30),
93
94 SUNXI_CCU_RESET(A13_RST_VE, VE_CFG_REG, 0),
95
96 SUNXI_CCU_RESET(A13_RST_GPU, MALI_CLOCK_CFG_REG, 30),
97
98 SUNXI_CCU_RESET(A13_RST_IEP, IEP_SCLK_CFG_REG, 30),
99 };
100
101 static const char *cpu_parents[] = { "losc", "osc24m", "pll_core", "pll_periph" };
102 static const char *axi_parents[] = { "cpu" };
103 static const char *ahb_parents[] = { "axi", "cpu", "pll_periph" };
104 static const char *apb0_parents[] = { "ahb" };
105 static const char *apb1_parents[] = { "osc24m", "pll_periph", "losc" };
106 static const char *mod_parents[] = { "osc24m", "pll_periph", "pll_ddr" };
107
108 static const struct sunxi_ccu_nkmp_tbl sun5i_a13_ac_dig_table[] = {
109 { 24576000, 86, 0, 21, 3 },
110 { 0 }
111 };
112
113 static struct sunxi_ccu_clk sun5i_a13_ccu_clks[] = {
114 SUNXI_CCU_GATE(A13_CLK_HOSC, "osc24m", "hosc",
115 OSC24M_CFG_REG, 0),
116
117 SUNXI_CCU_NKMP(A13_CLK_PLL_CORE, "pll_core", "osc24m",
118 PLL1_CFG_REG, /* reg */
119 __BITS(12,8), /* n */
120 __BITS(5,4), /* k */
121 __BITS(1,0), /* m */
122 __BITS(17,16), /* p */
123 __BIT(31), /* enable */
124 SUNXI_CCU_NKMP_FACTOR_P_POW2 | SUNXI_CCU_NKMP_FACTOR_N_EXACT),
125
126 SUNXI_CCU_NKMP_TABLE(A13_CLK_PLL_AUDIO_BASE, "pll_audio", "osc24m",
127 PLL2_CFG_REG, /* reg */
128 __BITS(14,8), /* n */
129 0, /* k */
130 __BITS(4,0), /* m */
131 __BITS(29,26), /* p */
132 __BIT(31), /* enable */
133 0, /* lock */
134 sun5i_a13_ac_dig_table, /* table */
135 0),
136
137 SUNXI_CCU_NKMP(A13_CLK_PERIPH, "pll_periph", "osc24m",
138 PLL6_CFG_REG, /* reg */
139 __BITS(12,8), /* n */
140 __BITS(5,4), /* k */
141 __BITS(1,0), /* m */
142 0, /* p */
143 __BIT(31), /* enable */
144 SUNXI_CCU_NKMP_DIVIDE_BY_TWO | SUNXI_CCU_NKMP_FACTOR_N_EXACT),
145
146 SUNXI_CCU_PREDIV_FIXED(A13_CLK_CPU, "cpu", cpu_parents,
147 CPU_AHB_APB0_CFG_REG, /* reg */
148 0, /* prediv */
149 __BIT(3), /* prediv_sel */
150 6, /* prediv_fixed */
151 0, /* div */
152 __BITS(17,16), /* sel */
153 0),
154
155 SUNXI_CCU_DIV(A13_CLK_AXI, "axi", axi_parents,
156 CPU_AHB_APB0_CFG_REG, /* reg */
157 __BITS(1,0), /* div */
158 0, /* sel */
159 0),
160
161 SUNXI_CCU_DIV(A13_CLK_AHB, "ahb", ahb_parents,
162 CPU_AHB_APB0_CFG_REG, /* reg */
163 0, /* div */
164 __BITS(5,4), /* sel */
165 SUNXI_CCU_DIV_POWER_OF_TWO),
166
167 SUNXI_CCU_DIV(A13_CLK_APB0, "apb0", apb0_parents,
168 CPU_AHB_APB0_CFG_REG, /* reg */
169 __BITS(9,8), /* div */
170 0, /* sel */
171 SUNXI_CCU_DIV_ZERO_IS_ONE | SUNXI_CCU_DIV_POWER_OF_TWO),
172
173 SUNXI_CCU_NM(A13_CLK_APB1, "apb1", apb1_parents,
174 APB1_CLK_DIV_REG, /* reg */
175 __BITS(17,16), /* n */
176 __BITS(4,0), /* m */
177 __BITS(25,24), /* sel */
178 0, /* enable */
179 SUNXI_CCU_NM_POWER_OF_TWO),
180
181 SUNXI_CCU_NM(A13_CLK_MMC0, "mmc0", mod_parents,
182 SD0_SCLK_CFG_REG, /* reg */
183 __BITS(17,16), /* n */
184 __BITS(3,0), /* m */
185 __BITS(25,24), /* sel */
186 __BIT(31), /* enable */
187 SUNXI_CCU_NM_POWER_OF_TWO),
188 SUNXI_CCU_NM(A13_CLK_MMC1, "mmc1", mod_parents,
189 SD1_SCLK_CFG_REG, /* reg */
190 __BITS(17,16), /* n */
191 __BITS(3,0), /* m */
192 __BITS(25,24), /* sel */
193 __BIT(31), /* enable */
194 SUNXI_CCU_NM_POWER_OF_TWO),
195 SUNXI_CCU_NM(A13_CLK_MMC2, "mmc2", mod_parents,
196 SD2_SCLK_CFG_REG, /* reg */
197 __BITS(17,16), /* n */
198 __BITS(3,0), /* m */
199 __BITS(25,24), /* sel */
200 __BIT(31), /* enable */
201 SUNXI_CCU_NM_POWER_OF_TWO),
202
203 SUNXI_CCU_NM(A13_CLK_NAND, "nand", mod_parents,
204 NAND_SCLK_CFG_REG, /* reg */
205 __BITS(17,16), /* n */
206 __BITS(3,0), /* m */
207 __BITS(25,24), /* sel */
208 __BIT(31), /* enable */
209 SUNXI_CCU_NM_POWER_OF_TWO),
210
211 /* AHB_GATING_REG0. Missing: SS, EMAC, TS, GPS */
212 SUNXI_CCU_GATE(A13_CLK_AHB_OTG, "ahb-otg", "ahb",
213 AHB_GATING_REG0, 0),
214 SUNXI_CCU_GATE(A13_CLK_AHB_EHCI, "ahb-ehci", "ahb",
215 AHB_GATING_REG0, 1),
216 SUNXI_CCU_GATE(A13_CLK_AHB_OHCI, "ahb-ohci", "ahb",
217 AHB_GATING_REG0, 2),
218 SUNXI_CCU_GATE(A13_CLK_AHB_DMA, "ahb-dma", "ahb",
219 AHB_GATING_REG0, 6),
220 SUNXI_CCU_GATE(A13_CLK_AHB_BIST, "ahb-bist", "ahb",
221 AHB_GATING_REG0, 7),
222 SUNXI_CCU_GATE(A13_CLK_AHB_MMC0, "ahb-mmc0", "ahb",
223 AHB_GATING_REG0, 8),
224 SUNXI_CCU_GATE(A13_CLK_AHB_MMC1, "ahb-mmc1", "ahb",
225 AHB_GATING_REG0, 9),
226 SUNXI_CCU_GATE(A13_CLK_AHB_MMC2, "ahb-mmc2", "ahb",
227 AHB_GATING_REG0, 10),
228 SUNXI_CCU_GATE(A13_CLK_AHB_NAND, "ahb-nand", "ahb",
229 AHB_GATING_REG0, 13),
230 SUNXI_CCU_GATE(A13_CLK_AHB_SDRAM, "ahb-sdram", "ahb",
231 AHB_GATING_REG0, 14),
232 SUNXI_CCU_GATE(A13_CLK_AHB_SPI0, "ahb-spi0", "ahb",
233 AHB_GATING_REG0, 20),
234 SUNXI_CCU_GATE(A13_CLK_AHB_SPI1, "ahb-spi1", "ahb",
235 AHB_GATING_REG0, 21),
236 SUNXI_CCU_GATE(A13_CLK_AHB_SPI2, "ahb-spi2", "ahb",
237 AHB_GATING_REG0, 22),
238 SUNXI_CCU_GATE(A13_CLK_AHB_HSTIMER, "ahb-hstimer", "ahb",
239 AHB_GATING_REG0, 28),
240
241 /* AHB_GATING_REG1. Missing: TVE, HDMI */
242 SUNXI_CCU_GATE(A13_CLK_AHB_VE, "ahb-ve", "ahb",
243 AHB_GATING_REG1, 0),
244 SUNXI_CCU_GATE(A13_CLK_AHB_LCD, "ahb-lcd", "ahb",
245 AHB_GATING_REG1, 4),
246 SUNXI_CCU_GATE(A13_CLK_AHB_CSI, "ahb-csi", "ahb",
247 AHB_GATING_REG1, 8),
248 SUNXI_CCU_GATE(A13_CLK_AHB_DE_BE, "ahb-de_be", "ahb",
249 AHB_GATING_REG1, 12),
250 SUNXI_CCU_GATE(A13_CLK_AHB_DE_FE, "ahb-de_fe", "ahb",
251 AHB_GATING_REG1, 14),
252 SUNXI_CCU_GATE(A13_CLK_AHB_IEP, "ahb-iep", "ahb",
253 AHB_GATING_REG1, 19),
254 SUNXI_CCU_GATE(A13_CLK_AHB_GPU, "ahb-gpu", "ahb",
255 AHB_GATING_REG1, 20),
256
257 /* APB0_GATING_REG. Missing: SPDIF, I2S, KEYPAD */
258 SUNXI_CCU_GATE(A13_CLK_APB0_CODEC, "apb0-codec", "apb0",
259 APB0_GATING_REG, 0),
260 SUNXI_CCU_GATE(A13_CLK_APB0_PIO, "apb0-pio", "apb0",
261 APB0_GATING_REG, 5),
262 SUNXI_CCU_GATE(A13_CLK_APB0_IR, "apb0-ir", "apb0",
263 APB0_GATING_REG, 6),
264
265 /* APB1_GATING_REG. Missing: UART0, UART2 */
266 SUNXI_CCU_GATE(A13_CLK_APB1_I2C0, "apb1-i2c0", "apb1",
267 APB1_GATING_REG, 0),
268 SUNXI_CCU_GATE(A13_CLK_APB1_I2C1, "apb1-i2c1", "apb1",
269 APB1_GATING_REG, 1),
270 SUNXI_CCU_GATE(A13_CLK_APB1_I2C2, "apb1-i2c2", "apb1",
271 APB1_GATING_REG, 2),
272 SUNXI_CCU_GATE(A13_CLK_APB1_UART1, "apb1-uart1", "apb1",
273 APB1_GATING_REG, 17),
274 SUNXI_CCU_GATE(A13_CLK_APB1_UART3, "apb1-uart3", "apb1",
275 APB1_GATING_REG, 19),
276
277 /* AUDIO_CODEC_SCLK_CFG_REG */
278 SUNXI_CCU_GATE(A13_CLK_CODEC, "codec", "pll_audio",
279 AUDIO_CODEC_SCLK_CFG_REG, 31),
280
281 /* USBPHY_CFG_REG */
282 SUNXI_CCU_GATE(A13_CLK_USB_OHCI, "usb-ohci", "osc24m",
283 USBPHY_CFG_REG, 6),
284 SUNXI_CCU_GATE(A13_CLK_USB_PHY0, "usb-phy0", "osc24m",
285 USBPHY_CFG_REG, 8),
286 SUNXI_CCU_GATE(A13_CLK_USB_PHY1, "usb-phy1", "osc24m",
287 USBPHY_CFG_REG, 9),
288 };
289
290 static int
sun5i_a13_ccu_match(device_t parent,cfdata_t cf,void * aux)291 sun5i_a13_ccu_match(device_t parent, cfdata_t cf, void *aux)
292 {
293 struct fdt_attach_args * const faa = aux;
294
295 return of_compatible_match(faa->faa_phandle, compat_data);
296 }
297
298 static void
sun5i_a13_ccu_attach(device_t parent,device_t self,void * aux)299 sun5i_a13_ccu_attach(device_t parent, device_t self, void *aux)
300 {
301 struct sunxi_ccu_softc * const sc = device_private(self);
302 struct fdt_attach_args * const faa = aux;
303
304 sc->sc_dev = self;
305 sc->sc_phandle = faa->faa_phandle;
306 sc->sc_bst = faa->faa_bst;
307
308 sc->sc_resets = sun5i_a13_ccu_resets;
309 sc->sc_nresets = __arraycount(sun5i_a13_ccu_resets);
310
311 sc->sc_clks = sun5i_a13_ccu_clks;
312 sc->sc_nclks = __arraycount(sun5i_a13_ccu_clks);
313
314 if (sunxi_ccu_attach(sc) != 0)
315 return;
316
317 aprint_naive("\n");
318 aprint_normal(": A13 CCU\n");
319
320 sunxi_ccu_print(sc);
321 }
322