1 /* $NetBSD: s3c2800_pci.c,v 1.34 2022/09/25 12:28:54 andvar Exp $ */
2
3 /*
4 * Copyright (c) 2002 Fujitsu Component Limited
5 * Copyright (c) 2002 Genetec Corporation
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of The Fujitsu Component Limited nor the name of
17 * Genetec corporation may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * derived from evbarm/ifpga/ifpga_pci.c
35 */
36
37 /*
38 * Copyright (c) 2001 ARM Ltd
39 * All rights reserved.
40 *
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
43 * are met:
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. The name of the company may not be used to endorse or promote
50 * products derived from this software without specific prior written
51 * permission.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
63 * SUCH DAMAGE.
64 *
65 * Copyright (c) 1997,1998 Mark Brinicombe.
66 * Copyright (c) 1997,1998 Causality Limited
67 * All rights reserved.
68 *
69 * Redistribution and use in source and binary forms, with or without
70 * modification, are permitted provided that the following conditions
71 * are met:
72 * 1. Redistributions of source code must retain the above copyright
73 * notice, this list of conditions and the following disclaimer.
74 * 2. Redistributions in binary form must reproduce the above copyright
75 * notice, this list of conditions and the following disclaimer in the
76 * documentation and/or other materials provided with the distribution.
77 * 3. All advertising materials mentioning features or use of this software
78 * must display the following acknowledgement:
79 * This product includes software developed by Mark Brinicombe
80 * for the NetBSD Project.
81 * 4. The name of the company nor the name of the author may be used to
82 * endorse or promote products derived from this software without specific
83 * prior written permission.
84 *
85 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
86 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
87 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
88 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
89 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
90 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
91 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
92 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
93 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
94 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
95 * SUCH DAMAGE.
96 */
97
98 /*
99 * PCI configuration support for Samsung s3c2800.
100 */
101
102 #include <sys/cdefs.h>
103 __KERNEL_RCSID(0, "$NetBSD: s3c2800_pci.c,v 1.34 2022/09/25 12:28:54 andvar Exp $");
104
105 #include "opt_pci.h"
106 #include "pci.h"
107
108 #include <sys/param.h>
109 #include <sys/systm.h>
110 #include <sys/kernel.h>
111 #include <sys/device.h>
112 #include <sys/kmem.h>
113
114 #include <uvm/uvm_extern.h>
115
116 #include <sys/bus.h>
117
118 #include <dev/pci/pcireg.h>
119 #include <dev/pci/pcivar.h>
120 #include <dev/pci/pciconf.h>
121
122 #include <arm/locore.h>
123
124 #include <arm/s3c2xx0/s3c2800reg.h>
125 #include <arm/s3c2xx0/s3c2800var.h>
126
127 /*
128 * pci tag encoding.
129 * also useful for configuration type 0 address
130 */
131 #define BUSNO_SHIFT 16
132 #define BUSNO_MASK (0xff<<BUSNO_SHIFT)
133 #define DEVNO_SHIFT 11
134 #define DEVNO_MASK (0x1f<<DEVNO_SHIFT)
135 #define tag_to_devno(tag) (((tag)&DEVNO_MASK)>>DEVNO_SHIFT)
136 #define FUNNO_SHIFT 8
137 #define FUNNO_MASK (0x07<<FUNNO_SHIFT)
138
139 #define BUS0_DEV_MIN 1
140 #define BUS0_DEV_MAX 21
141
142 void s3c2800_pci_attach_hook(device_t, device_t, struct pcibus_attach_args *);
143 int s3c2800_pci_bus_maxdevs(void *, int);
144 pcitag_t s3c2800_pci_make_tag(void *, int, int, int);
145 void s3c2800_pci_decompose_tag(void *, pcitag_t, int *, int *, int *);
146 pcireg_t s3c2800_pci_conf_read(void *, pcitag_t, int);
147 void s3c2800_pci_conf_write(void *, pcitag_t, int, pcireg_t);
148 void s3c2800_pci_conf_interrupt(void *, int, int, int, int, int *);
149 int s3c2800_pci_intr_map(const struct pci_attach_args *,
150 pci_intr_handle_t *);
151 const char *s3c2800_pci_intr_string(void *, pci_intr_handle_t, char *, size_t);
152 const struct evcnt *s3c2800_pci_intr_evcnt(void *, pci_intr_handle_t);
153 void *s3c2800_pci_intr_establish(void *, pci_intr_handle_t, int,
154 int (*) (void *), void *, const char *);
155 void s3c2800_pci_intr_disestablish(void *, void *);
156
157 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit)
158 #define PCI_CONF_UNLOCK(s) restore_interrupts((s))
159
160 struct sspci_irq_handler {
161 int (*func) (void *);
162 void *arg;
163 int level;
164 SLIST_ENTRY(sspci_irq_handler) link;
165 };
166
167 struct sspci_softc {
168 device_t sc_dev;
169
170 bus_space_tag_t sc_iot;
171 bus_space_handle_t sc_reg_ioh;
172 bus_space_handle_t sc_conf0_ioh; /* config type0 space */
173 bus_space_handle_t sc_conf1_ioh; /* config type1 space */
174
175 uint32_t sc_pciinten; /* copy of PCIINTEN register */
176
177 /* list of interrupt handlers. SLIST is not good for removing
178 * element from it, but intr_disestablish is rarely called */
179 SLIST_HEAD(, sspci_irq_handler) sc_irq_handlers;
180
181 void *sc_softinterrupt;
182 };
183
184 static int sspci_match(device_t, cfdata_t, void *aux);
185 static void sspci_attach(device_t, device_t, void *);
186
187 static int sspci_bs_map(void *, bus_addr_t, bus_size_t, int,
188 bus_space_handle_t *);
189 static int sspci_init_controller(struct sspci_softc *);
190 static int sspci_intr(void *);
191 static void sspci_softintr(void *);
192
193 /* attach structures */
194 CFATTACH_DECL_NEW(sspci, sizeof(struct sspci_softc), sspci_match, sspci_attach,
195 NULL, NULL);
196
197
198 struct arm32_pci_chipset sspci_chipset = {
199 .pc_attach_hook = s3c2800_pci_attach_hook,
200 .pc_bus_maxdevs = s3c2800_pci_bus_maxdevs,
201 .pc_make_tag = s3c2800_pci_make_tag,
202 .pc_decompose_tag = s3c2800_pci_decompose_tag,
203 .pc_conf_read = s3c2800_pci_conf_read,
204 .pc_conf_write = s3c2800_pci_conf_write,
205 .pc_intr_map = s3c2800_pci_intr_map,
206 .pc_intr_string = s3c2800_pci_intr_string,
207 .pc_intr_evcnt = s3c2800_pci_intr_evcnt,
208 .pc_intr_establish = s3c2800_pci_intr_establish,
209 .pc_intr_disestablish = s3c2800_pci_intr_disestablish,
210 .pc_conf_interrupt = s3c2800_pci_conf_interrupt,
211 };
212
213
214 /*
215 * bus space tag for PCI IO/Memory access space.
216 * filled in by sspci_attach()
217 */
218 struct bus_space sspci_io_tag, sspci_mem_tag;
219
220 static int
sspci_match(device_t parent,cfdata_t match,void * aux)221 sspci_match(device_t parent, cfdata_t match, void *aux)
222 {
223 return 1;
224 }
225
226 static void
sspci_attach(device_t parent,device_t self,void * aux)227 sspci_attach(device_t parent, device_t self, void *aux)
228 {
229 struct sspci_softc *sc = device_private(self);
230 struct s3c2xx0_attach_args *aa = aux;
231 bus_space_tag_t iot;
232 bus_dma_tag_t pci_dma_tag;
233 const char *error_on; /* for panic message */
234 #if defined(PCI_NETBSD_CONFIGURE)
235 struct pciconf_resources *pcires;
236 struct pcibus_attach_args pci_pba;
237 #endif
238
239 #define FAIL(which) do { \
240 error_on=(which); goto abort; }while(/*CONSTCOND*/0)
241
242 sc->sc_dev = self;
243 iot = sc->sc_iot = aa->sa_iot;
244 if (bus_space_map(iot, S3C2800_PCICTL_BASE,
245 S3C2800_PCICTL_SIZE, 0, &sc->sc_reg_ioh))
246 FAIL("control regs");
247
248 if (bus_space_map(iot, S3C2800_PCI_CONF0_BASE,
249 S3C2800_PCI_CONF0_SIZE, 0, &sc->sc_conf0_ioh))
250 FAIL("config type 0 area");
251
252 #if 0
253 if (bus_space_map(iot, S3C2800_PCI_CONF1_BASE,
254 S3C2800_PCI_CONF1_SIZE, 0, &sc->sc_conf1_ioh))
255 FAIL("config type 1 area");
256 #endif
257 printf("\n");
258
259 SLIST_INIT(&sc->sc_irq_handlers);
260 if (!s3c2800_intr_establish(S3C2800_INT_PCI, IPL_AUDIO, IST_LEVEL,
261 sspci_intr, sc))
262 FAIL("intr_establish");
263
264 sc->sc_softinterrupt = softint_establish(SOFTINT_SERIAL,
265 sspci_softintr, sc);
266 if (sc->sc_softinterrupt == NULL)
267 FAIL("softint_establish");
268
269 #if defined(PCI_NETBSD_CONFIGURE)
270 if (sspci_init_controller(sc)) {
271 printf("%s: failed to initialize controller\n", device_xname(self));
272 return;
273 }
274 #endif
275
276 sc->sc_pciinten =
277 PCIINT_INA | PCIINT_SER | PCIINT_TPE | PCIINT_MPE |
278 PCIINT_MFE | PCIINT_PRA | PCIINT_PRD;
279
280 bus_space_write_4(iot, sc->sc_reg_ioh, PCICTL_PCIINTEN,
281 sc->sc_pciinten);
282
283 {
284 pcireg_t id_reg, class_reg;
285 char buf[1000];
286
287 id_reg = bus_space_read_4(iot, sc->sc_reg_ioh,
288 PCI_ID_REG);
289 class_reg = bus_space_read_4(iot,
290 sc->sc_reg_ioh, PCI_CLASS_REG);
291
292 pci_devinfo(id_reg, class_reg, 1, buf, sizeof(buf));
293 printf("%s: %s\n", device_xname(self), buf);
294 }
295
296 #if defined(PCI_NETBSD_CONFIGURE)
297 pcires = pciconf_resource_init();
298
299 pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
300 0x100, S3C2800_PCI_IOSPACE_SIZE - 0x100);
301 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
302 0, S3C2800_PCI_MEMSPACE_SIZE);
303
304 sspci_chipset.pc_conf_v = (void *) sc;
305 sspci_chipset.pc_intr_v = (void *) sc;
306
307 pci_configure_bus(&sspci_chipset, pcires, 0, arm_dcache_align);
308
309 pciconf_resource_fini(pcires);
310 #endif /* PCI_NETBSD_CONFIGURE */
311
312 /* initialize bus space tag */
313 sspci_io_tag = *iot;
314 sspci_io_tag.bs_cookie = (void *) S3C2800_PCI_IOSPACE_BASE;
315 sspci_io_tag.bs_map = sspci_bs_map;
316 sspci_mem_tag = *iot;
317 sspci_mem_tag.bs_cookie = (void *) S3C2800_PCI_MEMSPACE_BASE;
318 sspci_mem_tag.bs_map = sspci_bs_map;
319
320
321 /* Platform provides PCI DMA tag */
322 pci_dma_tag = s3c2800_pci_dma_init();
323
324 pci_pba.pba_pc = &sspci_chipset;
325 pci_pba.pba_iot = &sspci_io_tag;
326 pci_pba.pba_memt = &sspci_mem_tag;
327 pci_pba.pba_dmat = pci_dma_tag;
328 pci_pba.pba_dmat64 = NULL;
329 pci_pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
330 pci_pba.pba_bus = 0;
331 pci_pba.pba_bridgetag = NULL;
332
333 config_found(self, &pci_pba, pcibusprint, CFARGS_NONE);
334
335 return;
336
337 #undef FAIL
338 abort:
339 panic("%s: map failed (%s)",
340 device_xname(self), error_on);
341 }
342
343
344 static int
sspci_bs_map(void * t,bus_addr_t bpa,bus_size_t size,int flag,bus_space_handle_t * bshp)345 sspci_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flag,
346 bus_space_handle_t * bshp)
347 {
348 bus_addr_t startpa, endpa;
349 vaddr_t va;
350
351 #ifdef PCI_DEBUG
352 printf("sspci_bs_map: t=%p, addr=%lx, size=%lx, flag=%d\n",
353 t, bpa, size, flag);
354 #endif
355
356 /* Round the allocation to page boundaries */
357 startpa = trunc_page(bpa);
358 endpa = round_page(bpa + size);
359
360 /* Get some VM. */
361 va = uvm_km_alloc(kernel_map, endpa - startpa, 0,
362 UVM_KMF_VAONLY | UVM_KMF_NOWAIT);
363 if (va == 0)
364 return ENOMEM;
365
366 /* Store the bus space handle */
367 *bshp = va + (bpa & PGOFSET);
368
369 /* Now map the pages */
370 /* The cookie is the physical base address for PCI I/O or memory area */
371 while (startpa < endpa) {
372 /* XXX pmap_kenter_pa maps pages cacheable -- not what we
373 * want. */
374 pmap_enter(pmap_kernel(), va, (bus_addr_t) t + startpa,
375 VM_PROT_READ | VM_PROT_WRITE, 0);
376 va += PAGE_SIZE;
377 startpa += PAGE_SIZE;
378 }
379 pmap_update(pmap_kernel());
380
381 return 0;
382 }
383
384
385
386 void
s3c2800_pci_conf_interrupt(void * v,int bus,int dev,int ipin,int swiz,int * iline)387 s3c2800_pci_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline)
388 {
389 #ifdef PCI_DEBUG
390 printf("pci_conf_interrupt(v(%p), bus(%d), dev(%d), ipin(%d), swiz(%d), *iline(%p)\n", v, bus, dev, ipin, swiz, iline);
391 #endif
392 if (bus == 0) {
393 *iline = dev;
394 } else {
395 panic("pci_conf_interrupt: bus=%d: not yet implemented", bus);
396 }
397 }
398
399 void
s3c2800_pci_attach_hook(device_t parent,device_t self,struct pcibus_attach_args * pba)400 s3c2800_pci_attach_hook(device_t parent, device_t self,
401 struct pcibus_attach_args * pba)
402 {
403
404 /* Nothing to do. */
405 #ifdef PCI_DEBUG
406 printf("s3c2800_pci_attach_hook()\n");
407 #endif
408 }
409
410 int
s3c2800_pci_bus_maxdevs(void * v,int busno)411 s3c2800_pci_bus_maxdevs(void *v, int busno)
412 {
413
414 #ifdef PCI_DEBUG
415 printf("s3c2800_pci_bus_maxdevs(v=%p, busno=%d)\n", v, busno);
416 #endif
417 return (32);
418 }
419 pcitag_t
s3c2800_pci_make_tag(void * v,int bus,int device,int function)420 s3c2800_pci_make_tag(void *v, int bus, int device, int function)
421 {
422
423 return ((bus << BUSNO_SHIFT) | (device << DEVNO_SHIFT) |
424 (function << FUNNO_SHIFT));
425 }
426
427 void
s3c2800_pci_decompose_tag(void * v,pcitag_t tag,int * bp,int * dp,int * fp)428 s3c2800_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
429 {
430 if (bp != NULL)
431 *bp = (tag >> BUSNO_SHIFT) & 0xff;
432 if (dp != NULL)
433 *dp = (tag >> DEVNO_SHIFT) & 0x1f;
434 if (fp != NULL)
435 *fp = (tag >> FUNNO_SHIFT) & 0x7;
436 }
437
438 static vaddr_t
make_pci_conf_va(struct sspci_softc * sc,pcitag_t tag,int offset)439 make_pci_conf_va(struct sspci_softc * sc, pcitag_t tag, int offset)
440 {
441
442 if ((unsigned int)offset >= PCI_CONF_SIZE)
443 return (vaddr_t) -1;
444
445 if ((tag & BUSNO_MASK) == 0) {
446 /* configuration type 0 */
447 int devno = tag_to_devno(tag);
448
449 if (devno < BUS0_DEV_MIN || BUS0_DEV_MAX < devno)
450 return 0;
451
452 return (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_conf0_ioh) +
453 (tag & (DEVNO_MASK | FUNNO_MASK)) + offset;
454 } else {
455 /* XXX */
456 return (vaddr_t) - 1; /* cause fault */
457 }
458 }
459
460
461 pcireg_t
s3c2800_pci_conf_read(void * v,pcitag_t tag,int offset)462 s3c2800_pci_conf_read(void *v, pcitag_t tag, int offset)
463 {
464 struct sspci_softc *sc = v;
465 vaddr_t va = make_pci_conf_va(sc, tag, offset);
466 int s;
467 pcireg_t rv;
468
469 #ifdef PCI_DEBUG
470 printf("s3c2800_pci_conf_read: base=%lx tag=%lx offset=%x\n",
471 sc->sc_conf0_ioh, tag, offset);
472 #endif
473 if (va == 0)
474 return -1;
475
476 PCI_CONF_LOCK(s);
477
478 if (badaddr_read((void *) va, sizeof(rv), &rv)) {
479 #if PCI_DEBUG
480 printf("conf_read: %lx bad address\n", va);
481 #endif
482 rv = (pcireg_t) - 1;
483 }
484 PCI_CONF_UNLOCK(s);
485
486 return rv;
487 }
488
489 void
s3c2800_pci_conf_write(void * v,pcitag_t tag,int offset,pcireg_t val)490 s3c2800_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
491 {
492 struct sspci_softc *sc = v;
493 vaddr_t va = make_pci_conf_va(sc, tag, offset);
494 u_int s;
495
496 #ifdef PCI_DEBUG
497 printf("s3c2800_pci_conf_write: tag=%lx offset=%x -> va=%lx\n", tag, offset, va);
498 #endif
499
500 PCI_CONF_LOCK(s);
501
502 *(pcireg_t *) va = val;
503
504 PCI_CONF_UNLOCK(s);
505 }
506
507 void *
s3c2800_pci_intr_establish(void * pcv,pci_intr_handle_t ih,int level,int (* func)(void *),void * arg,const char * xname)508 s3c2800_pci_intr_establish(void *pcv, pci_intr_handle_t ih, int level,
509 int (*func) (void *), void *arg, const char *xname)
510 {
511 struct sspci_softc *sc = pcv;
512 struct sspci_irq_handler *handler;
513 int s;
514
515 #ifdef PCI_DEBUG
516 printf("s3c2800_pci_intr_establish(pcv=%p, ih=0x%lx, level=%d, "
517 "func=%p, arg=%p, xname=%s)\n", pcv, ih, level, func, arg, xname);
518 #endif
519
520 handler = kmem_alloc(sizeof *handler, KM_SLEEP);
521 handler->func = func;
522 handler->arg = arg;
523 handler->level = level;
524
525 s = splhigh();
526 SLIST_INSERT_HEAD(&sc->sc_irq_handlers, handler, link);
527 splx(s);
528
529 return (handler);
530 }
531
532 void
s3c2800_pci_intr_disestablish(void * pcv,void * cookie)533 s3c2800_pci_intr_disestablish(void *pcv, void *cookie)
534 {
535 struct sspci_softc *sc = pcv;
536 struct sspci_irq_handler *ih = cookie;
537 int s;
538
539 #ifdef PCI_DEBUG
540 printf("s3c2800_pci_intr_disestablish(pcv=%p, cookie=%p)\n",
541 pcv, cookie);
542 #endif
543
544 s = splhigh();
545 SLIST_REMOVE(&sc->sc_irq_handlers, ih, sspci_irq_handler, link);
546 splx(s);
547 }
548
549 int
s3c2800_pci_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ihp)550 s3c2800_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
551 {
552 #ifdef PCI_DEBUG
553 int pin = pa->pa_intrpin;
554 void *pcv = pa->pa_pc;
555 pcitag_t intrtag = pa->pa_intrtag;
556 int bus, device, function;
557
558 s3c2800_pci_decompose_tag(pcv, intrtag, &bus, &device, &function);
559 printf("s3c2800_pci_intr_map: pcv=%p, tag=%08lx pin=%d dev=%d\n",
560 pcv, intrtag, pin, device);
561 #endif
562
563
564 /* S3C2800 has only one interrupt line for PCI */
565 *ihp = 0;
566 return 0;
567 }
568
569 const char *
s3c2800_pci_intr_string(void * pcv,pci_intr_handle_t ih,char * buf,size_t len)570 s3c2800_pci_intr_string(void *pcv, pci_intr_handle_t ih, char *buf, size_t len)
571 {
572 /* We have only one interrupt source from PCI */
573 strlcpy(buf, "pciint", len);
574 return buf;
575 }
576
577 const struct evcnt *
s3c2800_pci_intr_evcnt(void * pcv,pci_intr_handle_t ih)578 s3c2800_pci_intr_evcnt(void *pcv, pci_intr_handle_t ih)
579 {
580
581 /* XXX for now, no evcnt parent reported */
582 return NULL;
583 }
584 /*
585 * Initialize PCI controller
586 */
587 int
sspci_init_controller(struct sspci_softc * sc)588 sspci_init_controller(struct sspci_softc * sc)
589 {
590 bus_space_tag_t iot = sc->sc_iot;
591 bus_space_handle_t ioh = sc->sc_reg_ioh;
592
593 /* disable PCI command */
594 bus_space_write_4(iot, ioh, PCI_COMMAND_STATUS_REG,
595 0xffff0000);
596
597 /* latency=0x10, cacheline=8 */
598 bus_space_write_4(iot, ioh, PCI_BHLC_REG,
599 PCI_BHLC_CODE(0, 0, 0, 0x10, 8));
600
601 bus_space_write_4(iot, ioh, PCI_INTERRUPT_REG,
602 PCI_INTERRUPT_CODE(0, 0, 0, 0));
603
604
605
606 #if 1
607 bus_space_write_4(iot, ioh, PCI_MAPREG_START,
608 PCI_MAPREG_MEM_TYPE_32BIT | 0x80000000);
609 /* Cover all DBANKs with BAR0 */
610 bus_space_write_4(iot, ioh, PCICTL_PCIBAM0, 0xf8000000);
611 bus_space_write_4(iot, ioh, PCICTL_PCIBATPA0, S3C2800_DBANK0_START);
612 #else
613 bus_space_write_4(iot, ioh, PCI_MAPREG_START,
614 PCI_MAPREG_MEM_TYPE_32BIT | 0xf0000000);
615 bus_space_write_4(iot, ioh, PCI_MAPREG_START + 4,
616 PCI_MAPREG_MEM_TYPE_32BIT | 0x80000000);
617
618 bus_space_write_4(iot, ioh, PCICTL_PCIBAM0, 0xffff0000);
619 bus_space_write_4(iot, ioh, PCICTL_PCIBATPA0, 0xffff0000);
620 bus_space_write_4(iot, ioh, PCICTL_PCIBAM1, 0xf1000000);
621 bus_space_write_4(iot, ioh, PCICTL_PCIBATPA1, S3C2800_DBANK0_START);
622 #endif
623
624 bus_space_write_4(iot, ioh, PCI_COMMAND_STATUS_REG,
625 PCI_STATUS_PARITY_DETECT |
626 PCI_STATUS_SPECIAL_ERROR |
627 PCI_STATUS_MASTER_ABORT |
628 PCI_STATUS_MASTER_TARGET_ABORT |
629 PCI_STATUS_TARGET_TARGET_ABORT |
630 PCI_STATUS_DEVSEL_MEDIUM |
631 PCI_STATUS_PARITY_ERROR |
632 PCI_STATUS_BACKTOBACK_SUPPORT |
633 PCI_STATUS_CAPLIST_SUPPORT |
634 PCI_COMMAND_MASTER_ENABLE |
635 PCI_COMMAND_MEM_ENABLE |
636 PCI_COMMAND_IO_ENABLE);
637
638 bus_space_write_4(iot, ioh, PCICTL_PCICON,
639 PCICON_ARB | PCICON_HST);
640
641 bus_space_write_4(iot, ioh, PCICTL_PCISET, 0);
642 /* clear all interrupts */
643 bus_space_write_4(iot, ioh, PCICTL_PCIINTST, 0xffffffff);
644 bus_space_write_4(iot, ioh, PCICTL_PCIINTEN, 0);
645
646 bus_space_write_4(iot, ioh, PCICTL_PCICON,
647 PCICON_RDY | PCICON_CFD | PCICON_ATS |
648 PCICON_ARB | PCICON_HST);
649
650
651 #ifdef PCI_DEBUG
652 {
653 pcireg_t reg;
654 int i;
655
656 for (i = 0; i <= 0x40; i += sizeof(pcireg_t)) {
657 reg = bus_space_read_4(iot, ioh, i);
658 printf("%03x: %08x\n", i, reg);
659 }
660 for (i = 0x100; i <= 0x154; i += sizeof(pcireg_t)) {
661 reg = bus_space_read_4(iot, ioh, i);
662 printf("%03x: %08x\n", i, reg);
663 }
664 }
665 #endif
666 return 0;
667 }
668
669
670 static const char *pci_abnormal_error_name[] = {
671 "PCI reset deasserted",
672 "PCI reset asserted",
673 "PCI master detected fatal error",
674 "PCI master detected parity error",
675 "PCI target detected parity error",
676 "PCI SERR# asserted",
677 };
678
679 static int
sspci_intr(void * arg)680 sspci_intr(void *arg)
681 {
682 struct sspci_softc *sc = arg;
683 int s;
684 bus_space_tag_t iot = sc->sc_iot;
685 bus_space_handle_t ioh = sc->sc_reg_ioh;
686 uint32_t interrupts, errors;
687
688 interrupts = bus_space_read_4(iot, ioh, PCICTL_PCIINTST);
689
690 if (interrupts & PCIINT_INA) {
691 s = splhigh();
692 softint_schedule(sc->sc_softinterrupt);
693
694 /* mask INTA interrupt until softinterrupt is handled */
695 sc->sc_pciinten &= ~PCIINT_INA;
696 bus_space_write_4(iot, ioh, PCICTL_PCIINTEN,
697 sc->sc_pciinten);
698
699 /* acknowledge INTA interrupt */
700 bus_space_write_4(iot, ioh, PCICTL_PCIINTST, PCIINT_INA);
701
702 splx(s);
703
704 interrupts &= ~PCIINT_INA;
705
706 }
707 errors = interrupts & (PCIINT_SER | PCIINT_TPE | PCIINT_MPE |
708 PCIINT_MFE | PCIINT_PRA | PCIINT_PRD);
709 if (errors) {
710 int i;
711
712 for (i = 0; errors; ++i) {
713 if ((errors & (1 << i)) == 0)
714 continue;
715
716 printf("%s: %s\n", device_xname(sc->sc_dev),
717 pci_abnormal_error_name[i > 4 ? 5 : i]);
718
719 errors &= ~(1 << i);
720 }
721 /* acknowledge interrupts */
722 bus_space_write_4(iot, ioh, PCICTL_PCIINTST, interrupts);
723 }
724 return 0;
725 }
726
727 static void
sspci_softintr(void * arg)728 sspci_softintr(void *arg)
729 {
730 struct sspci_softc *sc = arg;
731 struct sspci_irq_handler *ih;
732 int s;
733
734
735 SLIST_FOREACH(ih, &(sc->sc_irq_handlers), link) {
736 s = _splraise(ih->level);
737 ih->func(ih->arg);
738 splx(s);
739 }
740
741 /* unmask INTA interrupt */
742 s = splhigh();
743 sc->sc_pciinten |= PCIINT_INA;
744 bus_space_write_4(sc->sc_iot, sc->sc_reg_ioh, PCICTL_PCIINTEN,
745 sc->sc_pciinten);
746 splx(s);
747 }
748