1 /* $NetBSD: rk_gpio.c,v 1.7 2023/10/17 17:31:12 tnn Exp $ */
2
3 /*-
4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: rk_gpio.c,v 1.7 2023/10/17 17:31:12 tnn Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/device.h>
35 #include <sys/intr.h>
36 #include <sys/systm.h>
37 #include <sys/mutex.h>
38 #include <sys/kmem.h>
39 #include <sys/gpio.h>
40 #include <sys/bitops.h>
41 #include <sys/lwp.h>
42
43 #include <dev/fdt/fdtvar.h>
44 #include <dev/gpio/gpiovar.h>
45
46 #define GPIO_SWPORTA_DR_REG 0x0000
47 #define GPIO_SWPORTA_DDR_REG 0x0004
48 #define GPIO_INTEN_REG 0x0030
49 #define GPIO_INTMASK_REG 0x0034
50 #define GPIO_INTTYPE_LEVEL_REG 0x0038
51 #define GPIO_INT_POLARITY_REG 0x003c
52 #define GPIO_INT_STATUS_REG 0x0040
53 #define GPIO_INT_RAWSTATUS_REG 0x0044
54 #define GPIO_DEBOUNCE_REG 0x0048
55 #define GPIO_PORTA_EOI_REG 0x004c
56 #define GPIO_EXT_PORTA_REG 0x0050
57 #define GPIO_LS_SYNC_REG 0x0060
58 #define GPIO_VER_ID_REG 0x0078
59 #define GPIO_VER_ID_GPIOV2 0x0101157c
60
61 /*
62 * In "version 2" GPIO controllers, half of each register is used by the
63 * write_enable mask, so the 32 pins are spread over two registers.
64 *
65 * pins 0 - 15 go into the GPIO_SWPORT_*_L register
66 * pins 16 - 31 go into the GPIO_SWPORT_*_H register
67 */
68 #define GPIOV2_SWPORT_DR_BASE 0x0000
69 #define GPIOV2_SWPORT_DR_REG(pin) \
70 (GPIOV2_SWPORT_DR_BASE + GPIOV2_REG_OFFSET(pin))
71 #define GPIOV2_SWPORT_DDR_BASE 0x0008
72 #define GPIOV2_SWPORT_DDR_REG(pin) \
73 (GPIOV2_SWPORT_DDR_BASE + GPIOV2_REG_OFFSET(pin))
74 #define GPIOV2_EXT_PORT_REG 0x0070
75 #define GPIOV2_REG_OFFSET(pin) (((pin) >> 4) << 2)
76 #define GPIOV2_DATA_MASK(pin) (__BIT((pin) & 0xF))
77 #define GPIOV2_WRITE_MASK(pin) (__BIT(((pin) & 0xF) | 0x10))
78
79 static const struct device_compatible_entry compat_data[] = {
80 { .compat = "rockchip,gpio-bank" },
81 DEVICE_COMPAT_EOL
82 };
83
84 struct rk_gpio_softc {
85 device_t sc_dev;
86 bus_space_tag_t sc_bst;
87 bus_space_handle_t sc_bsh;
88 kmutex_t sc_lock;
89
90 struct gpio_chipset_tag sc_gp;
91 gpio_pin_t sc_pins[32];
92 device_t sc_gpiodev;
93 };
94
95 struct rk_gpio_pin {
96 struct rk_gpio_softc *pin_sc;
97 u_int pin_nr;
98 int pin_flags;
99 bool pin_actlo;
100 };
101
102 #define RD4(sc, reg) \
103 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
104 #define WR4(sc, reg, val) \
105 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
106
107 static int rk_gpio_match(device_t, cfdata_t, void *);
108 static void rk_gpio_attach(device_t, device_t, void *);
109
110 CFATTACH_DECL_NEW(rk_gpio, sizeof(struct rk_gpio_softc),
111 rk_gpio_match, rk_gpio_attach, NULL, NULL);
112
113 static void *
rk_gpio_acquire(device_t dev,const void * data,size_t len,int flags)114 rk_gpio_acquire(device_t dev, const void *data, size_t len, int flags)
115 {
116 struct rk_gpio_softc * const sc = device_private(dev);
117 struct rk_gpio_pin *gpin;
118 const u_int *gpio = data;
119
120 if (len != 12)
121 return NULL;
122
123 const uint8_t pin = be32toh(gpio[1]) & 0xff;
124 const bool actlo = be32toh(gpio[2]) & 1;
125
126 if (pin >= __arraycount(sc->sc_pins))
127 return NULL;
128
129 sc->sc_gp.gp_pin_ctl(sc, pin, flags);
130
131 gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP);
132 gpin->pin_sc = sc;
133 gpin->pin_nr = pin;
134 gpin->pin_flags = flags;
135 gpin->pin_actlo = actlo;
136
137 return gpin;
138 }
139
140 static void
rk_gpio_release(device_t dev,void * priv)141 rk_gpio_release(device_t dev, void *priv)
142 {
143 struct rk_gpio_softc * const sc = device_private(dev);
144 struct rk_gpio_pin *pin = priv;
145
146 KASSERT(sc == pin->pin_sc);
147
148 sc->sc_gp.gp_pin_ctl(sc, pin->pin_nr, GPIO_PIN_INPUT);
149
150 kmem_free(pin, sizeof(*pin));
151 }
152
153 static int
rk_gpio_read(device_t dev,void * priv,bool raw)154 rk_gpio_read(device_t dev, void *priv, bool raw)
155 {
156 struct rk_gpio_softc * const sc = device_private(dev);
157 struct rk_gpio_pin *pin = priv;
158 int val;
159
160 KASSERT(sc == pin->pin_sc);
161
162 val = sc->sc_gp.gp_pin_read(sc, pin->pin_nr);
163 if (!raw && pin->pin_actlo)
164 val = !val;
165
166 return val;
167 }
168
169 static void
rk_gpio_write(device_t dev,void * priv,int val,bool raw)170 rk_gpio_write(device_t dev, void *priv, int val, bool raw)
171 {
172 struct rk_gpio_softc * const sc = device_private(dev);
173 struct rk_gpio_pin *pin = priv;
174
175 KASSERT(sc == pin->pin_sc);
176
177 if (!raw && pin->pin_actlo)
178 val = !val;
179
180 sc->sc_gp.gp_pin_write(sc, pin->pin_nr, val);
181 }
182
183 static struct fdtbus_gpio_controller_func rk_gpio_funcs = {
184 .acquire = rk_gpio_acquire,
185 .release = rk_gpio_release,
186 .read = rk_gpio_read,
187 .write = rk_gpio_write,
188 };
189
190 static int
rk_gpio_pin_read(void * priv,int pin)191 rk_gpio_pin_read(void *priv, int pin)
192 {
193 struct rk_gpio_softc * const sc = priv;
194 uint32_t data;
195 int val;
196
197 KASSERT(pin < __arraycount(sc->sc_pins));
198
199 const uint32_t data_mask = __BIT(pin);
200
201 /* No lock required for reads */
202 data = RD4(sc, GPIO_EXT_PORTA_REG);
203 val = __SHIFTOUT(data, data_mask);
204
205 return val;
206 }
207
208 static void
rk_gpio_pin_write(void * priv,int pin,int val)209 rk_gpio_pin_write(void *priv, int pin, int val)
210 {
211 struct rk_gpio_softc * const sc = priv;
212 uint32_t data;
213
214 KASSERT(pin < __arraycount(sc->sc_pins));
215
216 const uint32_t data_mask = __BIT(pin);
217
218 mutex_enter(&sc->sc_lock);
219 data = RD4(sc, GPIO_SWPORTA_DR_REG);
220 if (val)
221 data |= data_mask;
222 else
223 data &= ~data_mask;
224 WR4(sc, GPIO_SWPORTA_DR_REG, data);
225 mutex_exit(&sc->sc_lock);
226 }
227
228 static void
rk_gpio_pin_ctl(void * priv,int pin,int flags)229 rk_gpio_pin_ctl(void *priv, int pin, int flags)
230 {
231 struct rk_gpio_softc * const sc = priv;
232 uint32_t ddr;
233
234 KASSERT(pin < __arraycount(sc->sc_pins));
235
236 mutex_enter(&sc->sc_lock);
237 ddr = RD4(sc, GPIO_SWPORTA_DDR_REG);
238 if (flags & GPIO_PIN_INPUT)
239 ddr &= ~__BIT(pin);
240 else if (flags & GPIO_PIN_OUTPUT)
241 ddr |= __BIT(pin);
242 WR4(sc, GPIO_SWPORTA_DDR_REG, ddr);
243 mutex_exit(&sc->sc_lock);
244 }
245
246 static int
rk_gpio_v2_pin_read(void * priv,int pin)247 rk_gpio_v2_pin_read(void *priv, int pin)
248 {
249 struct rk_gpio_softc * const sc = priv;
250 uint32_t data;
251 int val;
252
253 KASSERT(pin < __arraycount(sc->sc_pins));
254
255 const uint32_t data_mask = __BIT(pin);
256
257 /* No lock required for reads */
258 data = RD4(sc, GPIOV2_EXT_PORT_REG);
259 val = __SHIFTOUT(data, data_mask);
260
261 return val;
262 }
263
264 static void
rk_gpio_v2_pin_write(void * priv,int pin,int val)265 rk_gpio_v2_pin_write(void *priv, int pin, int val)
266 {
267 struct rk_gpio_softc * const sc = priv;
268 uint32_t data;
269
270 KASSERT(pin < __arraycount(sc->sc_pins));
271
272 const uint32_t write_mask = GPIOV2_WRITE_MASK(pin);
273
274 /* No lock required for writes on v2 controllers */
275 data = val ? GPIOV2_DATA_MASK(pin) : 0;
276 WR4(sc, GPIOV2_SWPORT_DR_REG(pin), write_mask | data);
277 }
278
279 static void
rk_gpio_v2_pin_ctl(void * priv,int pin,int flags)280 rk_gpio_v2_pin_ctl(void *priv, int pin, int flags)
281 {
282 struct rk_gpio_softc * const sc = priv;
283 uint32_t ddr;
284
285 KASSERT(pin < __arraycount(sc->sc_pins));
286
287 /* No lock required for writes on v2 controllers */
288 ddr = (flags & GPIO_PIN_OUTPUT) ? GPIOV2_DATA_MASK(pin) : 0;
289 WR4(sc, GPIOV2_SWPORT_DDR_REG(pin), GPIOV2_WRITE_MASK(pin) | ddr);
290 }
291
292 static void
rk_gpio_attach_ports(struct rk_gpio_softc * sc)293 rk_gpio_attach_ports(struct rk_gpio_softc *sc)
294 {
295 struct gpiobus_attach_args gba;
296 u_int pin;
297
298 for (pin = 0; pin < __arraycount(sc->sc_pins); pin++) {
299 sc->sc_pins[pin].pin_num = pin;
300 sc->sc_pins[pin].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT;
301 sc->sc_pins[pin].pin_state = rk_gpio_pin_read(sc, pin);
302 }
303
304 memset(&gba, 0, sizeof(gba));
305 gba.gba_gc = &sc->sc_gp;
306 gba.gba_pins = sc->sc_pins;
307 gba.gba_npins = __arraycount(sc->sc_pins);
308 sc->sc_gpiodev = config_found(sc->sc_dev, &gba, NULL, CFARGS_NONE);
309 }
310
311 static int
rk_gpio_match(device_t parent,cfdata_t cf,void * aux)312 rk_gpio_match(device_t parent, cfdata_t cf, void *aux)
313 {
314 struct fdt_attach_args * const faa = aux;
315
316 return of_compatible_match(faa->faa_phandle, compat_data);
317 }
318
319 static void
rk_gpio_attach(device_t parent,device_t self,void * aux)320 rk_gpio_attach(device_t parent, device_t self, void *aux)
321 {
322 struct rk_gpio_softc * const sc = device_private(self);
323 struct gpio_chipset_tag * const gp = &sc->sc_gp;
324 struct fdt_attach_args * const faa = aux;
325 const int phandle = faa->faa_phandle;
326 struct clk *clk;
327 bus_addr_t addr;
328 bus_size_t size;
329 uint32_t ver_id;
330 int ver;
331
332 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
333 aprint_error(": couldn't get registers\n");
334 return;
335 }
336
337 if ((clk = fdtbus_clock_get_index(phandle, 0)) == NULL || clk_enable(clk) != 0) {
338 aprint_error(": couldn't enable clock\n");
339 return;
340 }
341
342 sc->sc_dev = self;
343 sc->sc_bst = faa->faa_bst;
344 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
345 aprint_error(": couldn't map registers\n");
346 return;
347 }
348
349 gp->gp_cookie = sc;
350 ver_id = RD4(sc, GPIO_VER_ID_REG);
351 switch (ver_id) {
352 case 0: /* VER_ID not implemented in v1 but reads back as 0 */
353 ver = 1;
354 gp->gp_pin_read = rk_gpio_pin_read;
355 gp->gp_pin_write = rk_gpio_pin_write;
356 gp->gp_pin_ctl = rk_gpio_pin_ctl;
357 break;
358 case GPIO_VER_ID_GPIOV2:
359 ver = 2;
360 gp->gp_pin_read = rk_gpio_v2_pin_read;
361 gp->gp_pin_write = rk_gpio_v2_pin_write;
362 gp->gp_pin_ctl = rk_gpio_v2_pin_ctl;
363 break;
364 default:
365 aprint_error(": unknown version 0x%08" PRIx32 "\n", ver_id);
366 return;
367 }
368
369 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
370
371 aprint_naive("\n");
372 aprint_normal(": GPIO v%d (%s)\n", ver, fdtbus_get_string(phandle, "name"));
373
374 fdtbus_register_gpio_controller(self, phandle, &rk_gpio_funcs);
375
376 rk_gpio_attach_ports(sc);
377 }
378