1 /* $NetBSD: rk3588_iomux.c,v 1.2 2024/02/07 04:20:27 msaitoh Exp $ */
2
3 /*-
4 * Copyright (c) 2022 Ryo Shimizu
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
17 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: rk3588_iomux.c,v 1.2 2024/02/07 04:20:27 msaitoh Exp $");
31
32 #include <sys/param.h>
33 #include <sys/device.h>
34
35 #include <dev/fdt/fdtvar.h>
36 #include <dev/fdt/syscon.h>
37
38 /* #define RK3588_IOMUX_DEBUG */
39
40 struct rk3588_iomux_softc {
41 device_t sc_dev;
42 struct syscon *sc_grf;
43 };
44
45 static int rk3588_iomux_match(device_t, cfdata_t, void *);
46 static void rk3588_iomux_attach(device_t, device_t, void *);
47
48 CFATTACH_DECL_NEW(rk3588_iomux, sizeof(struct rk3588_iomux_softc),
49 rk3588_iomux_match, rk3588_iomux_attach, NULL, NULL);
50
51 static const struct device_compatible_entry compat_data[] = {
52 { .compat = "rockchip,rk3588-pinctrl" },
53 DEVICE_COMPAT_EOL
54 };
55
56 /* GRF offsets */
57 #define RK3588_PMU1_IOC_REG 0x00000000
58 #define RK3588_PMU2_IOC_REG 0x00004000
59 #define RK3588_BUS_IOC_REG 0x00008000
60 #define RK3588_VCCIO1_4_IOC_REG 0x00009000
61 #define RK3588_VCCIO3_5_IOC_REG 0x0000a000
62 #define RK3588_VCCIO2_IOC_REG 0x0000b000
63 #define RK3588_VCCIO6_IOC_REG 0x0000c000
64 #define RK3588_EMMC_IOC_REG 0x0000d000
65
66 #define NBANKS 5
67 #define NPINPERBANK 32
68 #define NPINS (NBANKS * NPINPERBANK)
69
70 #define PIN(bank, idx) (((bank) * NPINPERBANK) + (idx))
71
72 struct regmask {
73 bus_size_t reg;
74 uint32_t mask;
75 };
76
77 struct regmaskreg {
78 bus_size_t reg;
79 uint32_t mask;
80 bus_size_t reg0;
81 };
82
83 static const struct regmask rk3588_drive_regmap[NBANKS * NPINPERBANK] = {
84 /* GPIO0_A[0-7] */
85 { RK3588_PMU1_IOC_REG + 0x0010, __BITS(3,0) },
86 { RK3588_PMU1_IOC_REG + 0x0010, __BITS(7,4) },
87 { RK3588_PMU1_IOC_REG + 0x0010, __BITS(11,8) },
88 { RK3588_PMU1_IOC_REG + 0x0010, __BITS(15,12) },
89 { RK3588_PMU1_IOC_REG + 0x0014, __BITS(3,0) },
90 { RK3588_PMU1_IOC_REG + 0x0014, __BITS(7,4) },
91 { RK3588_PMU1_IOC_REG + 0x0014, __BITS(11,8) },
92 { RK3588_PMU1_IOC_REG + 0x0014, __BITS(15,12) },
93 /* GPIO0_B[0-7] */
94 { RK3588_PMU1_IOC_REG + 0x0018, __BITS(3,0) },
95 { RK3588_PMU1_IOC_REG + 0x0018, __BITS(7,4) },
96 { RK3588_PMU1_IOC_REG + 0x0018, __BITS(11,8) },
97 { RK3588_PMU1_IOC_REG + 0x0018, __BITS(15,12) },
98 { RK3588_PMU2_IOC_REG + 0x0014, __BITS(3,0) },
99 { RK3588_PMU2_IOC_REG + 0x0014, __BITS(7,4) },
100 { RK3588_PMU2_IOC_REG + 0x0014, __BITS(11,8) },
101 { RK3588_PMU2_IOC_REG + 0x0014, __BITS(15,12) },
102 /* GPIO0_C[0-7] */
103 { RK3588_PMU2_IOC_REG + 0x0018, __BITS(3,0) },
104 { RK3588_PMU2_IOC_REG + 0x0018, __BITS(7,4) },
105 { RK3588_PMU2_IOC_REG + 0x0018, __BITS(11,8) },
106 { RK3588_PMU2_IOC_REG + 0x0018, __BITS(15,12) },
107 { RK3588_PMU2_IOC_REG + 0x001c, __BITS(3,0) },
108 { RK3588_PMU2_IOC_REG + 0x001c, __BITS(7,4) },
109 { RK3588_PMU2_IOC_REG + 0x001c, __BITS(11,8) },
110 { RK3588_PMU2_IOC_REG + 0x001c, __BITS(15,12) },
111 /* GPIO0_D[0-7] */
112 { RK3588_PMU2_IOC_REG + 0x0020, __BITS(3,0) },
113 { RK3588_PMU2_IOC_REG + 0x0020, __BITS(7,4) },
114 { RK3588_PMU2_IOC_REG + 0x0020, __BITS(11,8) },
115 { RK3588_PMU2_IOC_REG + 0x0020, __BITS(15,12) },
116 { RK3588_PMU2_IOC_REG + 0x0024, __BITS(3,0) },
117 { RK3588_PMU2_IOC_REG + 0x0024, __BITS(7,4) },
118 { RK3588_PMU2_IOC_REG + 0x0024, __BITS(11,8) },
119 { RK3588_PMU2_IOC_REG + 0x0024, __BITS(15,12) },
120
121 /* GPIO1_A[0-7] */
122 { RK3588_VCCIO1_4_IOC_REG + 0x0020, __BITS(3,0) },
123 { RK3588_VCCIO1_4_IOC_REG + 0x0020, __BITS(7,4) },
124 { RK3588_VCCIO1_4_IOC_REG + 0x0020, __BITS(11,8) },
125 { RK3588_VCCIO1_4_IOC_REG + 0x0020, __BITS(15,12) },
126 { RK3588_VCCIO1_4_IOC_REG + 0x0024, __BITS(3,0) },
127 { RK3588_VCCIO1_4_IOC_REG + 0x0024, __BITS(7,4) },
128 { RK3588_VCCIO1_4_IOC_REG + 0x0024, __BITS(11,8) },
129 { RK3588_VCCIO1_4_IOC_REG + 0x0024, __BITS(15,12) },
130 /* GPIO1_B[0-7] */
131 { RK3588_VCCIO1_4_IOC_REG + 0x0028, __BITS(3,0) },
132 { RK3588_VCCIO1_4_IOC_REG + 0x0028, __BITS(7,4) },
133 { RK3588_VCCIO1_4_IOC_REG + 0x0028, __BITS(11,8) },
134 { RK3588_VCCIO1_4_IOC_REG + 0x0028, __BITS(15,12) },
135 { RK3588_VCCIO1_4_IOC_REG + 0x002c, __BITS(3,0) },
136 { RK3588_VCCIO1_4_IOC_REG + 0x002c, __BITS(7,4) },
137 { RK3588_VCCIO1_4_IOC_REG + 0x002c, __BITS(11,8) },
138 { RK3588_VCCIO1_4_IOC_REG + 0x002c, __BITS(15,12) },
139 /* GPIO1_C[0-7] */
140 { RK3588_VCCIO1_4_IOC_REG + 0x0030, __BITS(3,0) },
141 { RK3588_VCCIO1_4_IOC_REG + 0x0030, __BITS(7,4) },
142 { RK3588_VCCIO1_4_IOC_REG + 0x0030, __BITS(11,8) },
143 { RK3588_VCCIO1_4_IOC_REG + 0x0030, __BITS(15,12) },
144 { RK3588_VCCIO1_4_IOC_REG + 0x0034, __BITS(3,0) },
145 { RK3588_VCCIO1_4_IOC_REG + 0x0034, __BITS(7,4) },
146 { RK3588_VCCIO1_4_IOC_REG + 0x0034, __BITS(11,8) },
147 { RK3588_VCCIO1_4_IOC_REG + 0x0034, __BITS(15,12) },
148 /* GPIO1_D[0-7] */
149 { RK3588_VCCIO1_4_IOC_REG + 0x0038, __BITS(3,0) },
150 { RK3588_VCCIO1_4_IOC_REG + 0x0038, __BITS(7,4) },
151 { RK3588_VCCIO1_4_IOC_REG + 0x0038, __BITS(11,8) },
152 { RK3588_VCCIO1_4_IOC_REG + 0x0038, __BITS(15,12) },
153 { RK3588_VCCIO1_4_IOC_REG + 0x003c, __BITS(3,0) },
154 { RK3588_VCCIO1_4_IOC_REG + 0x003c, __BITS(7,4) },
155 { RK3588_VCCIO1_4_IOC_REG + 0x003c, __BITS(11,8) },
156 { RK3588_VCCIO1_4_IOC_REG + 0x003c, __BITS(15,12) },
157
158 /* GPIO2_A[0-7] */
159 { RK3588_EMMC_IOC_REG + 0x0040, __BITS(3,0) },
160 { RK3588_EMMC_IOC_REG + 0x0040, __BITS(7,4) },
161 { RK3588_EMMC_IOC_REG + 0x0040, __BITS(11,8) },
162 { RK3588_EMMC_IOC_REG + 0x0040, __BITS(15,12) },
163 { RK3588_VCCIO3_5_IOC_REG + 0x0044, __BITS(3,0) },
164 { RK3588_VCCIO3_5_IOC_REG + 0x0044, __BITS(7,4) },
165 { RK3588_VCCIO3_5_IOC_REG + 0x0044, __BITS(11,8) },
166 { RK3588_VCCIO3_5_IOC_REG + 0x0044, __BITS(15,12) },
167 /* GPIO2_B[0-7] */
168 { RK3588_VCCIO3_5_IOC_REG + 0x0048, __BITS(3,0) },
169 { RK3588_VCCIO3_5_IOC_REG + 0x0048, __BITS(7,4) },
170 { RK3588_VCCIO3_5_IOC_REG + 0x0048, __BITS(11,8) },
171 { RK3588_VCCIO3_5_IOC_REG + 0x0048, __BITS(15,12) },
172 { RK3588_VCCIO3_5_IOC_REG + 0x004c, __BITS(3,0) },
173 { RK3588_VCCIO3_5_IOC_REG + 0x004c, __BITS(7,4) },
174 { RK3588_VCCIO3_5_IOC_REG + 0x004c, __BITS(11,8) },
175 { RK3588_VCCIO3_5_IOC_REG + 0x004c, __BITS(15,12) },
176 /* GPIO2_C[0-7] */
177 { RK3588_VCCIO3_5_IOC_REG + 0x0050, __BITS(3,0) },
178 { RK3588_VCCIO3_5_IOC_REG + 0x0050, __BITS(7,4) },
179 { RK3588_VCCIO3_5_IOC_REG + 0x0050, __BITS(11,8) },
180 { RK3588_VCCIO3_5_IOC_REG + 0x0050, __BITS(15,12) },
181 { RK3588_VCCIO3_5_IOC_REG + 0x0054, __BITS(3,0) },
182 { RK3588_VCCIO3_5_IOC_REG + 0x0054, __BITS(7,4) },
183 { RK3588_VCCIO3_5_IOC_REG + 0x0054, __BITS(11,8) },
184 { RK3588_VCCIO3_5_IOC_REG + 0x0054, __BITS(15,12) },
185 /* GPIO2_D[0-7] */
186 { RK3588_EMMC_IOC_REG + 0x0058, __BITS(3,0) },
187 { RK3588_EMMC_IOC_REG + 0x0058, __BITS(7,4) },
188 { RK3588_EMMC_IOC_REG + 0x0058, __BITS(11,8) },
189 { RK3588_EMMC_IOC_REG + 0x0058, __BITS(15,12) },
190 { RK3588_EMMC_IOC_REG + 0x005c, __BITS(3,0) },
191 { RK3588_EMMC_IOC_REG + 0x005c, __BITS(7,4) },
192 { RK3588_EMMC_IOC_REG + 0x005c, __BITS(11,8) },
193 { RK3588_EMMC_IOC_REG + 0x005c, __BITS(15,12) },
194
195 /* GPIO3_A[0-7] */
196 { RK3588_VCCIO3_5_IOC_REG + 0x0060, __BITS(3,0) },
197 { RK3588_VCCIO3_5_IOC_REG + 0x0060, __BITS(7,4) },
198 { RK3588_VCCIO3_5_IOC_REG + 0x0060, __BITS(11,8) },
199 { RK3588_VCCIO3_5_IOC_REG + 0x0060, __BITS(15,12) },
200 { RK3588_VCCIO3_5_IOC_REG + 0x0064, __BITS(3,0) },
201 { RK3588_VCCIO3_5_IOC_REG + 0x0064, __BITS(7,4) },
202 { RK3588_VCCIO3_5_IOC_REG + 0x0064, __BITS(11,8) },
203 { RK3588_VCCIO3_5_IOC_REG + 0x0064, __BITS(15,12) },
204 /* GPIO3_B[0-7] */
205 { RK3588_VCCIO3_5_IOC_REG + 0x0068, __BITS(3,0) },
206 { RK3588_VCCIO3_5_IOC_REG + 0x0068, __BITS(7,4) },
207 { RK3588_VCCIO3_5_IOC_REG + 0x0068, __BITS(11,8) },
208 { RK3588_VCCIO3_5_IOC_REG + 0x0068, __BITS(15,12) },
209 { RK3588_VCCIO3_5_IOC_REG + 0x006c, __BITS(3,0) },
210 { RK3588_VCCIO3_5_IOC_REG + 0x006c, __BITS(7,4) },
211 { RK3588_VCCIO3_5_IOC_REG + 0x006c, __BITS(11,8) },
212 { RK3588_VCCIO3_5_IOC_REG + 0x006c, __BITS(15,12) },
213 /* GPIO3_C[0-7] */
214 { RK3588_VCCIO3_5_IOC_REG + 0x0070, __BITS(3,0) },
215 { RK3588_VCCIO3_5_IOC_REG + 0x0070, __BITS(7,4) },
216 { RK3588_VCCIO3_5_IOC_REG + 0x0070, __BITS(11,8) },
217 { RK3588_VCCIO3_5_IOC_REG + 0x0070, __BITS(15,12) },
218 { RK3588_VCCIO3_5_IOC_REG + 0x0074, __BITS(3,0) },
219 { RK3588_VCCIO3_5_IOC_REG + 0x0074, __BITS(7,4) },
220 { RK3588_VCCIO3_5_IOC_REG + 0x0074, __BITS(11,8) },
221 { RK3588_VCCIO3_5_IOC_REG + 0x0074, __BITS(15,12) },
222 /* GPIO3_D[0-7] */
223 { RK3588_VCCIO3_5_IOC_REG + 0x0078, __BITS(3,0) },
224 { RK3588_VCCIO3_5_IOC_REG + 0x0078, __BITS(7,4) },
225 { RK3588_VCCIO3_5_IOC_REG + 0x0078, __BITS(11,8) },
226 { RK3588_VCCIO3_5_IOC_REG + 0x0078, __BITS(15,12) },
227 { RK3588_VCCIO3_5_IOC_REG + 0x007c, __BITS(3,0) },
228 { RK3588_VCCIO3_5_IOC_REG + 0x007c, __BITS(7,4) },
229 { RK3588_VCCIO3_5_IOC_REG + 0x007c, __BITS(11,8) },
230 { RK3588_VCCIO3_5_IOC_REG + 0x007c, __BITS(15,12) },
231
232 /* GPIO4_A[0-7] */
233 { RK3588_VCCIO6_IOC_REG + 0x0080, __BITS(3,0) },
234 { RK3588_VCCIO6_IOC_REG + 0x0080, __BITS(7,4) },
235 { RK3588_VCCIO6_IOC_REG + 0x0080, __BITS(11,8) },
236 { RK3588_VCCIO6_IOC_REG + 0x0080, __BITS(15,12) },
237 { RK3588_VCCIO6_IOC_REG + 0x0084, __BITS(3,0) },
238 { RK3588_VCCIO6_IOC_REG + 0x0084, __BITS(7,4) },
239 { RK3588_VCCIO6_IOC_REG + 0x0084, __BITS(11,8) },
240 { RK3588_VCCIO6_IOC_REG + 0x0084, __BITS(15,12) },
241 /* GPIO4_B[0-7] */
242 { RK3588_VCCIO6_IOC_REG + 0x0088, __BITS(3,0) },
243 { RK3588_VCCIO6_IOC_REG + 0x0088, __BITS(7,4) },
244 { RK3588_VCCIO6_IOC_REG + 0x0088, __BITS(11,8) },
245 { RK3588_VCCIO6_IOC_REG + 0x0088, __BITS(15,12) },
246 { RK3588_VCCIO6_IOC_REG + 0x008c, __BITS(3,0) },
247 { RK3588_VCCIO6_IOC_REG + 0x008c, __BITS(7,4) },
248 { RK3588_VCCIO6_IOC_REG + 0x008c, __BITS(11,8) },
249 { RK3588_VCCIO6_IOC_REG + 0x008c, __BITS(15,12) },
250 /* GPIO4_C[0-7] */
251 { RK3588_VCCIO6_IOC_REG + 0x0090, __BITS(3,0) },
252 { RK3588_VCCIO6_IOC_REG + 0x0090, __BITS(7,4) },
253 { RK3588_VCCIO3_5_IOC_REG + 0x0090, __BITS(11,8) },
254 { RK3588_VCCIO3_5_IOC_REG + 0x0090, __BITS(15,12) },
255 { RK3588_VCCIO3_5_IOC_REG + 0x0094, __BITS(3,0) },
256 { RK3588_VCCIO3_5_IOC_REG + 0x0094, __BITS(7,4) },
257 { RK3588_VCCIO3_5_IOC_REG + 0x0094, __BITS(11,8) },
258 { RK3588_VCCIO3_5_IOC_REG + 0x0094, __BITS(15,12) },
259 /* GPIO4_D[0-7] */
260 { RK3588_VCCIO2_IOC_REG + 0x0098, __BITS(3,0) },
261 { RK3588_VCCIO2_IOC_REG + 0x0098, __BITS(7,4) },
262 { RK3588_VCCIO2_IOC_REG + 0x0098, __BITS(11,8) },
263 { RK3588_VCCIO2_IOC_REG + 0x0098, __BITS(15,12) },
264 { RK3588_VCCIO2_IOC_REG + 0x009c, __BITS(3,0) },
265 { RK3588_VCCIO2_IOC_REG + 0x009c, __BITS(7,4) },
266 { RK3588_VCCIO2_IOC_REG + 0x009c, __BITS(11,8) },
267 { RK3588_VCCIO2_IOC_REG + 0x009c, __BITS(15,12) }
268 };
269
270 #define RK3588_GPIO_P_CTL_Z 0
271 #define RK3588_GPIO_P_PULLDOWN 1
272 #define RK3588_GPIO_P_DISABLE 2
273 #define RK3588_GPIO_P_PULLUP 3
274
275 static const struct regmask rk3588_pull_regmap[NBANKS * NPINPERBANK] = {
276 /* GPIO0_A[0-7] */
277 { RK3588_PMU1_IOC_REG + 0x0020, __BITS(1,0) },
278 { RK3588_PMU1_IOC_REG + 0x0020, __BITS(3,2) },
279 { RK3588_PMU1_IOC_REG + 0x0020, __BITS(5,4) },
280 { RK3588_PMU1_IOC_REG + 0x0020, __BITS(7,6) },
281 { RK3588_PMU1_IOC_REG + 0x0020, __BITS(9,8) },
282 { RK3588_PMU1_IOC_REG + 0x0020, __BITS(11,10) },
283 { RK3588_PMU1_IOC_REG + 0x0020, __BITS(13,12) },
284 { RK3588_PMU1_IOC_REG + 0x0020, __BITS(15,14) },
285 /* GPIO0_B[0-7] */
286 { RK3588_PMU1_IOC_REG + 0x0024, __BITS(1,0) },
287 { RK3588_PMU1_IOC_REG + 0x0024, __BITS(3,2) },
288 { RK3588_PMU1_IOC_REG + 0x0024, __BITS(5,4) },
289 { RK3588_PMU1_IOC_REG + 0x0024, __BITS(7,6) },
290 { RK3588_PMU1_IOC_REG + 0x0024, __BITS(9,8) },
291 { RK3588_PMU2_IOC_REG + 0x0028, __BITS(11,10) },
292 { RK3588_PMU2_IOC_REG + 0x0028, __BITS(13,12) },
293 { RK3588_PMU2_IOC_REG + 0x0028, __BITS(15,14) },
294 /* GPIO0_C[0-7] */
295 { RK3588_PMU2_IOC_REG + 0x002c, __BITS(1,0) },
296 { RK3588_PMU2_IOC_REG + 0x002c, __BITS(3,2) },
297 { RK3588_PMU2_IOC_REG + 0x002c, __BITS(5,4) },
298 { RK3588_PMU2_IOC_REG + 0x002c, __BITS(7,6) },
299 { RK3588_PMU2_IOC_REG + 0x002c, __BITS(9,8) },
300 { RK3588_PMU2_IOC_REG + 0x002c, __BITS(11,10) },
301 { RK3588_PMU2_IOC_REG + 0x002c, __BITS(13,12) },
302 { RK3588_PMU2_IOC_REG + 0x002c, __BITS(15,14) },
303 /* GPIO0_D[0-7] */
304 { RK3588_PMU2_IOC_REG + 0x0030, __BITS(1,0) },
305 { RK3588_PMU2_IOC_REG + 0x0030, __BITS(3,2) },
306 { RK3588_PMU2_IOC_REG + 0x0030, __BITS(5,4) },
307 { RK3588_PMU2_IOC_REG + 0x0030, __BITS(7,6) },
308 { RK3588_PMU2_IOC_REG + 0x0030, __BITS(9,8) },
309 { RK3588_PMU2_IOC_REG + 0x0030, __BITS(11,10) },
310 { RK3588_PMU2_IOC_REG + 0x0030, __BITS(13,12) },
311 { RK3588_PMU2_IOC_REG + 0x0030, __BITS(15,14) },
312
313 /* GPIO1_A[0-7] */
314 { RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(1,0) },
315 { RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(3,2) },
316 { RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(5,4) },
317 { RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(7,6) },
318 { RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(9,8) },
319 { RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(11,10) },
320 { RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(13,12) },
321 { RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(15,14) },
322 /* GPIO1_B[0-7] */
323 { RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(1,0) },
324 { RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(3,2) },
325 { RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(5,4) },
326 { RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(7,6) },
327 { RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(9,8) },
328 { RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(11,10) },
329 { RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(13,12) },
330 { RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(15,14) },
331 /* GPIO1_C[0-7] */
332 { RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(1,0) },
333 { RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(3,2) },
334 { RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(5,4) },
335 { RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(7,6) },
336 { RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(9,8) },
337 { RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(11,10) },
338 { RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(13,12) },
339 { RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(15,14) },
340 /* GPIO1_D[0-7] */
341 { RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(1,0) },
342 { RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(3,2) },
343 { RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(5,4) },
344 { RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(7,6) },
345 { RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(9,8) },
346 { RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(11,10) },
347 { RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(13,12) },
348 { RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(15,14) },
349
350 /* GPIO2_A[0-7] */
351 { RK3588_EMMC_IOC_REG + 0x0120, __BITS(1,0) },
352 { RK3588_EMMC_IOC_REG + 0x0120, __BITS(3,2) },
353 { RK3588_EMMC_IOC_REG + 0x0120, __BITS(5,4) },
354 { RK3588_EMMC_IOC_REG + 0x0120, __BITS(7,6) },
355 { RK3588_EMMC_IOC_REG + 0x0120, __BITS(9,8) },
356 { RK3588_EMMC_IOC_REG + 0x0120, __BITS(11,10) },
357 { RK3588_VCCIO3_5_IOC_REG + 0x0120, __BITS(13,12) },
358 { RK3588_VCCIO3_5_IOC_REG + 0x0120, __BITS(15,14) },
359 /* GPIO2_B[0-7] */
360 { RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(1,0) },
361 { RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(3,2) },
362 { RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(5,4) },
363 { RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(7,6) },
364 { RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(9,8) },
365 { RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(11,10) },
366 { RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(13,12) },
367 { RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(15,14) },
368 /* GPIO2_C[0-7] */
369 { RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(1,0) },
370 { RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(3,2) },
371 { RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(5,4) },
372 { RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(7,6) },
373 { RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(9,8) },
374 { RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(11,10) },
375 { RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(13,12) },
376 { RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(15,14) },
377 /* GPIO2_D[0-7] */
378 { RK3588_EMMC_IOC_REG + 0x012c, __BITS(1,0) },
379 { RK3588_EMMC_IOC_REG + 0x012c, __BITS(3,2) },
380 { RK3588_EMMC_IOC_REG + 0x012c, __BITS(5,4) },
381 { RK3588_EMMC_IOC_REG + 0x012c, __BITS(7,6) },
382 { RK3588_EMMC_IOC_REG + 0x012c, __BITS(9,8) },
383 { RK3588_EMMC_IOC_REG + 0x012c, __BITS(11,10) },
384 { RK3588_EMMC_IOC_REG + 0x012c, __BITS(13,12) },
385 { RK3588_EMMC_IOC_REG + 0x012c, __BITS(15,14) },
386
387 /* GPIO3_A[0-7] */
388 { RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(1,0) },
389 { RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(3,2) },
390 { RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(5,4) },
391 { RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(7,6) },
392 { RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(9,8) },
393 { RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(11,10) },
394 { RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(13,12) },
395 { RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(15,14) },
396 /* GPIO3_B[0-7] */
397 { RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(1,0) },
398 { RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(3,2) },
399 { RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(5,4) },
400 { RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(7,6) },
401 { RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(9,8) },
402 { RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(11,10) },
403 { RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(13,12) },
404 { RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(15,14) },
405 /* GPIO3_C[0-7] */
406 { RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(1,0) },
407 { RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(3,2) },
408 { RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(5,4) },
409 { RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(7,6) },
410 { RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(9,8) },
411 { RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(11,10) },
412 { RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(13,12) },
413 { RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(15,14) },
414 /* GPIO3_D[0-7] */
415 { RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(1,0) },
416 { RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(3,2) },
417 { RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(5,4) },
418 { RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(7,6) },
419 { RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(9,8) },
420 { RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(11,10) },
421 { RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(13,12) },
422 { RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(15,14) },
423
424 /* GPIO4_A[0-7] */
425 { RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(1,0) },
426 { RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(3,2) },
427 { RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(5,4) },
428 { RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(7,6) },
429 { RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(9,8) },
430 { RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(11,10) },
431 { RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(13,12) },
432 { RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(15,14) },
433 /* GPIO4_B[0-7] */
434 { RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(1,0) },
435 { RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(3,2) },
436 { RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(5,4) },
437 { RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(7,6) },
438 { RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(9,8) },
439 { RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(11,10) },
440 { RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(13,12) },
441 { RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(15,14) },
442 /* GPIO4_C[0-7] */
443 { RK3588_VCCIO6_IOC_REG + 0x0148, __BITS(1,0) },
444 { RK3588_VCCIO6_IOC_REG + 0x0148, __BITS(3,2) },
445 { RK3588_VCCIO3_5_IOC_REG + 0x0148, __BITS(5,4) },
446 { RK3588_VCCIO3_5_IOC_REG + 0x0148, __BITS(7,6) },
447 { RK3588_VCCIO3_5_IOC_REG + 0x0148, __BITS(9,8) },
448 { RK3588_VCCIO3_5_IOC_REG + 0x0148, __BITS(11,10) },
449 { RK3588_VCCIO3_5_IOC_REG + 0x0148, __BITS(13,12) },
450 { RK3588_VCCIO3_5_IOC_REG + 0x0148, __BITS(15,14) },
451 /* GPIO4_D[0-7] */
452 { RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(1,0) },
453 { RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(3,2) },
454 { RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(5,4) },
455 { RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(7,6) },
456 { RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(9,8) },
457 { RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(11,10) },
458 { RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(13,12) },
459 { RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(15,14) }
460 };
461
462 #if notyet
463 static const struct regmask rk3588_schmitt_regmap[NBANKS * NPINPERBANK] = {
464 /* GPIO0_A[0-7] */
465 { RK3588_PMU1_IOC_REG + 0x0030, __BIT(0) },
466 { RK3588_PMU1_IOC_REG + 0x0030, __BIT(1) },
467 { RK3588_PMU1_IOC_REG + 0x0030, __BIT(2) },
468 { RK3588_PMU1_IOC_REG + 0x0030, __BIT(3) },
469 { RK3588_PMU1_IOC_REG + 0x0030, __BIT(4) },
470 { RK3588_PMU1_IOC_REG + 0x0030, __BIT(5) },
471 { RK3588_PMU1_IOC_REG + 0x0030, __BIT(6) },
472 { RK3588_PMU1_IOC_REG + 0x0030, __BIT(7) },
473 /* GPIO0_B[0-7] */
474 { RK3588_PMU1_IOC_REG + 0x0034, __BIT(0) },
475 { RK3588_PMU1_IOC_REG + 0x0034, __BIT(1) },
476 { RK3588_PMU1_IOC_REG + 0x0034, __BIT(2) },
477 { RK3588_PMU1_IOC_REG + 0x0034, __BIT(3) },
478 { RK3588_PMU1_IOC_REG + 0x0034, __BIT(4) },
479 { RK3588_PMU2_IOC_REG + 0x0040, __BIT(5) },
480 { RK3588_PMU2_IOC_REG + 0x0040, __BIT(6) },
481 { RK3588_PMU2_IOC_REG + 0x0040, __BIT(7) },
482 /* GPIO0_C[0-7] */
483 { RK3588_PMU2_IOC_REG + 0x0044, __BIT(0) },
484 { RK3588_PMU2_IOC_REG + 0x0044, __BIT(1) },
485 { RK3588_PMU2_IOC_REG + 0x0044, __BIT(2) },
486 { RK3588_PMU2_IOC_REG + 0x0044, __BIT(3) },
487 { RK3588_PMU2_IOC_REG + 0x0044, __BIT(4) },
488 { RK3588_PMU2_IOC_REG + 0x0044, __BIT(5) },
489 { RK3588_PMU2_IOC_REG + 0x0044, __BIT(6) },
490 { RK3588_PMU2_IOC_REG + 0x0044, __BIT(7) },
491 /* GPIO0_D[0-7] */
492 { RK3588_PMU2_IOC_REG + 0x0048, __BIT(0) },
493 { RK3588_PMU2_IOC_REG + 0x0048, __BIT(1) },
494 { RK3588_PMU2_IOC_REG + 0x0048, __BIT(2) },
495 { RK3588_PMU2_IOC_REG + 0x0048, __BIT(3) },
496 { RK3588_PMU2_IOC_REG + 0x0048, __BIT(4) },
497 { RK3588_PMU2_IOC_REG + 0x0048, __BIT(5) },
498 { RK3588_PMU2_IOC_REG + 0x0048, __BIT(6) },
499 { RK3588_PMU2_IOC_REG + 0x0048, __BIT(7) },
500
501 /* GPIO1_A[0-7] */
502 { RK3588_VCCIO1_4_IOC_REG + 0x0210, __BIT(0) },
503 { RK3588_VCCIO1_4_IOC_REG + 0x0210, __BIT(1) },
504 { RK3588_VCCIO1_4_IOC_REG + 0x0210, __BIT(2) },
505 { RK3588_VCCIO1_4_IOC_REG + 0x0210, __BIT(3) },
506 { RK3588_VCCIO1_4_IOC_REG + 0x0210, __BIT(4) },
507 { RK3588_VCCIO1_4_IOC_REG + 0x0210, __BIT(5) },
508 { RK3588_VCCIO1_4_IOC_REG + 0x0210, __BIT(6) },
509 { RK3588_VCCIO1_4_IOC_REG + 0x0210, __BIT(7) },
510 /* GPIO1_B[0-7] */
511 { RK3588_VCCIO1_4_IOC_REG + 0x0214, __BIT(0) },
512 { RK3588_VCCIO1_4_IOC_REG + 0x0214, __BIT(1) },
513 { RK3588_VCCIO1_4_IOC_REG + 0x0214, __BIT(2) },
514 { RK3588_VCCIO1_4_IOC_REG + 0x0214, __BIT(3) },
515 { RK3588_VCCIO1_4_IOC_REG + 0x0214, __BIT(4) },
516 { RK3588_VCCIO1_4_IOC_REG + 0x0214, __BIT(5) },
517 { RK3588_VCCIO1_4_IOC_REG + 0x0214, __BIT(6) },
518 { RK3588_VCCIO1_4_IOC_REG + 0x0214, __BIT(7) },
519 /* GPIO1_C[0-7] */
520 { RK3588_VCCIO1_4_IOC_REG + 0x0218, __BIT(0) },
521 { RK3588_VCCIO1_4_IOC_REG + 0x0218, __BIT(1) },
522 { RK3588_VCCIO1_4_IOC_REG + 0x0218, __BIT(2) },
523 { RK3588_VCCIO1_4_IOC_REG + 0x0218, __BIT(3) },
524 { RK3588_VCCIO1_4_IOC_REG + 0x0218, __BIT(4) },
525 { RK3588_VCCIO1_4_IOC_REG + 0x0218, __BIT(5) },
526 { RK3588_VCCIO1_4_IOC_REG + 0x0218, __BIT(6) },
527 { RK3588_VCCIO1_4_IOC_REG + 0x0218, __BIT(7) },
528 /* GPIO1_D[0-7] */
529 { RK3588_VCCIO1_4_IOC_REG + 0x021c, __BIT(0) },
530 { RK3588_VCCIO1_4_IOC_REG + 0x021c, __BIT(1) },
531 { RK3588_VCCIO1_4_IOC_REG + 0x021c, __BIT(2) },
532 { RK3588_VCCIO1_4_IOC_REG + 0x021c, __BIT(3) },
533 { RK3588_VCCIO1_4_IOC_REG + 0x021c, __BIT(4) },
534 { RK3588_VCCIO1_4_IOC_REG + 0x021c, __BIT(5) },
535 { RK3588_VCCIO1_4_IOC_REG + 0x021c, __BIT(6) },
536 { RK3588_VCCIO1_4_IOC_REG + 0x021c, __BIT(7) },
537
538 /* GPIO2_A[0-7] */
539 { RK3588_EMMC_IOC_REG + 0x0220, __BIT(0) },
540 { RK3588_EMMC_IOC_REG + 0x0220, __BIT(1) },
541 { RK3588_EMMC_IOC_REG + 0x0220, __BIT(2) },
542 { RK3588_EMMC_IOC_REG + 0x0220, __BIT(3) },
543 { RK3588_EMMC_IOC_REG + 0x0220, __BIT(4) },
544 { RK3588_EMMC_IOC_REG + 0x0220, __BIT(5) },
545 { RK3588_VCCIO3_5_IOC_REG + 0x0220, __BIT(6) },
546 { RK3588_VCCIO3_5_IOC_REG + 0x0220, __BIT(7) },
547 /* GPIO2_B[0-7] */
548 { RK3588_VCCIO3_5_IOC_REG + 0x0224, __BIT(0) },
549 { RK3588_VCCIO3_5_IOC_REG + 0x0224, __BIT(1) },
550 { RK3588_VCCIO3_5_IOC_REG + 0x0224, __BIT(2) },
551 { RK3588_VCCIO3_5_IOC_REG + 0x0224, __BIT(3) },
552 { RK3588_VCCIO3_5_IOC_REG + 0x0224, __BIT(4) },
553 { RK3588_VCCIO3_5_IOC_REG + 0x0224, __BIT(5) },
554 { RK3588_VCCIO3_5_IOC_REG + 0x0224, __BIT(6) },
555 { RK3588_VCCIO3_5_IOC_REG + 0x0224, __BIT(7) },
556 /* GPIO2_C[0-7] */
557 { RK3588_VCCIO3_5_IOC_REG + 0x0228, __BIT(0) },
558 { RK3588_VCCIO3_5_IOC_REG + 0x0228, __BIT(1) },
559 { RK3588_VCCIO3_5_IOC_REG + 0x0228, __BIT(2) },
560 { RK3588_VCCIO3_5_IOC_REG + 0x0228, __BIT(3) },
561 { RK3588_VCCIO3_5_IOC_REG + 0x0228, __BIT(4) },
562 { RK3588_VCCIO3_5_IOC_REG + 0x0228, __BIT(5) },
563 { RK3588_VCCIO3_5_IOC_REG + 0x0228, __BIT(6) },
564 { RK3588_VCCIO3_5_IOC_REG + 0x0228, __BIT(7) },
565 /* GPIO2_D[0-7] */
566 { RK3588_EMMC_IOC_REG + 0x022c, __BIT(0) },
567 { RK3588_EMMC_IOC_REG + 0x022c, __BIT(1) },
568 { RK3588_EMMC_IOC_REG + 0x022c, __BIT(2) },
569 { RK3588_EMMC_IOC_REG + 0x022c, __BIT(3) },
570 { RK3588_EMMC_IOC_REG + 0x022c, __BIT(4) },
571 { RK3588_EMMC_IOC_REG + 0x022c, __BIT(5) },
572 { RK3588_EMMC_IOC_REG + 0x022c, __BIT(6) },
573 { RK3588_EMMC_IOC_REG + 0x022c, __BIT(7) },
574
575 /* GPIO3_A[0-7] */
576 { RK3588_VCCIO3_5_IOC_REG + 0x0230, __BIT(0) },
577 { RK3588_VCCIO3_5_IOC_REG + 0x0230, __BIT(1) },
578 { RK3588_VCCIO3_5_IOC_REG + 0x0230, __BIT(2) },
579 { RK3588_VCCIO3_5_IOC_REG + 0x0230, __BIT(3) },
580 { RK3588_VCCIO3_5_IOC_REG + 0x0230, __BIT(4) },
581 { RK3588_VCCIO3_5_IOC_REG + 0x0230, __BIT(5) },
582 { RK3588_VCCIO3_5_IOC_REG + 0x0230, __BIT(6) },
583 { RK3588_VCCIO3_5_IOC_REG + 0x0230, __BIT(7) },
584 /* GPIO3_B[0-7] */
585 { RK3588_VCCIO3_5_IOC_REG + 0x0234, __BIT(0) },
586 { RK3588_VCCIO3_5_IOC_REG + 0x0234, __BIT(1) },
587 { RK3588_VCCIO3_5_IOC_REG + 0x0234, __BIT(2) },
588 { RK3588_VCCIO3_5_IOC_REG + 0x0234, __BIT(3) },
589 { RK3588_VCCIO3_5_IOC_REG + 0x0234, __BIT(4) },
590 { RK3588_VCCIO3_5_IOC_REG + 0x0234, __BIT(5) },
591 { RK3588_VCCIO3_5_IOC_REG + 0x0234, __BIT(6) },
592 { RK3588_VCCIO3_5_IOC_REG + 0x0234, __BIT(7) },
593 /* GPIO3_C[0-7] */
594 { RK3588_VCCIO3_5_IOC_REG + 0x0238, __BIT(0) },
595 { RK3588_VCCIO3_5_IOC_REG + 0x0238, __BIT(1) },
596 { RK3588_VCCIO3_5_IOC_REG + 0x0238, __BIT(2) },
597 { RK3588_VCCIO3_5_IOC_REG + 0x0238, __BIT(3) },
598 { RK3588_VCCIO3_5_IOC_REG + 0x0238, __BIT(4) },
599 { RK3588_VCCIO3_5_IOC_REG + 0x0238, __BIT(5) },
600 { RK3588_VCCIO3_5_IOC_REG + 0x0238, __BIT(6) },
601 { RK3588_VCCIO3_5_IOC_REG + 0x0238, __BIT(7) },
602 /* GPIO3_D[0-7] */
603 { RK3588_VCCIO3_5_IOC_REG + 0x023c, __BIT(0) },
604 { RK3588_VCCIO3_5_IOC_REG + 0x023c, __BIT(1) },
605 { RK3588_VCCIO3_5_IOC_REG + 0x023c, __BIT(2) },
606 { RK3588_VCCIO3_5_IOC_REG + 0x023c, __BIT(3) },
607 { RK3588_VCCIO3_5_IOC_REG + 0x023c, __BIT(4) },
608 { RK3588_VCCIO3_5_IOC_REG + 0x023c, __BIT(5) },
609 { RK3588_VCCIO3_5_IOC_REG + 0x023c, __BIT(6) },
610 { RK3588_VCCIO3_5_IOC_REG + 0x023c, __BIT(7) },
611
612 /* GPIO4_A[0-7] */
613 { RK3588_VCCIO6_IOC_REG + 0x0240, __BIT(0) },
614 { RK3588_VCCIO6_IOC_REG + 0x0240, __BIT(1) },
615 { RK3588_VCCIO6_IOC_REG + 0x0240, __BIT(2) },
616 { RK3588_VCCIO6_IOC_REG + 0x0240, __BIT(3) },
617 { RK3588_VCCIO6_IOC_REG + 0x0240, __BIT(4) },
618 { RK3588_VCCIO6_IOC_REG + 0x0240, __BIT(5) },
619 { RK3588_VCCIO6_IOC_REG + 0x0240, __BIT(6) },
620 { RK3588_VCCIO6_IOC_REG + 0x0240, __BIT(7) },
621 /* GPIO4_B[0-7] */
622 { RK3588_VCCIO6_IOC_REG + 0x0244, __BIT(0) },
623 { RK3588_VCCIO6_IOC_REG + 0x0244, __BIT(1) },
624 { RK3588_VCCIO6_IOC_REG + 0x0244, __BIT(2) },
625 { RK3588_VCCIO6_IOC_REG + 0x0244, __BIT(3) },
626 { RK3588_VCCIO6_IOC_REG + 0x0244, __BIT(4) },
627 { RK3588_VCCIO6_IOC_REG + 0x0244, __BIT(5) },
628 { RK3588_VCCIO6_IOC_REG + 0x0244, __BIT(6) },
629 { RK3588_VCCIO6_IOC_REG + 0x0244, __BIT(7) },
630 /* GPIO4_C[0-7] */
631 { RK3588_VCCIO6_IOC_REG + 0x0248, __BIT(0) },
632 { RK3588_VCCIO6_IOC_REG + 0x0248, __BIT(1) },
633 { RK3588_VCCIO3_5_IOC_REG + 0x0248, __BIT(2) },
634 { RK3588_VCCIO3_5_IOC_REG + 0x0248, __BIT(3) },
635 { RK3588_VCCIO3_5_IOC_REG + 0x0248, __BIT(4) },
636 { RK3588_VCCIO3_5_IOC_REG + 0x0248, __BIT(5) },
637 { RK3588_VCCIO3_5_IOC_REG + 0x0248, __BIT(6) },
638 { RK3588_VCCIO3_5_IOC_REG + 0x0248, __BIT(7) },
639 /* GPIO4_D[0-7] */
640 { RK3588_VCCIO2_IOC_REG + 0x024c, __BIT(0) },
641 { RK3588_VCCIO2_IOC_REG + 0x024c, __BIT(1) },
642 { RK3588_VCCIO2_IOC_REG + 0x024c, __BIT(2) },
643 { RK3588_VCCIO2_IOC_REG + 0x024c, __BIT(3) },
644 { RK3588_VCCIO2_IOC_REG + 0x024c, __BIT(4) },
645 { RK3588_VCCIO2_IOC_REG + 0x024c, __BIT(5) },
646 { RK3588_VCCIO2_IOC_REG + 0x024c, __BIT(6) },
647 { RK3588_VCCIO2_IOC_REG + 0x024c, __BIT(7) }
648 };
649 #endif
650
651 static const struct regmaskreg rk3588_iomux_regmap[NBANKS * NPINPERBANK] = {
652 /* GPIO0_A[0-7] */
653 { RK3588_PMU1_IOC_REG + 0x0000, __BITS(3,0) },
654 { RK3588_PMU1_IOC_REG + 0x0000, __BITS(7,4) },
655 { RK3588_PMU1_IOC_REG + 0x0000, __BITS(11,8) },
656 { RK3588_PMU1_IOC_REG + 0x0000, __BITS(15,12) },
657 { RK3588_PMU1_IOC_REG + 0x0004, __BITS(3,0) },
658 { RK3588_PMU1_IOC_REG + 0x0004, __BITS(7,4) },
659 { RK3588_PMU1_IOC_REG + 0x0004, __BITS(11,8) },
660 { RK3588_PMU1_IOC_REG + 0x0004, __BITS(15,12) },
661 /* GPIO0_B[0-7] */
662 { RK3588_PMU1_IOC_REG + 0x0008, __BITS(3,0) },
663 { RK3588_PMU1_IOC_REG + 0x0008, __BITS(7,4) },
664 { RK3588_PMU1_IOC_REG + 0x0008, __BITS(11,8) },
665 { RK3588_PMU1_IOC_REG + 0x0008, __BITS(15,12) },
666 { RK3588_BUS_IOC_REG + 0x000c, __BITS(3,0), RK3588_PMU2_IOC_REG + 0x0000 },
667 { RK3588_BUS_IOC_REG + 0x000c, __BITS(7,4), RK3588_PMU2_IOC_REG + 0x0000 },
668 { RK3588_BUS_IOC_REG + 0x000c, __BITS(11,8), RK3588_PMU2_IOC_REG + 0x0000 },
669 { RK3588_BUS_IOC_REG + 0x000c, __BITS(15,12), RK3588_PMU2_IOC_REG + 0x0000 },
670 /* GPIO0_C[0-7] */
671 { RK3588_BUS_IOC_REG + 0x0010, __BITS(3,0), RK3588_PMU2_IOC_REG + 0x0004 },
672 { RK3588_BUS_IOC_REG + 0x0010, __BITS(7,4), RK3588_PMU2_IOC_REG + 0x0004 },
673 { RK3588_BUS_IOC_REG + 0x0010, __BITS(11,8), RK3588_PMU2_IOC_REG + 0x0004 },
674 { RK3588_BUS_IOC_REG + 0x0010, __BITS(15,12), RK3588_PMU2_IOC_REG + 0x0004 },
675 { RK3588_BUS_IOC_REG + 0x0014, __BITS(3,0), RK3588_PMU2_IOC_REG + 0x0008 },
676 { RK3588_BUS_IOC_REG + 0x0014, __BITS(7,4), RK3588_PMU2_IOC_REG + 0x0008 },
677 { RK3588_BUS_IOC_REG + 0x0014, __BITS(11,8), RK3588_PMU2_IOC_REG + 0x0008 },
678 { RK3588_BUS_IOC_REG + 0x0014, __BITS(15,12), RK3588_PMU2_IOC_REG + 0x0008 },
679 /* GPIO0_D[0-7] */
680 { RK3588_BUS_IOC_REG + 0x0018, __BITS(3,0), RK3588_PMU2_IOC_REG + 0x000c },
681 { RK3588_BUS_IOC_REG + 0x0018, __BITS(7,4), RK3588_PMU2_IOC_REG + 0x000c },
682 { RK3588_BUS_IOC_REG + 0x0018, __BITS(11,8), RK3588_PMU2_IOC_REG + 0x000c },
683 { RK3588_BUS_IOC_REG + 0x0018, __BITS(15,12), RK3588_PMU2_IOC_REG + 0x000c },
684 { RK3588_BUS_IOC_REG + 0x001c, __BITS(3,0), RK3588_PMU2_IOC_REG + 0x0010 },
685 { RK3588_BUS_IOC_REG + 0x001c, __BITS(7,4), RK3588_PMU2_IOC_REG + 0x0010 },
686 { RK3588_BUS_IOC_REG + 0x001c, __BITS(11,8), RK3588_PMU2_IOC_REG + 0x0010 },
687 { RK3588_BUS_IOC_REG + 0x001c, __BITS(15,12), RK3588_PMU2_IOC_REG + 0x0010 },
688
689 /* GPIO1_A[0-7] */
690 { RK3588_BUS_IOC_REG + 0x0020, __BITS(3,0) },
691 { RK3588_BUS_IOC_REG + 0x0020, __BITS(7,4) },
692 { RK3588_BUS_IOC_REG + 0x0020, __BITS(11,8) },
693 { RK3588_BUS_IOC_REG + 0x0020, __BITS(15,12) },
694 { RK3588_BUS_IOC_REG + 0x0024, __BITS(3,0) },
695 { RK3588_BUS_IOC_REG + 0x0024, __BITS(7,4) },
696 { RK3588_BUS_IOC_REG + 0x0024, __BITS(11,8) },
697 { RK3588_BUS_IOC_REG + 0x0024, __BITS(15,12) },
698 /* GPIO1_B[0-7] */
699 { RK3588_BUS_IOC_REG + 0x0028, __BITS(3,0) },
700 { RK3588_BUS_IOC_REG + 0x0028, __BITS(7,4) },
701 { RK3588_BUS_IOC_REG + 0x0028, __BITS(11,8) },
702 { RK3588_BUS_IOC_REG + 0x0028, __BITS(15,12) },
703 { RK3588_BUS_IOC_REG + 0x002c, __BITS(3,0) },
704 { RK3588_BUS_IOC_REG + 0x002c, __BITS(7,4) },
705 { RK3588_BUS_IOC_REG + 0x002c, __BITS(11,8) },
706 { RK3588_BUS_IOC_REG + 0x002c, __BITS(15,12) },
707 /* GPIO1_C[0-7] */
708 { RK3588_BUS_IOC_REG + 0x0030, __BITS(3,0) },
709 { RK3588_BUS_IOC_REG + 0x0030, __BITS(7,4) },
710 { RK3588_BUS_IOC_REG + 0x0030, __BITS(11,8) },
711 { RK3588_BUS_IOC_REG + 0x0030, __BITS(15,12) },
712 { RK3588_BUS_IOC_REG + 0x0034, __BITS(3,0) },
713 { RK3588_BUS_IOC_REG + 0x0034, __BITS(7,4) },
714 { RK3588_BUS_IOC_REG + 0x0034, __BITS(11,8) },
715 { RK3588_BUS_IOC_REG + 0x0034, __BITS(15,12) },
716 /* GPIO1_D[0-7] */
717 { RK3588_BUS_IOC_REG + 0x0038, __BITS(3,0) },
718 { RK3588_BUS_IOC_REG + 0x0038, __BITS(7,4) },
719 { RK3588_BUS_IOC_REG + 0x0038, __BITS(11,8) },
720 { RK3588_BUS_IOC_REG + 0x0038, __BITS(15,12) },
721 { RK3588_BUS_IOC_REG + 0x003c, __BITS(3,0) },
722 { RK3588_BUS_IOC_REG + 0x003c, __BITS(7,4) },
723 { RK3588_BUS_IOC_REG + 0x003c, __BITS(11,8) },
724 { RK3588_BUS_IOC_REG + 0x003c, __BITS(15,12) },
725
726 /* GPIO2_A[0-7] */
727 { RK3588_BUS_IOC_REG + 0x0040, __BITS(3,0) },
728 { RK3588_BUS_IOC_REG + 0x0040, __BITS(7,4) },
729 { RK3588_BUS_IOC_REG + 0x0040, __BITS(11,8) },
730 { RK3588_BUS_IOC_REG + 0x0040, __BITS(15,12) },
731 { RK3588_BUS_IOC_REG + 0x0044, __BITS(3,0) },
732 { RK3588_BUS_IOC_REG + 0x0044, __BITS(7,4) },
733 { RK3588_BUS_IOC_REG + 0x0044, __BITS(11,8) },
734 { RK3588_BUS_IOC_REG + 0x0044, __BITS(15,12) },
735 /* GPIO2_B[0-7] */
736 { RK3588_BUS_IOC_REG + 0x0048, __BITS(3,0) },
737 { RK3588_BUS_IOC_REG + 0x0048, __BITS(7,4) },
738 { RK3588_BUS_IOC_REG + 0x0048, __BITS(11,8) },
739 { RK3588_BUS_IOC_REG + 0x0048, __BITS(15,12) },
740 { RK3588_BUS_IOC_REG + 0x004c, __BITS(3,0) },
741 { RK3588_BUS_IOC_REG + 0x004c, __BITS(7,4) },
742 { RK3588_BUS_IOC_REG + 0x004c, __BITS(11,8) },
743 { RK3588_BUS_IOC_REG + 0x004c, __BITS(15,12) },
744 /* GPIO2_C[0-7] */
745 { RK3588_BUS_IOC_REG + 0x0050, __BITS(3,0) },
746 { RK3588_BUS_IOC_REG + 0x0050, __BITS(7,4) },
747 { RK3588_BUS_IOC_REG + 0x0050, __BITS(11,8) },
748 { RK3588_BUS_IOC_REG + 0x0050, __BITS(15,12) },
749 { RK3588_BUS_IOC_REG + 0x0054, __BITS(3,0) },
750 { RK3588_BUS_IOC_REG + 0x0054, __BITS(7,4) },
751 { RK3588_BUS_IOC_REG + 0x0054, __BITS(11,8) },
752 { RK3588_BUS_IOC_REG + 0x0054, __BITS(15,12) },
753 /* GPIO2_D[0-7] */
754 { RK3588_BUS_IOC_REG + 0x0058, __BITS(3,0) },
755 { RK3588_BUS_IOC_REG + 0x0058, __BITS(7,4) },
756 { RK3588_BUS_IOC_REG + 0x0058, __BITS(11,8) },
757 { RK3588_BUS_IOC_REG + 0x0058, __BITS(15,12) },
758 { RK3588_BUS_IOC_REG + 0x005c, __BITS(3,0) },
759 { RK3588_BUS_IOC_REG + 0x005c, __BITS(7,4) },
760 { RK3588_BUS_IOC_REG + 0x005c, __BITS(11,8) },
761 { RK3588_BUS_IOC_REG + 0x005c, __BITS(15,12) },
762
763 /* GPIO3_A[0-7] */
764 { RK3588_BUS_IOC_REG + 0x0060, __BITS(3,0) },
765 { RK3588_BUS_IOC_REG + 0x0060, __BITS(7,4) },
766 { RK3588_BUS_IOC_REG + 0x0060, __BITS(11,8) },
767 { RK3588_BUS_IOC_REG + 0x0060, __BITS(15,12) },
768 { RK3588_BUS_IOC_REG + 0x0064, __BITS(3,0) },
769 { RK3588_BUS_IOC_REG + 0x0064, __BITS(7,4) },
770 { RK3588_BUS_IOC_REG + 0x0064, __BITS(11,8) },
771 { RK3588_BUS_IOC_REG + 0x0064, __BITS(15,12) },
772 /* GPIO3_B[0-7] */
773 { RK3588_BUS_IOC_REG + 0x0068, __BITS(3,0) },
774 { RK3588_BUS_IOC_REG + 0x0068, __BITS(7,4) },
775 { RK3588_BUS_IOC_REG + 0x0068, __BITS(11,8) },
776 { RK3588_BUS_IOC_REG + 0x0068, __BITS(15,12) },
777 { RK3588_BUS_IOC_REG + 0x006c, __BITS(3,0) },
778 { RK3588_BUS_IOC_REG + 0x006c, __BITS(7,4) },
779 { RK3588_BUS_IOC_REG + 0x006c, __BITS(11,8) },
780 { RK3588_BUS_IOC_REG + 0x006c, __BITS(15,12) },
781 /* GPIO3_C[0-7] */
782 { RK3588_BUS_IOC_REG + 0x0070, __BITS(3,0) },
783 { RK3588_BUS_IOC_REG + 0x0070, __BITS(7,4) },
784 { RK3588_BUS_IOC_REG + 0x0070, __BITS(11,8) },
785 { RK3588_BUS_IOC_REG + 0x0070, __BITS(15,12) },
786 { RK3588_BUS_IOC_REG + 0x0074, __BITS(3,0) },
787 { RK3588_BUS_IOC_REG + 0x0074, __BITS(7,4) },
788 { RK3588_BUS_IOC_REG + 0x0074, __BITS(11,8) },
789 { RK3588_BUS_IOC_REG + 0x0074, __BITS(15,12) },
790 /* GPIO3_D[0-7] */
791 { RK3588_BUS_IOC_REG + 0x0078, __BITS(3,0) },
792 { RK3588_BUS_IOC_REG + 0x0078, __BITS(7,4) },
793 { RK3588_BUS_IOC_REG + 0x0078, __BITS(11,8) },
794 { RK3588_BUS_IOC_REG + 0x0078, __BITS(15,12) },
795 { RK3588_BUS_IOC_REG + 0x007c, __BITS(3,0) },
796 { RK3588_BUS_IOC_REG + 0x007c, __BITS(7,4) },
797 { RK3588_BUS_IOC_REG + 0x007c, __BITS(11,8) },
798 { RK3588_BUS_IOC_REG + 0x007c, __BITS(15,12) },
799
800 /* GPIO4_A[0-7] */
801 { RK3588_BUS_IOC_REG + 0x0080, __BITS(3,0) },
802 { RK3588_BUS_IOC_REG + 0x0080, __BITS(7,4) },
803 { RK3588_BUS_IOC_REG + 0x0080, __BITS(11,8) },
804 { RK3588_BUS_IOC_REG + 0x0080, __BITS(15,12) },
805 { RK3588_BUS_IOC_REG + 0x0084, __BITS(3,0) },
806 { RK3588_BUS_IOC_REG + 0x0084, __BITS(7,4) },
807 { RK3588_BUS_IOC_REG + 0x0084, __BITS(11,8) },
808 { RK3588_BUS_IOC_REG + 0x0084, __BITS(15,12) },
809 /* GPIO4_B[0-7] */
810 { RK3588_BUS_IOC_REG + 0x0088, __BITS(3,0) },
811 { RK3588_BUS_IOC_REG + 0x0088, __BITS(7,4) },
812 { RK3588_BUS_IOC_REG + 0x0088, __BITS(11,8) },
813 { RK3588_BUS_IOC_REG + 0x0088, __BITS(15,12) },
814 { RK3588_BUS_IOC_REG + 0x008c, __BITS(3,0) },
815 { RK3588_BUS_IOC_REG + 0x008c, __BITS(7,4) },
816 { RK3588_BUS_IOC_REG + 0x008c, __BITS(11,8) },
817 { RK3588_BUS_IOC_REG + 0x008c, __BITS(15,12) },
818 /* GPIO4_C[0-7] */
819 { RK3588_BUS_IOC_REG + 0x0090, __BITS(3,0) },
820 { RK3588_BUS_IOC_REG + 0x0090, __BITS(7,4) },
821 { RK3588_BUS_IOC_REG + 0x0090, __BITS(11,8) },
822 { RK3588_BUS_IOC_REG + 0x0090, __BITS(15,12) },
823 { RK3588_BUS_IOC_REG + 0x0094, __BITS(3,0) },
824 { RK3588_BUS_IOC_REG + 0x0094, __BITS(7,4) },
825 { RK3588_BUS_IOC_REG + 0x0094, __BITS(11,8) },
826 { RK3588_BUS_IOC_REG + 0x0094, __BITS(15,12) },
827 /* GPIO4_D[0-7] */
828 { RK3588_BUS_IOC_REG + 0x0098, __BITS(3,0) },
829 { RK3588_BUS_IOC_REG + 0x0098, __BITS(7,4) },
830 { RK3588_BUS_IOC_REG + 0x0098, __BITS(11,8) },
831 { RK3588_BUS_IOC_REG + 0x0098, __BITS(15,12) },
832 { RK3588_BUS_IOC_REG + 0x009c, __BITS(3,0) },
833 { RK3588_BUS_IOC_REG + 0x009c, __BITS(7,4) },
834 { RK3588_BUS_IOC_REG + 0x009c, __BITS(11,8) },
835 { RK3588_BUS_IOC_REG + 0x009c, __BITS(15,12) }
836 };
837
838 #ifdef RK3588_IOMUX_DEBUG
839 static char *
rk3588_iomux_pinname(int pin)840 rk3588_iomux_pinname(int pin)
841 {
842 static char buf[16];
843
844 int bank = pin / 32;
845 int group = (pin / 8) & 3;
846 int idx = pin & 7;
847 snprintf(buf, sizeof(buf), "%d=[%d-RK_P%c%d]",
848 pin, bank, 'A' + group, idx);
849 return buf;
850 }
851 #endif
852
853 static void
rk3588_iomux_set_bias(struct rk3588_iomux_softc * sc,int pin,int bias)854 rk3588_iomux_set_bias(struct rk3588_iomux_softc *sc, int pin, int bias)
855 {
856 uint32_t val;
857
858 switch (bias) {
859 case 0:
860 val = RK3588_GPIO_P_CTL_Z;
861 break;
862 case GPIO_PIN_PULLUP:
863 val = RK3588_GPIO_P_PULLUP;
864 break;
865 case GPIO_PIN_PULLDOWN:
866 val = RK3588_GPIO_P_PULLDOWN;
867 break;
868 default:
869 return;
870 }
871
872 bus_size_t reg = rk3588_pull_regmap[pin].reg;
873 uint32_t mask = rk3588_pull_regmap[pin].mask;
874 val = (mask << 16) | __SHIFTIN(val, mask);
875
876 syscon_write_4(sc->sc_grf, reg, val);
877
878 #ifdef RK3588_IOMUX_DEBUG
879 printf("%s: pin=%s bias %s (reg:%08lx -> %08x)\n", __func__,
880 rk3588_iomux_pinname(pin), (bias == 0) ? "Z" :
881 (bias == GPIO_PIN_PULLUP) ? "PULLUP" : "PULLDOWN",
882 reg, val);
883 #endif
884 }
885
886 static void
rk3588_iomux_set_drive_strength(struct rk3588_iomux_softc * sc,int pin,int drv)887 rk3588_iomux_set_drive_strength(struct rk3588_iomux_softc *sc, int pin, int drv)
888 {
889 if (drv < 0 || drv > 15)
890 return;
891
892 /* Amperage (mA) corresponds directly to register values 0-15 */
893 bus_size_t reg = rk3588_drive_regmap[pin].reg;
894 uint32_t mask = rk3588_drive_regmap[pin].mask;
895 uint32_t val = (mask << 16) | __SHIFTIN(drv, mask);
896
897 syscon_write_4(sc->sc_grf, reg, val);
898
899 #ifdef RK3588_IOMUX_DEBUG
900 printf("%s: pin=%s strength %d (reg:%08lx -> %08x)\n", __func__,
901 rk3588_iomux_pinname(pin), drv, reg, val);
902 #endif
903 }
904
905 static void
rk3588_iomux_set_mux(struct rk3588_iomux_softc * sc,int pin,u_int mux)906 rk3588_iomux_set_mux(struct rk3588_iomux_softc *sc, int pin, u_int mux)
907 {
908 bus_size_t reg = rk3588_iomux_regmap[pin].reg;
909 bus_size_t reg0 = rk3588_iomux_regmap[pin].reg0;
910 uint32_t mask = rk3588_iomux_regmap[pin].mask;
911 uint32_t val;
912
913 if (reg0 != 0) {
914 val = (mask << 16) | __SHIFTIN(__BIT(3), mask);
915 syscon_write_4(sc->sc_grf, reg0, val);
916 }
917
918 val = (mask << 16) | __SHIFTIN(mux, mask);
919 syscon_write_4(sc->sc_grf, reg, val);
920
921 #ifdef RK3588_IOMUX_DEBUG
922 printf("%s: pin=%s mux %d (reg:%08lx -> %08x)\n", __func__,
923 rk3588_iomux_pinname(pin), mux, reg, val);
924 #endif
925 }
926
927 static void
rk3588_iomux_set_direction(struct rk3588_iomux_softc * sc,int pin,int dir,int value)928 rk3588_iomux_set_direction(struct rk3588_iomux_softc *sc, int pin, int dir,
929 int value)
930 {
931 /* XXX: notyet */
932 panic("%s:%d: pin=%d, dir=%d: not supported\n", __func__, __LINE__, pin, dir);
933
934 #ifdef RK3588_IOMUX_DEBUG
935 printf("%s: pin=%s dir %d, value %08x\n", __func__,
936 rk3588_iomux_pinname(pin), dir, value);
937 #endif
938 }
939
940 static int
rk3588_iomux_config(struct rk3588_iomux_softc * sc,const int phandle,u_int bank,u_int idx,u_int mux)941 rk3588_iomux_config(struct rk3588_iomux_softc *sc, const int phandle,
942 u_int bank, u_int idx, u_int mux)
943 {
944 const int pin = PIN(bank, idx);
945
946 if (pin < 0 || pin >= NPINS)
947 return EINVAL;
948
949 int bias = fdtbus_pinctrl_parse_bias(phandle, NULL);
950 if (bias != -1)
951 rk3588_iomux_set_bias(sc, pin, bias);
952
953 int drv = fdtbus_pinctrl_parse_drive_strength(phandle);
954 if (drv != -1)
955 rk3588_iomux_set_drive_strength(sc, pin, drv);
956
957 int output_value;
958 int dir = fdtbus_pinctrl_parse_input_output(phandle, &output_value);
959 if (dir != -1)
960 rk3588_iomux_set_direction(sc, pin, dir, output_value);
961
962 rk3588_iomux_set_mux(sc, pin, mux);
963
964 return 0;
965 }
966
967 static int
rk3588_iomux_pinctrl_set_config(device_t dev,const void * data,size_t len)968 rk3588_iomux_pinctrl_set_config(device_t dev, const void *data, size_t len)
969 {
970 struct rk3588_iomux_softc * const sc = device_private(dev);
971 int pins_len = 0;
972
973 if (len != 4)
974 return -1;
975
976 const int phandle = fdtbus_get_phandle_from_native(be32dec(data));
977 const u_int *pins = fdtbus_get_prop(phandle, "rockchip,pins",
978 &pins_len);
979
980 for (; pins_len >= 16; pins_len -= 16, pins += 4) {
981 const u_int bank = be32toh(pins[0]);
982 const u_int idx = be32toh(pins[1]);
983 const u_int mux = be32toh(pins[2]);
984 const int cfg =
985 fdtbus_get_phandle_from_native(be32toh(pins[3]));
986
987 syscon_lock(sc->sc_grf);
988 rk3588_iomux_config(sc, cfg, bank, idx, mux);
989 syscon_unlock(sc->sc_grf);
990 }
991
992 return 0;
993 }
994
995 static struct fdtbus_pinctrl_controller_func rk3588_iomux_pinctrl_funcs = {
996 .set_config = rk3588_iomux_pinctrl_set_config
997 };
998
999 static int
rk3588_iomux_match(device_t parent,cfdata_t cf,void * aux)1000 rk3588_iomux_match(device_t parent, cfdata_t cf, void *aux)
1001 {
1002 struct fdt_attach_args * const faa = aux;
1003 return of_compatible_match(faa->faa_phandle, compat_data);
1004 }
1005
1006 static void
rk3588_iomux_attach(device_t parent,device_t self,void * aux)1007 rk3588_iomux_attach(device_t parent, device_t self, void *aux)
1008 {
1009 struct rk3588_iomux_softc * const sc = device_private(self);
1010 struct fdt_attach_args * const faa = aux;
1011 const int phandle = faa->faa_phandle;
1012
1013 sc->sc_dev = self;
1014 sc->sc_grf = fdtbus_syscon_acquire(phandle, "rockchip,grf");
1015 if (sc->sc_grf == NULL) {
1016 aprint_error(": couldn't acquire grf syscon\n");
1017 return;
1018 }
1019
1020 aprint_naive("\n");
1021 aprint_normal(": RK3588 IOMUX control\n");
1022
1023 for (int child = OF_child(phandle); child; child = OF_peer(child)) {
1024 for (int sub = OF_child(child); sub; sub = OF_peer(sub)) {
1025 if (!of_hasprop(sub, "rockchip,pins"))
1026 continue;
1027 fdtbus_register_pinctrl_config(self, sub,
1028 &rk3588_iomux_pinctrl_funcs);
1029 }
1030 }
1031
1032 for (int child = OF_child(phandle); child; child = OF_peer(child)) {
1033 struct fdt_attach_args cfaa = *faa;
1034 cfaa.faa_phandle = child;
1035 cfaa.faa_name = fdtbus_get_string(child, "name");
1036 cfaa.faa_quiet = false;
1037
1038 config_found(self, &cfaa, NULL, CFARGS_NONE);
1039 }
1040 }
1041