1 /* $NetBSD: rk3399_pmucru.c,v 1.4 2021/01/27 03:10:19 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30
31 __KERNEL_RCSID(1, "$NetBSD: rk3399_pmucru.c,v 1.4 2021/01/27 03:10:19 thorpej Exp $");
32
33 #include <sys/param.h>
34 #include <sys/bus.h>
35 #include <sys/device.h>
36 #include <sys/systm.h>
37
38 #include <dev/fdt/fdtvar.h>
39
40 #include <arm/rockchip/rk_cru.h>
41 #include <arm/rockchip/rk3399_pmucru.h>
42
43 #define PLL_CON(n) (0x0000 + (n) * 4)
44 #define CLKSEL_CON(n) (0x0080 + (n) * 4)
45 #define CLKGATE_CON(n) (0x0100 + (n) * 4)
46 #define SOFTRST_CON(n) (0x0110 + (n) * 4)
47
48 static int rk3399_pmucru_match(device_t, cfdata_t, void *);
49 static void rk3399_pmucru_attach(device_t, device_t, void *);
50
51 static const struct device_compatible_entry compat_data[] = {
52 { .compat = "rockchip,rk3399-pmucru" },
53 DEVICE_COMPAT_EOL
54 };
55
56 CFATTACH_DECL_NEW(rk3399_pmucru, sizeof(struct rk_cru_softc),
57 rk3399_pmucru_match, rk3399_pmucru_attach, NULL, NULL);
58
59 static const struct rk_cru_pll_rate pll_rates[] = {
60 RK_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
61 RK_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
62 RK_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
63 RK_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0),
64 RK_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0),
65 RK_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
66 RK_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
67 RK_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
68 RK_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
69 RK_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
70 RK_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0),
71 RK_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0),
72 RK_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
73 RK_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
74 RK_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0),
75 RK_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0),
76 RK_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0),
77 RK_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
78 RK_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0),
79 RK_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0),
80 RK_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0),
81 RK_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
82 RK_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0),
83 RK_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
84 RK_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
85 RK_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
86 RK_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
87 RK_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
88 RK_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
89 RK_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
90 RK_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
91 RK_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
92 RK_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
93 RK_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
94 RK_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
95 RK_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
96 RK_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
97 RK_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
98 RK_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
99 RK_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
100 RK_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
101 RK_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
102 RK_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
103 RK_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
104 RK_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
105 RK_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
106 RK_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
107 RK_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0),
108 RK_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
109 RK_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
110 RK_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
111 RK_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
112 RK_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
113 RK_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
114 RK_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
115 RK_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
116 RK_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
117 RK_PLL_RATE( 800000000, 1, 100, 3, 1, 1, 0),
118 RK_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
119 RK_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
120 RK_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
121 RK_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
122 RK_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0),
123 RK_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0),
124 RK_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
125 RK_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
126 RK_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
127 RK_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
128 RK_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0),
129 RK_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
130 RK_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
131 RK_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0),
132 RK_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
133 RK_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0),
134 RK_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0),
135 RK_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0),
136 RK_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0),
137 };
138
139 #define PLL_CON0 0x00
140 #define PLL_FBDIV __BITS(11,0)
141
142 #define PLL_CON1 0x04
143 #define PLL_POSTDIV2 __BITS(14,12)
144 #define PLL_POSTDIV1 __BITS(10,8)
145 #define PLL_REFDIV __BITS(5,0)
146
147 #define PLL_CON2 0x08
148 #define PLL_LOCK __BIT(31)
149 #define PLL_FRACDIV __BITS(23,0)
150
151 #define PLL_CON3 0x0c
152 #define PLL_WORK_MODE __BITS(9,8)
153 #define PLL_WORK_MODE_SLOW 0
154 #define PLL_WORK_MODE_NORMAL 1
155 #define PLL_WORK_MODE_DEEP_SLOW 2
156 #define PLL_DSMPD __BIT(3)
157
158 #define PLL_WRITE_MASK 0xffff0000
159
160 static u_int
rk3399_pmucru_pll_get_rate(struct rk_cru_softc * sc,struct rk_cru_clk * clk)161 rk3399_pmucru_pll_get_rate(struct rk_cru_softc *sc,
162 struct rk_cru_clk *clk)
163 {
164 struct rk_cru_pll *pll = &clk->u.pll;
165 struct clk *clkp, *clkp_parent;
166 u_int foutvco, foutpostdiv;
167
168 KASSERT(clk->type == RK_CRU_PLL);
169
170 clkp = &clk->base;
171 clkp_parent = clk_get_parent(clkp);
172 if (clkp_parent == NULL)
173 return 0;
174
175 const u_int fref = clk_get_rate(clkp_parent);
176 if (fref == 0)
177 return 0;
178
179 const uint32_t con0 = CRU_READ(sc, pll->con_base + PLL_CON0);
180 const uint32_t con1 = CRU_READ(sc, pll->con_base + PLL_CON1);
181 const uint32_t con2 = CRU_READ(sc, pll->con_base + PLL_CON2);
182 const uint32_t con3 = CRU_READ(sc, pll->con_base + PLL_CON3);
183
184 const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV);
185 const u_int postdiv2 = __SHIFTOUT(con1, PLL_POSTDIV2);
186 const u_int postdiv1 = __SHIFTOUT(con1, PLL_POSTDIV1);
187 const u_int refdiv = __SHIFTOUT(con1, PLL_REFDIV);
188 const u_int fracdiv = __SHIFTOUT(con2, PLL_FRACDIV);
189 const u_int dsmpd = __SHIFTOUT(con3, PLL_DSMPD);
190
191 if (dsmpd == 1) {
192 /* integer mode */
193 foutvco = fref / refdiv * fbdiv;
194 } else {
195 /* fractional mode */
196 foutvco = fref / refdiv * fbdiv + ((fref * fracdiv) >> 24);
197 }
198 foutpostdiv = foutvco / postdiv1 / postdiv2;
199
200 return foutpostdiv;
201 }
202
203 static int
rk3399_pmucru_pll_set_rate(struct rk_cru_softc * sc,struct rk_cru_clk * clk,u_int rate)204 rk3399_pmucru_pll_set_rate(struct rk_cru_softc *sc,
205 struct rk_cru_clk *clk, u_int rate)
206 {
207 struct rk_cru_pll *pll = &clk->u.pll;
208 const struct rk_cru_pll_rate *pll_rate = NULL;
209 uint32_t val;
210 int retry;
211
212 KASSERT(clk->type == RK_CRU_PLL);
213
214 if (pll->rates == NULL || rate == 0)
215 return EIO;
216
217 for (int i = 0; i < pll->nrates; i++)
218 if (pll->rates[i].rate == rate) {
219 pll_rate = &pll->rates[i];
220 break;
221 }
222 if (pll_rate == NULL)
223 return EINVAL;
224
225 val = __SHIFTIN(PLL_WORK_MODE_SLOW, PLL_WORK_MODE) | (PLL_WORK_MODE << 16);
226 CRU_WRITE(sc, pll->con_base + PLL_CON3, val);
227
228 CRU_WRITE(sc, pll->con_base + PLL_CON0,
229 __SHIFTIN(pll_rate->fbdiv, PLL_FBDIV) |
230 PLL_WRITE_MASK);
231
232 CRU_WRITE(sc, pll->con_base + PLL_CON1,
233 __SHIFTIN(pll_rate->postdiv2, PLL_POSTDIV2) |
234 __SHIFTIN(pll_rate->postdiv1, PLL_POSTDIV1) |
235 __SHIFTIN(pll_rate->refdiv, PLL_REFDIV) |
236 PLL_WRITE_MASK);
237
238 val = CRU_READ(sc, pll->con_base + PLL_CON2);
239 val &= ~PLL_FRACDIV;
240 val |= __SHIFTIN(pll_rate->fracdiv, PLL_FRACDIV);
241 CRU_WRITE(sc, pll->con_base + PLL_CON2, val);
242
243 val = __SHIFTIN(pll_rate->dsmpd, PLL_DSMPD) | (PLL_DSMPD << 16);
244 CRU_WRITE(sc, pll->con_base + PLL_CON3, val);
245
246 /* Set PLL work mode to normal */
247 const uint32_t write_mask = pll->mode_mask << 16;
248 const uint32_t write_val = pll->mode_mask;
249 CRU_WRITE(sc, pll->mode_reg, write_mask | write_val);
250
251 for (retry = 1000; retry > 0; retry--) {
252 if (CRU_READ(sc, pll->con_base + PLL_CON2) & pll->lock_mask)
253 break;
254 delay(1);
255 }
256
257 if (retry == 0)
258 device_printf(sc->sc_dev, "WARNING: %s failed to lock\n",
259 clk->base.name);
260
261 val = __SHIFTIN(PLL_WORK_MODE_NORMAL, PLL_WORK_MODE) | (PLL_WORK_MODE << 16);
262 CRU_WRITE(sc, pll->con_base + PLL_CON3, val);
263
264 return 0;
265 }
266
267 #define RK3399_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \
268 { \
269 .id = (_id), \
270 .type = RK_CRU_PLL, \
271 .base.name = (_name), \
272 .base.flags = 0, \
273 .u.pll.parents = (_parents), \
274 .u.pll.nparents = __arraycount(_parents), \
275 .u.pll.con_base = (_con_base), \
276 .u.pll.mode_reg = (_mode_reg), \
277 .u.pll.mode_mask = (_mode_mask), \
278 .u.pll.lock_mask = (_lock_mask), \
279 .u.pll.rates = (_rates), \
280 .u.pll.nrates = __arraycount(_rates), \
281 .get_rate = rk3399_pmucru_pll_get_rate, \
282 .set_rate = rk3399_pmucru_pll_set_rate, \
283 .get_parent = rk_cru_pll_get_parent, \
284 }
285
286 static const char * pll_parents[] = { "xin24m", "xin32k" };
287
288 static struct rk_cru_clk rk3399_pmucru_clks[] = {
289 RK3399_PLL(RK3399_PLL_PPLL, "ppll", pll_parents,
290 PLL_CON(0), /* con_base */
291 PLL_CON(3), /* mode_reg */
292 __BIT(8), /* mode_mask */
293 __BIT(31), /* lock_mask */
294 pll_rates),
295
296 RK_COMPOSITE_NOMUX(RK3399_SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll",
297 CLKSEL_CON(2), /* div_reg */
298 __BITS(6,0), /* div_mask */
299 CLKGATE_CON(0), /* gate_reg */
300 __BIT(9), /* gate_mask */
301 0),
302 RK_COMPOSITE_NOMUX(RK3399_SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll",
303 CLKSEL_CON(3), /* div_reg */
304 __BITS(6,0), /* div_mask */
305 CLKGATE_CON(0), /* gate_reg */
306 __BIT(10), /* gate_mask */
307 0),
308 RK_COMPOSITE_NOMUX(RK3399_SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll",
309 CLKSEL_CON(2), /* div_reg */
310 __BITS(14,8), /* div_mask */
311 CLKGATE_CON(0), /* gate_reg */
312 __BIT(11), /* gate_mask */
313 0),
314
315 RK_DIV(RK3399_PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLKSEL_CON(0), __BITS(4,0), 0),
316
317 RK_GATE(RK3399_PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLKGATE_CON(1), 0),
318 RK_GATE(RK3399_PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", CLKGATE_CON(1), 3),
319 RK_GATE(RK3399_PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", CLKGATE_CON(1), 4),
320 RK_GATE(RK3399_PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", CLKGATE_CON(1), 7),
321 RK_GATE(RK3399_PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", CLKGATE_CON(1), 8),
322 RK_GATE(RK3399_PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", CLKGATE_CON(1), 9),
323 RK_GATE(RK3399_PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", CLKGATE_CON(1), 10),
324 };
325
326 static int
rk3399_pmucru_match(device_t parent,cfdata_t cf,void * aux)327 rk3399_pmucru_match(device_t parent, cfdata_t cf, void *aux)
328 {
329 struct fdt_attach_args * const faa = aux;
330
331 return of_compatible_match(faa->faa_phandle, compat_data);
332 }
333
334 static void
rk3399_pmucru_attach(device_t parent,device_t self,void * aux)335 rk3399_pmucru_attach(device_t parent, device_t self, void *aux)
336 {
337 struct rk_cru_softc * const sc = device_private(self);
338 struct fdt_attach_args * const faa = aux;
339
340 sc->sc_dev = self;
341 sc->sc_phandle = faa->faa_phandle;
342 sc->sc_bst = faa->faa_bst;
343
344 sc->sc_clks = rk3399_pmucru_clks;
345 sc->sc_nclks = __arraycount(rk3399_pmucru_clks);
346
347 sc->sc_softrst_base = SOFTRST_CON(0);
348
349 if (rk_cru_attach(sc) != 0)
350 return;
351
352 aprint_naive("\n");
353 aprint_normal(": RK3399 PMU CRU\n");
354
355 rk_cru_print(sc);
356 }
357