1 /* $NetBSD: bcm2835_gpio.c,v 1.24 2022/01/17 19:38:14 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2013, 2014, 2017 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jonathan A. Kollasch, Frank Kardel and Nick Hudson
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: bcm2835_gpio.c,v 1.24 2022/01/17 19:38:14 thorpej Exp $");
34
35 /*
36 * Driver for BCM2835 GPIO
37 *
38 * see: http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
39 */
40
41 #include <sys/param.h>
42 #include <sys/device.h>
43 #include <sys/systm.h>
44 #include <sys/mutex.h>
45 #include <sys/bus.h>
46 #include <sys/intr.h>
47 #include <sys/kernel.h>
48 #include <sys/kmem.h>
49 #include <sys/proc.h>
50 #include <sys/gpio.h>
51
52 #include <sys/bitops.h>
53
54 #include <arm/broadcom/bcm2835reg.h>
55 #include <arm/broadcom/bcm2835_gpioreg.h>
56
57 #include <dev/gpio/gpiovar.h>
58 #include <dev/fdt/fdtvar.h>
59
60 /* #define BCM2835_GPIO_DEBUG */
61 #ifdef BCM2835_GPIO_DEBUG
62 int bcm2835gpiodebug = 3;
63 #define DPRINTF(l, x) do { if (l <= bcm2835gpiodebug) { printf x; } } while (0)
64 #else
65 #define DPRINTF(l, x)
66 #endif
67
68 #define BCM2835_GPIO_MAXPINS 54
69 #define BCM2838_GPIO_MAXPINS 58
70 #define BCMGPIO_MAXPINS BCM2838_GPIO_MAXPINS
71
72 struct bcmgpio_eint {
73 int (*eint_func)(void *);
74 void *eint_arg;
75 int eint_flags;
76 int eint_bank;
77 int eint_num;
78 };
79
80 #define BCMGPIO_INTR_POS_EDGE 0x01
81 #define BCMGPIO_INTR_NEG_EDGE 0x02
82 #define BCMGPIO_INTR_HIGH_LEVEL 0x04
83 #define BCMGPIO_INTR_LOW_LEVEL 0x08
84 #define BCMGPIO_INTR_MPSAFE 0x10
85
86 struct bcmgpio_softc;
87 struct bcmgpio_bank {
88 struct bcmgpio_softc *sc_bcm;
89 void *sc_ih;
90 struct bcmgpio_eint sc_eint[32];
91 int sc_bankno;
92 };
93 #define BCMGPIO_NBANKS 2
94
95 struct bcmgpio_softc {
96 device_t sc_dev;
97 bus_space_tag_t sc_iot;
98 bus_space_handle_t sc_ioh;
99 struct gpio_chipset_tag sc_gpio_gc;
100
101 kmutex_t sc_lock;
102 gpio_pin_t sc_gpio_pins[BCMGPIO_MAXPINS];
103
104 /* For interrupt support. */
105 struct bcmgpio_bank sc_banks[BCMGPIO_NBANKS];
106
107 bool sc_is2835; /* for pullup on 2711 */
108 u_int sc_maxpins;
109 };
110
111 struct bcmgpio_pin {
112 int pin_no;
113 u_int pin_flags;
114 bool pin_actlo;
115 };
116
117
118 static int bcmgpio_match(device_t, cfdata_t, void *);
119 static void bcmgpio_attach(device_t, device_t, void *);
120
121 static int bcm2835gpio_gpio_pin_read(void *, int);
122 static void bcm2835gpio_gpio_pin_write(void *, int, int);
123 static void bcm2835gpio_gpio_pin_ctl(void *, int, int);
124
125 static void * bcmgpio_gpio_intr_establish(void *, int, int, int,
126 int (*)(void *), void *);
127 static void bcmgpio_gpio_intr_disestablish(void *, void *);
128 static bool bcmgpio_gpio_intrstr(void *, int, int, char *, size_t);
129
130 static int bcmgpio_intr(void *);
131
132 u_int bcm283x_pin_getfunc(const struct bcmgpio_softc * const, u_int);
133 void bcm283x_pin_setfunc(const struct bcmgpio_softc * const, u_int,
134 u_int);
135 void bcm283x_pin_setpull(const struct bcmgpio_softc * const, u_int,
136 u_int);
137
138 static int bcm283x_pinctrl_set_config(device_t, const void *, size_t);
139
140 static void * bcmgpio_fdt_acquire(device_t, const void *, size_t, int);
141 static void bcmgpio_fdt_release(device_t, void *);
142 static int bcmgpio_fdt_read(device_t, void *, bool);
143 static void bcmgpio_fdt_write(device_t, void *, int, bool);
144
145 static struct fdtbus_gpio_controller_func bcmgpio_funcs = {
146 .acquire = bcmgpio_fdt_acquire,
147 .release = bcmgpio_fdt_release,
148 .read = bcmgpio_fdt_read,
149 .write = bcmgpio_fdt_write
150 };
151
152 static void * bcmgpio_fdt_intr_establish(device_t, u_int *, int, int,
153 int (*func)(void *), void *, const char *);
154 static void bcmgpio_fdt_intr_disestablish(device_t, void *);
155 static bool bcmgpio_fdt_intrstr(device_t, u_int *, char *, size_t);
156
157 static struct fdtbus_interrupt_controller_func bcmgpio_fdt_intrfuncs = {
158 .establish = bcmgpio_fdt_intr_establish,
159 .disestablish = bcmgpio_fdt_intr_disestablish,
160 .intrstr = bcmgpio_fdt_intrstr,
161 };
162
163 CFATTACH_DECL_NEW(bcmgpio, sizeof(struct bcmgpio_softc),
164 bcmgpio_match, bcmgpio_attach, NULL, NULL);
165
166
167 static struct fdtbus_pinctrl_controller_func bcm283x_pinctrl_funcs = {
168 .set_config = bcm283x_pinctrl_set_config,
169 };
170
171 static int
bcm283x_pinctrl_set_config(device_t dev,const void * data,size_t len)172 bcm283x_pinctrl_set_config(device_t dev, const void *data, size_t len)
173 {
174 struct bcmgpio_softc * const sc = device_private(dev);
175
176 if (len != 4)
177 return -1;
178
179 const int phandle = fdtbus_get_phandle_from_native(be32dec(data));
180
181 /*
182 * Required: brcm,pins
183 * Optional: brcm,function, brcm,pull
184 */
185
186 int pins_len;
187 const u_int *pins = fdtbus_get_prop(phandle, "brcm,pins", &pins_len);
188
189 if (pins == NULL)
190 return -1;
191
192 int pull_len = 0;
193 const u_int *pull = fdtbus_get_prop(phandle, "brcm,pull", &pull_len);
194
195 int func_len = 0;
196 const u_int *func = fdtbus_get_prop(phandle, "brcm,function", &func_len);
197
198 if (!pull && !func) {
199 aprint_error_dev(dev, "one of brcm,pull or brcm,function must "
200 "be specified");
201 return -1;
202 }
203
204 const int npins = pins_len / 4;
205 const int npull = pull_len / 4;
206 const int nfunc = func_len / 4;
207
208 if (npull > 1 && npull != npins) {
209 aprint_error_dev(dev, "brcm,pull must have 1 or %d entries",
210 npins);
211 return -1;
212 }
213 if (nfunc > 1 && nfunc != npins) {
214 aprint_error_dev(dev, "brcm,function must have 1 or %d entries",
215 npins);
216 return -1;
217 }
218
219 mutex_enter(&sc->sc_lock);
220
221 for (int i = 0; i < npins; i++) {
222 const u_int pin = be32toh(pins[i]);
223
224 if (pin >= sc->sc_maxpins)
225 continue;
226 if (pull) {
227 const int value = be32toh(pull[npull == 1 ? 0 : i]);
228 bcm283x_pin_setpull(sc, pin, value);
229 }
230 if (func) {
231 const int value = be32toh(func[nfunc == 1 ? 0 : i]);
232 bcm283x_pin_setfunc(sc, pin, value);
233 }
234 }
235
236 mutex_exit(&sc->sc_lock);
237
238 return 0;
239 }
240
241 static const struct device_compatible_entry compat_data[] = {
242 { .compat = "brcm,bcm2835-gpio" },
243 { .compat = "brcm,bcm2838-gpio" },
244 { .compat = "brcm,bcm2711-gpio" },
245 DEVICE_COMPAT_EOL
246 };
247
248 static int
bcmgpio_match(device_t parent,cfdata_t cf,void * aux)249 bcmgpio_match(device_t parent, cfdata_t cf, void *aux)
250 {
251 struct fdt_attach_args * const faa = aux;
252
253 return of_compatible_match(faa->faa_phandle, compat_data);
254 }
255
256 static void
bcmgpio_attach(device_t parent,device_t self,void * aux)257 bcmgpio_attach(device_t parent, device_t self, void *aux)
258 {
259 struct bcmgpio_softc * const sc = device_private(self);
260 struct fdt_attach_args * const faa = aux;
261 struct gpiobus_attach_args gba;
262 bus_addr_t addr;
263 bus_size_t size;
264 u_int func;
265 int error;
266 int pin;
267 int bank;
268 uint32_t reg;
269
270 const int phandle = faa->faa_phandle;
271 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
272 aprint_error(": couldn't get registers\n");
273 return;
274 }
275
276 sc->sc_dev = self;
277
278 sc->sc_iot = faa->faa_bst;
279 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh);
280 if (error) {
281 aprint_error_dev(self, ": couldn't map registers\n");
282 return;
283 }
284
285 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
286
287 /* BCM2835, BCM2836, BCM2837 return 'gpio' in this unused register */
288 reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BCM2838_GPIO_GPPUPPDN(3));
289 sc->sc_is2835 = reg == 0x6770696f;
290 sc->sc_maxpins = sc->sc_is2835 ? BCM2835_GPIO_MAXPINS
291 : BCM2838_GPIO_MAXPINS;
292
293 aprint_naive("\n");
294 aprint_normal(": GPIO controller %s\n", sc->sc_is2835 ? "2835" : "2838");
295
296 for (pin = 0; pin < sc->sc_maxpins; pin++) {
297 sc->sc_gpio_pins[pin].pin_num = pin;
298 /*
299 * find out pins still available for GPIO
300 */
301 func = bcm283x_pin_getfunc(sc, pin);
302
303 if (func == BCM2835_GPIO_IN ||
304 func == BCM2835_GPIO_OUT) {
305 /* XXX TRISTATE? Really? */
306 sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT |
307 GPIO_PIN_OUTPUT |
308 GPIO_PIN_PUSHPULL | GPIO_PIN_TRISTATE |
309 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN |
310 GPIO_PIN_ALT0 | GPIO_PIN_ALT1 |
311 GPIO_PIN_ALT2 | GPIO_PIN_ALT3 |
312 GPIO_PIN_ALT4 | GPIO_PIN_ALT5;
313 sc->sc_gpio_pins[pin].pin_intrcaps =
314 GPIO_INTR_POS_EDGE |
315 GPIO_INTR_NEG_EDGE |
316 GPIO_INTR_DOUBLE_EDGE |
317 GPIO_INTR_HIGH_LEVEL |
318 GPIO_INTR_LOW_LEVEL |
319 GPIO_INTR_MPSAFE;
320 /* read initial state */
321 sc->sc_gpio_pins[pin].pin_state =
322 bcm2835gpio_gpio_pin_read(sc, pin);
323 aprint_debug_dev(sc->sc_dev, "attach pin %d\n", pin);
324 } else {
325 sc->sc_gpio_pins[pin].pin_caps = 0;
326 sc->sc_gpio_pins[pin].pin_state = 0;
327 aprint_debug_dev(sc->sc_dev, "skip pin %d - func = %x\n", pin, func);
328 }
329 }
330
331 /* Initialize interrupts. */
332 for (bank = 0; bank < BCMGPIO_NBANKS; bank++) {
333 char intrstr[128];
334
335 if (!fdtbus_intr_str(phandle, bank, intrstr, sizeof(intrstr))) {
336 aprint_error_dev(self, "failed to decode interrupt\n");
337 continue;
338 }
339
340 char xname[16];
341 snprintf(xname, sizeof(xname), "%s #%u", device_xname(self),
342 bank);
343 sc->sc_banks[bank].sc_bankno = bank;
344 sc->sc_banks[bank].sc_bcm = sc;
345 sc->sc_banks[bank].sc_ih = fdtbus_intr_establish_xname(phandle,
346 bank, IPL_VM, FDT_INTR_MPSAFE, bcmgpio_intr,
347 &sc->sc_banks[bank], xname);
348 if (sc->sc_banks[bank].sc_ih) {
349 aprint_normal_dev(self,
350 "pins %d..%d interrupting on %s\n",
351 bank * 32,
352 MIN((bank * 32) + 31, sc->sc_maxpins),
353 intrstr);
354 } else {
355 aprint_error_dev(self,
356 "failed to establish interrupt for pins %d..%d\n",
357 bank * 32,
358 MIN((bank * 32) + 31, sc->sc_maxpins));
359 }
360 }
361
362 fdtbus_register_gpio_controller(self, faa->faa_phandle, &bcmgpio_funcs);
363
364 for (int child = OF_child(phandle); child; child = OF_peer(child)) {
365 if (!of_hasprop(child, "brcm,pins"))
366 continue;
367 fdtbus_register_pinctrl_config(self, child,
368 &bcm283x_pinctrl_funcs);
369 }
370
371 fdtbus_register_interrupt_controller(self, phandle,
372 &bcmgpio_fdt_intrfuncs);
373
374 /* create controller tag */
375 sc->sc_gpio_gc.gp_cookie = sc;
376 sc->sc_gpio_gc.gp_pin_read = bcm2835gpio_gpio_pin_read;
377 sc->sc_gpio_gc.gp_pin_write = bcm2835gpio_gpio_pin_write;
378 sc->sc_gpio_gc.gp_pin_ctl = bcm2835gpio_gpio_pin_ctl;
379 sc->sc_gpio_gc.gp_intr_establish = bcmgpio_gpio_intr_establish;
380 sc->sc_gpio_gc.gp_intr_disestablish = bcmgpio_gpio_intr_disestablish;
381 sc->sc_gpio_gc.gp_intr_str = bcmgpio_gpio_intrstr;
382
383 gba.gba_gc = &sc->sc_gpio_gc;
384 gba.gba_pins = &sc->sc_gpio_pins[0];
385 gba.gba_npins = sc->sc_maxpins;
386 config_found(self, &gba, gpiobus_print,
387 CFARGS(.devhandle = device_handle(self)));
388 }
389
390 /* GPIO interrupt support functions */
391
392 static int
bcmgpio_intr(void * arg)393 bcmgpio_intr(void *arg)
394 {
395 struct bcmgpio_bank * const b = arg;
396 struct bcmgpio_softc * const sc = b->sc_bcm;
397 struct bcmgpio_eint *eint;
398 uint32_t status, pending, bit;
399 uint32_t clear_level;
400 int (*func)(void *);
401 int rv = 0;
402
403 for (;;) {
404 status = pending = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
405 BCM2835_GPIO_GPEDS(b->sc_bankno));
406 if (status == 0)
407 break;
408
409 /*
410 * This will clear the indicator for any pending
411 * edge-triggered pins, but level-triggered pins
412 * will still be indicated until the pin is
413 * de-asserted. We'll have to clear level-triggered
414 * indicators below.
415 */
416 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
417 BCM2835_GPIO_GPEDS(b->sc_bankno), status);
418 clear_level = 0;
419
420 while ((bit = ffs32(pending)) != 0) {
421 pending &= ~__BIT(bit - 1);
422 eint = &b->sc_eint[bit - 1];
423 if ((func = eint->eint_func) == NULL)
424 continue;
425 if (eint->eint_flags & (BCMGPIO_INTR_HIGH_LEVEL |
426 BCMGPIO_INTR_LOW_LEVEL))
427 clear_level |= __BIT(bit - 1);
428 const bool mpsafe =
429 (eint->eint_flags & BCMGPIO_INTR_MPSAFE) != 0;
430 if (!mpsafe)
431 KERNEL_LOCK(1, curlwp);
432 rv |= (*func)(eint->eint_arg);
433 if (!mpsafe)
434 KERNEL_UNLOCK_ONE(curlwp);
435 }
436
437 /*
438 * Now that all of the handlers have been called,
439 * we can clear the indicators for any level-triggered
440 * pins.
441 */
442 if (clear_level)
443 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
444 BCM2835_GPIO_GPEDS(b->sc_bankno), clear_level);
445 }
446
447 return (rv);
448 }
449
450 static void *
bmcgpio_intr_enable(struct bcmgpio_softc * sc,int (* func)(void *),void * arg,int bank,int pin,int flags)451 bmcgpio_intr_enable(struct bcmgpio_softc *sc, int (*func)(void *), void *arg,
452 int bank, int pin, int flags)
453 {
454 struct bcmgpio_eint *eint;
455 uint32_t mask, enabled_ren, enabled_fen, enabled_hen, enabled_len;
456 int has_edge = flags & (BCMGPIO_INTR_POS_EDGE|BCMGPIO_INTR_NEG_EDGE);
457 int has_level = flags &
458 (BCMGPIO_INTR_HIGH_LEVEL|BCMGPIO_INTR_LOW_LEVEL);
459
460 if (bank < 0 || bank >= BCMGPIO_NBANKS)
461 return NULL;
462 if (pin < 0 || pin >= 32)
463 return (NULL);
464
465 /* Must specify a mode. */
466 if (!has_edge && !has_level)
467 return (NULL);
468
469 /* Can't have HIGH and LOW together. */
470 if (has_level == (BCMGPIO_INTR_HIGH_LEVEL|BCMGPIO_INTR_LOW_LEVEL))
471 return (NULL);
472
473 /* Can't have EDGE and LEVEL together. */
474 if (has_edge && has_level)
475 return (NULL);
476
477 eint = &sc->sc_banks[bank].sc_eint[pin];
478
479 mask = __BIT(pin);
480
481 mutex_enter(&sc->sc_lock);
482
483 if (eint->eint_func != NULL) {
484 mutex_exit(&sc->sc_lock);
485 return (NULL); /* in use */
486 }
487
488 eint->eint_func = func;
489 eint->eint_arg = arg;
490 eint->eint_flags = flags;
491 eint->eint_bank = bank;
492 eint->eint_num = pin;
493
494 enabled_ren = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
495 BCM2835_GPIO_GPREN(bank));
496 enabled_fen = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
497 BCM2835_GPIO_GPFEN(bank));
498 enabled_hen = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
499 BCM2835_GPIO_GPHEN(bank));
500 enabled_len = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
501 BCM2835_GPIO_GPLEN(bank));
502
503 enabled_ren &= ~mask;
504 enabled_fen &= ~mask;
505 enabled_hen &= ~mask;
506 enabled_len &= ~mask;
507
508 if (flags & BCMGPIO_INTR_POS_EDGE)
509 enabled_ren |= mask;
510 if (flags & BCMGPIO_INTR_NEG_EDGE)
511 enabled_fen |= mask;
512 if (flags & BCMGPIO_INTR_HIGH_LEVEL)
513 enabled_hen |= mask;
514 if (flags & BCMGPIO_INTR_LOW_LEVEL)
515 enabled_len |= mask;
516
517 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
518 BCM2835_GPIO_GPREN(bank), enabled_ren);
519 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
520 BCM2835_GPIO_GPFEN(bank), enabled_fen);
521 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
522 BCM2835_GPIO_GPHEN(bank), enabled_hen);
523 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
524 BCM2835_GPIO_GPLEN(bank), enabled_len);
525
526 mutex_exit(&sc->sc_lock);
527 return (eint);
528 }
529
530 static void
bcmgpio_intr_disable(struct bcmgpio_softc * sc,struct bcmgpio_eint * eint)531 bcmgpio_intr_disable(struct bcmgpio_softc *sc, struct bcmgpio_eint *eint)
532 {
533 uint32_t mask, enabled_ren, enabled_fen, enabled_hen, enabled_len;
534 int bank = eint->eint_bank;
535
536 mask = __BIT(eint->eint_num);
537
538 KASSERT(eint->eint_func != NULL);
539
540 mutex_enter(&sc->sc_lock);
541
542 enabled_ren = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
543 BCM2835_GPIO_GPREN(bank));
544 enabled_fen = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
545 BCM2835_GPIO_GPFEN(bank));
546 enabled_hen = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
547 BCM2835_GPIO_GPHEN(bank));
548 enabled_len = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
549 BCM2835_GPIO_GPLEN(bank));
550
551 enabled_ren &= ~mask;
552 enabled_fen &= ~mask;
553 enabled_hen &= ~mask;
554 enabled_len &= ~mask;
555
556 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
557 BCM2835_GPIO_GPREN(bank), enabled_ren);
558 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
559 BCM2835_GPIO_GPFEN(bank), enabled_fen);
560 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
561 BCM2835_GPIO_GPHEN(bank), enabled_hen);
562 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
563 BCM2835_GPIO_GPLEN(bank), enabled_len);
564
565 eint->eint_func = NULL;
566 eint->eint_arg = NULL;
567 eint->eint_flags = 0;
568
569 mutex_exit(&sc->sc_lock);
570 }
571
572 static void *
bcmgpio_fdt_intr_establish(device_t dev,u_int * specifier,int ipl,int flags,int (* func)(void *),void * arg,const char * xname)573 bcmgpio_fdt_intr_establish(device_t dev, u_int *specifier, int ipl, int flags,
574 int (*func)(void *), void *arg, const char *xname)
575 {
576 struct bcmgpio_softc * const sc = device_private(dev);
577 int eint_flags = (flags & FDT_INTR_MPSAFE) ? BCMGPIO_INTR_MPSAFE : 0;
578
579 if (ipl != IPL_VM) {
580 aprint_error_dev(dev, "%s: wrong IPL %d (expected %d)\n",
581 __func__, ipl, IPL_VM);
582 return (NULL);
583 }
584
585 /* 1st cell is the GPIO number */
586 /* 2nd cell is flags */
587 const u_int bank = be32toh(specifier[0]) / 32;
588 const u_int pin = be32toh(specifier[0]) % 32;
589 const u_int type = be32toh(specifier[1]) & 0xf;
590
591 switch (type) {
592 case FDT_INTR_TYPE_POS_EDGE:
593 eint_flags |= BCMGPIO_INTR_POS_EDGE;
594 break;
595 case FDT_INTR_TYPE_NEG_EDGE:
596 eint_flags |= BCMGPIO_INTR_NEG_EDGE;
597 break;
598 case FDT_INTR_TYPE_DOUBLE_EDGE:
599 eint_flags |= BCMGPIO_INTR_POS_EDGE | BCMGPIO_INTR_NEG_EDGE;
600 break;
601 case FDT_INTR_TYPE_HIGH_LEVEL:
602 eint_flags |= BCMGPIO_INTR_HIGH_LEVEL;
603 break;
604 case FDT_INTR_TYPE_LOW_LEVEL:
605 eint_flags |= BCMGPIO_INTR_LOW_LEVEL;
606 break;
607 default:
608 aprint_error_dev(dev, "%s: unsupported irq type 0x%x\n",
609 __func__, type);
610 return (NULL);
611 }
612
613 return (bmcgpio_intr_enable(sc, func, arg, bank, pin, eint_flags));
614 }
615
616 static void
bcmgpio_fdt_intr_disestablish(device_t dev,void * ih)617 bcmgpio_fdt_intr_disestablish(device_t dev, void *ih)
618 {
619 struct bcmgpio_softc * const sc = device_private(dev);
620 struct bcmgpio_eint * const eint = ih;
621
622 bcmgpio_intr_disable(sc, eint);
623 }
624
625 static void *
bcmgpio_gpio_intr_establish(void * vsc,int pin,int ipl,int irqmode,int (* func)(void *),void * arg)626 bcmgpio_gpio_intr_establish(void *vsc, int pin, int ipl, int irqmode,
627 int (*func)(void *), void *arg)
628 {
629 struct bcmgpio_softc * const sc = vsc;
630 int eint_flags = (irqmode & GPIO_INTR_MPSAFE) ? BCMGPIO_INTR_MPSAFE : 0;
631 int bank = pin / 32;
632 int type = irqmode & GPIO_INTR_MODE_MASK;
633
634 pin %= 32;
635
636 if (ipl != IPL_VM) {
637 aprint_error_dev(sc->sc_dev, "%s: wrong IPL %d (expected %d)\n",
638 __func__, ipl, IPL_VM);
639 return (NULL);
640 }
641
642 switch (type) {
643 case GPIO_INTR_POS_EDGE:
644 eint_flags |= BCMGPIO_INTR_POS_EDGE;
645 break;
646 case GPIO_INTR_NEG_EDGE:
647 eint_flags |= BCMGPIO_INTR_NEG_EDGE;
648 break;
649 case GPIO_INTR_DOUBLE_EDGE:
650 eint_flags |= BCMGPIO_INTR_POS_EDGE | BCMGPIO_INTR_NEG_EDGE;
651 break;
652 case GPIO_INTR_HIGH_LEVEL:
653 eint_flags |= BCMGPIO_INTR_HIGH_LEVEL;
654 break;
655 case GPIO_INTR_LOW_LEVEL:
656 eint_flags |= BCMGPIO_INTR_LOW_LEVEL;
657 break;
658 default:
659 aprint_error_dev(sc->sc_dev, "%s: unsupported irq type 0x%x\n",
660 __func__, type);
661 return (NULL);
662 }
663
664 return (bmcgpio_intr_enable(sc, func, arg, bank, pin, eint_flags));
665 }
666
667 static void
bcmgpio_gpio_intr_disestablish(void * vsc,void * ih)668 bcmgpio_gpio_intr_disestablish(void *vsc, void *ih)
669 {
670 struct bcmgpio_softc * const sc = vsc;
671 struct bcmgpio_eint * const eint = ih;
672
673 bcmgpio_intr_disable(sc, eint);
674 }
675
676 static bool
bcmgpio_gpio_intrstr(void * vsc,int pin,int irqmode,char * buf,size_t buflen)677 bcmgpio_gpio_intrstr(void *vsc, int pin, int irqmode, char *buf, size_t buflen)
678 {
679 struct bcmgpio_softc * const sc = vsc;
680
681 if (pin < 0 || pin >= sc->sc_maxpins)
682 return (false);
683
684 snprintf(buf, buflen, "GPIO %d", pin);
685
686 return (true);
687 }
688
689 static bool
bcmgpio_fdt_intrstr(device_t dev,u_int * specifier,char * buf,size_t buflen)690 bcmgpio_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen)
691 {
692
693 /* 1st cell is the GPIO number */
694 /* 2nd cell is flags */
695 if (!specifier)
696 return (false);
697 const u_int bank = be32toh(specifier[0]) / 32;
698 const u_int pin = be32toh(specifier[0]) % 32;
699 const u_int type = be32toh(specifier[1]) & 0xf;
700 char const* typestr;
701
702 if (bank >= BCMGPIO_NBANKS)
703 return (false);
704 switch (type) {
705 case FDT_INTR_TYPE_DOUBLE_EDGE:
706 typestr = "double edge";
707 break;
708 case FDT_INTR_TYPE_POS_EDGE:
709 typestr = "positive edge";
710 break;
711 case FDT_INTR_TYPE_NEG_EDGE:
712 typestr = "negative edge";
713 break;
714 case FDT_INTR_TYPE_HIGH_LEVEL:
715 typestr = "high level";
716 break;
717 case FDT_INTR_TYPE_LOW_LEVEL:
718 typestr = "low level";
719 break;
720 default:
721 aprint_error_dev(dev, "%s: unsupported irq type 0x%x\n",
722 __func__, type);
723
724 return (false);
725 }
726
727 snprintf(buf, buflen, "GPIO %u (%s)", (bank * 32) + pin, typestr);
728
729 return (true);
730 }
731
732 /* GPIO support functions */
733 static int
bcm2835gpio_gpio_pin_read(void * arg,int pin)734 bcm2835gpio_gpio_pin_read(void *arg, int pin)
735 {
736 struct bcmgpio_softc *sc = arg;
737 uint32_t val;
738 int res;
739
740 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
741 BCM2835_GPIO_GPLEV(pin / BCM2835_GPIO_GPLEV_PINS_PER_REGISTER));
742
743 res = val & (1 << (pin % BCM2835_GPIO_GPLEV_PINS_PER_REGISTER)) ?
744 GPIO_PIN_HIGH : GPIO_PIN_LOW;
745
746 DPRINTF(2, ("%s: gpio_read pin %d->%d\n", device_xname(sc->sc_dev),
747 pin, (res == GPIO_PIN_HIGH)));
748
749 return res;
750 }
751
752 static void
bcm2835gpio_gpio_pin_write(void * arg,int pin,int value)753 bcm2835gpio_gpio_pin_write(void *arg, int pin, int value)
754 {
755 struct bcmgpio_softc *sc = arg;
756 bus_size_t reg;
757
758 if (value == GPIO_PIN_HIGH) {
759 reg = BCM2835_GPIO_GPSET(pin / BCM2835_GPIO_GPSET_PINS_PER_REGISTER);
760 } else {
761 reg = BCM2835_GPIO_GPCLR(pin / BCM2835_GPIO_GPCLR_PINS_PER_REGISTER);
762 }
763
764 bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg,
765 1 << (pin % BCM2835_GPIO_GPSET_PINS_PER_REGISTER));
766
767 DPRINTF(2, ("%s: gpio_write pin %d<-%d\n", device_xname(sc->sc_dev),
768 pin, (value == GPIO_PIN_HIGH)));
769 }
770
771
772 void
bcm283x_pin_setfunc(const struct bcmgpio_softc * const sc,u_int pin,u_int func)773 bcm283x_pin_setfunc(const struct bcmgpio_softc * const sc, u_int pin,
774 u_int func)
775 {
776 const u_int mask = (1 << BCM2835_GPIO_GPFSEL_BITS_PER_PIN) - 1;
777 const u_int regid = (pin / BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER);
778 const u_int shift = (pin % BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER) *
779 BCM2835_GPIO_GPFSEL_BITS_PER_PIN;
780 uint32_t v;
781
782 KASSERT(mutex_owned(&sc->sc_lock));
783 KASSERT(func <= mask);
784
785 v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPFSEL(regid));
786
787 if (((v >> shift) & mask) == func) {
788 return;
789 }
790
791 DPRINTF(2, ("%s: gpio_write pin %d<-%d\n", device_xname(sc->sc_dev),
792 pin, func));
793
794 v &= ~(mask << shift);
795 v |= (func << shift);
796
797 bus_space_write_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPFSEL(regid), v);
798 }
799
800 u_int
bcm283x_pin_getfunc(const struct bcmgpio_softc * const sc,u_int pin)801 bcm283x_pin_getfunc(const struct bcmgpio_softc * const sc, u_int pin)
802 {
803 const u_int mask = (1 << BCM2835_GPIO_GPFSEL_BITS_PER_PIN) - 1;
804 const u_int regid = (pin / BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER);
805 const u_int shift = (pin % BCM2835_GPIO_GPFSEL_PINS_PER_REGISTER) *
806 BCM2835_GPIO_GPFSEL_BITS_PER_PIN;
807 uint32_t v;
808
809 v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BCM2835_GPIO_GPFSEL(regid));
810
811 return ((v >> shift) & mask);
812 }
813
814 void
bcm283x_pin_setpull(const struct bcmgpio_softc * const sc,u_int pin,u_int pud)815 bcm283x_pin_setpull(const struct bcmgpio_softc * const sc, u_int pin, u_int pud)
816 {
817
818 KASSERT(mutex_owned(&sc->sc_lock));
819
820 u_int mask, regid;
821 uint32_t reg;
822
823 if (sc->sc_is2835) {
824 mask = 1 << (pin % BCM2835_GPIO_GPPUD_PINS_PER_REGISTER);
825 regid = (pin / BCM2835_GPIO_GPPUD_PINS_PER_REGISTER);
826
827 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
828 BCM2835_GPIO_GPPUD, pud);
829 delay(1);
830 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
831 BCM2835_GPIO_GPPUDCLK(regid), mask);
832 delay(1);
833 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
834 BCM2835_GPIO_GPPUD, 0);
835 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
836 BCM2835_GPIO_GPPUDCLK(regid), 0);
837 } else {
838 mask = BCM2838_GPIO_GPPUD_MASK(pin);
839 regid = BCM2838_GPIO_GPPUD_REGID(pin);
840
841 switch (pud) {
842 case BCM2835_GPIO_GPPUD_PULLUP:
843 pud = BCM2838_GPIO_GPPUD_PULLUP;
844 break;
845 case BCM2835_GPIO_GPPUD_PULLDOWN:
846 pud = BCM2838_GPIO_GPPUD_PULLDOWN;
847 break;
848 default:
849 pud = BCM2838_GPIO_GPPUD_PULLOFF;
850 break;
851 }
852
853 reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
854 BCM2838_GPIO_GPPUPPDN(regid));
855 reg &= ~mask;
856 reg |= __SHIFTIN(pud, mask);
857 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
858 BCM2838_GPIO_GPPUPPDN(regid), reg);
859 }
860 }
861
862
863 static void
bcm2835gpio_gpio_pin_ctl(void * arg,int pin,int flags)864 bcm2835gpio_gpio_pin_ctl(void *arg, int pin, int flags)
865 {
866 struct bcmgpio_softc *sc = arg;
867 uint32_t cmd;
868 uint32_t altmask = GPIO_PIN_ALT0 | GPIO_PIN_ALT1 |
869 GPIO_PIN_ALT2 | GPIO_PIN_ALT3 |
870 GPIO_PIN_ALT4 | GPIO_PIN_ALT5;
871
872 DPRINTF(2, ("%s: gpio_ctl pin %d flags 0x%x\n", device_xname(sc->sc_dev), pin, flags));
873
874 mutex_enter(&sc->sc_lock);
875 if (flags & (GPIO_PIN_OUTPUT|GPIO_PIN_INPUT)) {
876 if ((flags & GPIO_PIN_INPUT) != 0) {
877 /* for safety INPUT will override output */
878 bcm283x_pin_setfunc(sc, pin, BCM2835_GPIO_IN);
879 } else {
880 bcm283x_pin_setfunc(sc, pin, BCM2835_GPIO_OUT);
881 }
882 } else if ((flags & altmask) != 0) {
883 u_int func;
884
885 switch (flags & altmask) {
886 case GPIO_PIN_ALT0:
887 func = BCM2835_GPIO_ALT0;
888 break;
889 case GPIO_PIN_ALT1:
890 func = BCM2835_GPIO_ALT1;
891 break;
892 case GPIO_PIN_ALT2:
893 func = BCM2835_GPIO_ALT2;
894 break;
895 case GPIO_PIN_ALT3:
896 func = BCM2835_GPIO_ALT3;
897 break;
898 case GPIO_PIN_ALT4:
899 func = BCM2835_GPIO_ALT4;
900 break;
901 case GPIO_PIN_ALT5:
902 func = BCM2835_GPIO_ALT5;
903 break;
904 default:
905 /* ignored below */
906 func = BCM2835_GPIO_IN;
907 break;
908 }
909 if (func != BCM2835_GPIO_IN)
910 bcm283x_pin_setfunc(sc, pin, func);
911 }
912
913 if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) {
914 cmd = (flags & GPIO_PIN_PULLUP) ?
915 BCM2835_GPIO_GPPUD_PULLUP : BCM2835_GPIO_GPPUD_PULLDOWN;
916 } else {
917 cmd = BCM2835_GPIO_GPPUD_PULLOFF;
918 }
919
920 bcm283x_pin_setpull(sc, pin, cmd);
921 mutex_exit(&sc->sc_lock);
922 }
923
924 static void *
bcmgpio_fdt_acquire(device_t dev,const void * data,size_t len,int flags)925 bcmgpio_fdt_acquire(device_t dev, const void *data, size_t len, int flags)
926 {
927 struct bcmgpio_softc *sc = device_private(dev);
928 struct bcmgpio_pin *gpin;
929 const u_int *gpio = data;
930
931 if (len != 12)
932 return NULL;
933
934 const u_int pin = be32toh(gpio[1]);
935 const bool actlo = be32toh(gpio[2]) & 1;
936
937 if (pin >= sc->sc_maxpins)
938 return NULL;
939
940 gpin = kmem_alloc(sizeof(*gpin), KM_SLEEP);
941 gpin->pin_no = pin;
942 gpin->pin_flags = flags;
943 gpin->pin_actlo = actlo;
944
945 bcm2835gpio_gpio_pin_ctl(sc, gpin->pin_no, gpin->pin_flags);
946
947 return gpin;
948 }
949
950 static void
bcmgpio_fdt_release(device_t dev,void * priv)951 bcmgpio_fdt_release(device_t dev, void *priv)
952 {
953 struct bcmgpio_softc *sc = device_private(dev);
954 struct bcmgpio_pin *gpin = priv;
955
956 bcm2835gpio_gpio_pin_ctl(sc, gpin->pin_no, GPIO_PIN_INPUT);
957 kmem_free(gpin, sizeof(*gpin));
958 }
959
960 static int
bcmgpio_fdt_read(device_t dev,void * priv,bool raw)961 bcmgpio_fdt_read(device_t dev, void *priv, bool raw)
962 {
963 struct bcmgpio_softc *sc = device_private(dev);
964 struct bcmgpio_pin *gpin = priv;
965 int val;
966
967 val = bcm2835gpio_gpio_pin_read(sc, gpin->pin_no);
968
969 if (!raw && gpin->pin_actlo)
970 val = !val;
971
972 return val;
973 }
974
975 static void
bcmgpio_fdt_write(device_t dev,void * priv,int val,bool raw)976 bcmgpio_fdt_write(device_t dev, void *priv, int val, bool raw)
977 {
978 struct bcmgpio_softc *sc = device_private(dev);
979 struct bcmgpio_pin *gpin = priv;
980
981 if (!raw && gpin->pin_actlo)
982 val = !val;
983
984 bcm2835gpio_gpio_pin_write(sc, gpin->pin_no, val);
985 }
986