1 /* $NetBSD: bcm2835_cm.c,v 1.3 2021/01/27 03:10:19 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2015 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Michael van Elst
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Driver for BCM2835 Clock Manager
34 */
35
36 #include <sys/cdefs.h>
37 __KERNEL_RCSID(0, "$NetBSD: bcm2835_cm.c,v 1.3 2021/01/27 03:10:19 thorpej Exp $");
38
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/device.h>
42 #include <sys/kernel.h>
43 #include <sys/bus.h>
44
45 #include <arm/broadcom/bcm2835reg.h>
46 #include <arm/broadcom/bcm2835_cm.h>
47
48 #include <dev/fdt/fdtvar.h>
49
50 #include <arm/fdt/arm_fdtvar.h>
51
52 struct bcm2835cm_softc {
53 device_t sc_dev;
54
55 bus_space_tag_t sc_iot;
56 bus_space_handle_t sc_ioh;
57 };
58
59 #define CM_WRITE(sc, reg, val) \
60 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
61 #define CM_READ(sc, reg) \
62 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
63
64 static int bcmcm_match(device_t, cfdata_t, void *);
65 static void bcmcm_attach(device_t, device_t, void *);
66 static int bcmcm_wait(struct bcm2835cm_softc *, int, int);
67
68 CFATTACH_DECL_NEW(bcmcm_fdt, sizeof(struct bcm2835cm_softc),
69 bcmcm_match, bcmcm_attach, NULL, NULL);
70
71 static const struct device_compatible_entry compat_data[] = {
72 { .compat = "brcm,bcm2835-cprman" },
73 DEVICE_COMPAT_EOL
74 };
75
76 /* ARGSUSED */
77 static int
bcmcm_match(device_t parent,cfdata_t match,void * aux)78 bcmcm_match(device_t parent, cfdata_t match, void *aux)
79 {
80 struct fdt_attach_args * const faa = aux;
81
82 return of_compatible_match(faa->faa_phandle, compat_data);
83 }
84
85 static void
bcmcm_attach(device_t parent,device_t self,void * aux)86 bcmcm_attach(device_t parent, device_t self, void *aux)
87 {
88 struct bcm2835cm_softc *sc = device_private(self);
89 struct fdt_attach_args * const faa = aux;
90
91 aprint_naive("\n");
92 aprint_normal(": CM\n");
93
94 sc->sc_dev = self;
95 sc->sc_iot = faa->faa_bst;
96 const int phandle = faa->faa_phandle;
97
98 bus_addr_t addr;
99 bus_size_t size;
100
101 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
102 aprint_error(": missing 'reg' property\n");
103 return;
104 }
105
106 if (bus_space_map(faa->faa_bst, addr, size, 0, &sc->sc_ioh)) {
107 aprint_error_dev(sc->sc_dev, "unable to map device\n");
108 return;
109 }
110
111 /* Success! */
112
113 return;
114 }
115
116 static int
bcmcm_wait(struct bcm2835cm_softc * sc,int ctlreg,int onoff)117 bcmcm_wait(struct bcm2835cm_softc *sc, int ctlreg, int onoff)
118 {
119 int i;
120 uint32_t r;
121
122 for (i=0; i<100; ++i) {
123 r = CM_READ(sc, ctlreg);
124 if (((r & CM_CTL_BUSY) != 0) == onoff)
125 break;
126 delay(10);
127 }
128 if (i >= 100) {
129 device_printf(sc->sc_dev, "busy (addr=%#x)\n", ctlreg);
130 return EIO;
131 }
132
133 return 0;
134 }
135
136 int
bcm_cm_set(enum bcm_cm_clock clk,uint32_t ctl,uint32_t div)137 bcm_cm_set(enum bcm_cm_clock clk, uint32_t ctl, uint32_t div)
138 {
139 struct bcm2835cm_softc *sc;
140 device_t dev;
141 int ctlreg, divreg;
142 uint32_t r;
143
144 dev = device_find_by_driver_unit("bcmcm", 0);
145 if (dev == NULL)
146 return ENXIO;
147 sc = device_private(dev);
148
149 switch (clk) {
150 case BCM_CM_GP0:
151 ctlreg = CM_GP0CTL;
152 divreg = CM_GP0DIV;
153 break;
154 case BCM_CM_GP1:
155 ctlreg = CM_GP1CTL;
156 divreg = CM_GP1DIV;
157 break;
158 case BCM_CM_GP2:
159 ctlreg = CM_GP2CTL;
160 divreg = CM_GP2DIV;
161 break;
162 case BCM_CM_PCM:
163 ctlreg = CM_PCMCTL;
164 divreg = CM_PCMDIV;
165 break;
166 case BCM_CM_PWM:
167 ctlreg = CM_PWMCTL;
168 divreg = CM_PWMDIV;
169 break;
170 default:
171 return EINVAL;
172 }
173
174 ctl &= ~CM_CTL_PASSWD;
175 ctl |= __SHIFTIN(CM_PASSWD, CM_CTL_PASSWD);
176 div &= ~CM_DIV_PASSWD;
177 div |= __SHIFTIN(CM_PASSWD, CM_DIV_PASSWD);
178
179 /*
180 * if clock is running, turn it off and wait for
181 * the cycle to end
182 */
183 r = CM_READ(sc, ctlreg);
184 if (r & CM_CTL_ENAB) {
185 r &= ~CM_CTL_PASSWD;
186 r |= __SHIFTIN(CM_PASSWD, CM_CTL_PASSWD);
187 r &= ~CM_CTL_ENAB;
188 CM_WRITE(sc, ctlreg, r);
189 }
190
191 bcmcm_wait(sc, ctlreg, 0);
192
193 /* configure new divider, mode, don't enable */
194 CM_WRITE(sc, divreg, div);
195 CM_WRITE(sc, ctlreg, ctl & ~CM_CTL_ENAB);
196
197 /* enable it */
198 if (ctl & CM_CTL_ENAB) {
199 CM_WRITE(sc, ctlreg, ctl);
200 return bcmcm_wait(sc, ctlreg, 1);
201 }
202
203 return 0;
204 }
205
206 int
bcm_cm_get(enum bcm_cm_clock clk,uint32_t * ctlp,uint32_t * divp)207 bcm_cm_get(enum bcm_cm_clock clk, uint32_t *ctlp, uint32_t *divp)
208 {
209 struct bcm2835cm_softc *sc;
210 device_t dev;
211 int ctlreg, divreg;
212
213 dev = device_find_by_driver_unit("bcmcm", 0);
214 if (dev == NULL)
215 return ENXIO;
216 sc = device_private(dev);
217
218 switch (clk) {
219 case BCM_CM_GP0:
220 ctlreg = CM_GP0CTL;
221 divreg = CM_GP0DIV;
222 break;
223 case BCM_CM_GP1:
224 ctlreg = CM_GP1CTL;
225 divreg = CM_GP1DIV;
226 break;
227 case BCM_CM_GP2:
228 ctlreg = CM_GP2CTL;
229 divreg = CM_GP2DIV;
230 break;
231 case BCM_CM_PCM:
232 ctlreg = CM_PCMCTL;
233 divreg = CM_PCMDIV;
234 break;
235 case BCM_CM_PWM:
236 ctlreg = CM_PWMCTL;
237 divreg = CM_PWMDIV;
238 break;
239 default:
240 return EINVAL;
241 }
242
243 if (ctlp != NULL)
244 *ctlp = CM_READ(sc, ctlreg);
245 if (divp != NULL)
246 *divp = CM_READ(sc, divreg);
247
248 return 0;
249 }
250