xref: /netbsd-src/sys/arch/arm/arm/cpufunc_asm_arm1136.S (revision ab152917fb47fdea0738028292e422fc44cddffb)
1/* $NetBSD: cpufunc_asm_arm1136.S,v 1.4 2013/08/18 06:28:18 matt Exp $ */
2
3/*
4 * Copyright (c) 2007 Microsoft
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 *    must display the following acknowledgement:
17 *	This product includes software developed by Microsoft
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include "assym.h"
33#include <machine/asm.h>
34#include <arm/locore.h>
35
36RCSID("$NetBSD: cpufunc_asm_arm1136.S,v 1.4 2013/08/18 06:28:18 matt Exp $")
37
38ENTRY_NP(arm1136_sleep_rev0)		/* errata 336501 */
39	mov	r0, #0
40	mcr	p15, 0, r0, c7, c10, 2	/* clean data cache line (via index) */
41	mcr	p15, 0, r0, c7, c10, 5	/* data memory barrier */
42	mcr	p15, 0, r0, c7, c0, 4	/* wait for interrupt */
43	RET
44END(arm1136_sleep_rev0)
45