1 /* $NetBSD: cpu_subr.c,v 1.5 2021/11/14 16:56:32 riastradh Exp $ */
2
3 /*-
4 * Copyright (c) 2020 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Nick Hudson
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include "opt_cputypes.h"
33 #include "opt_multiprocessor.h"
34
35 #include <sys/cdefs.h>
36 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.5 2021/11/14 16:56:32 riastradh Exp $");
37
38 #include <sys/param.h>
39 #include <sys/atomic.h>
40 #include <sys/cpu.h>
41 #include <sys/reboot.h>
42
43 #include <arm/cpufunc.h>
44
45 #ifdef VERBOSE_INIT_ARM
46 #define VPRINTF(...) printf(__VA_ARGS__)
47 #else
48 #define VPRINTF(...) __nothing
49 #endif
50
51 #ifdef MULTIPROCESSOR
52 #define NCPUINFO MAXCPUS
53 #else
54 #define NCPUINFO 1
55 #endif /* MULTIPROCESSOR */
56
57 mpidr_t cpu_mpidr[NCPUINFO] = {
58 [0 ... NCPUINFO - 1] = ~0,
59 };
60
61 struct cpu_info *cpu_info[NCPUINFO] __read_mostly = {
62 [0] = &cpu_info_store[0]
63 };
64
65 #ifdef MULTIPROCESSOR
66
67 #define CPUINDEX_DIVISOR (sizeof(u_long) * NBBY)
68
69 volatile u_long arm_cpu_hatched[howmany(MAXCPUS, CPUINDEX_DIVISOR)] __cacheline_aligned = { 0 };
70 volatile u_long arm_cpu_mbox[howmany(MAXCPUS, CPUINDEX_DIVISOR)] __cacheline_aligned = { 0 };
71 u_int arm_cpu_max = 1;
72
73 void
cpu_boot_secondary_processors(void)74 cpu_boot_secondary_processors(void)
75 {
76 u_int cpuno;
77
78 if ((boothowto & RB_MD1) != 0)
79 return;
80
81 VPRINTF("%s: starting secondary processors\n", __func__);
82
83 /* send mbox to have secondary processors do cpu_hatch() */
84 dmb(ish); /* store-release matches locore.S/armv6_start.S */
85 for (size_t n = 0; n < __arraycount(arm_cpu_mbox); n++)
86 atomic_or_ulong(&arm_cpu_mbox[n], arm_cpu_hatched[n]);
87
88 dsb(ishst);
89 sev();
90
91 /* wait all cpus have done cpu_hatch() */
92 for (cpuno = 1; cpuno < ncpu; cpuno++) {
93 if (!cpu_hatched_p(cpuno))
94 continue;
95
96 const size_t off = cpuno / CPUINDEX_DIVISOR;
97 const u_long bit = __BIT(cpuno % CPUINDEX_DIVISOR);
98
99 /* load-acquire matches cpu_clr_mbox */
100 while (atomic_load_acquire(&arm_cpu_mbox[off]) & bit) {
101 __asm __volatile ("wfe");
102 }
103 /* Add processor to kcpuset */
104 kcpuset_set(kcpuset_attached, cpuno);
105 }
106
107 VPRINTF("%s: secondary processors hatched\n", __func__);
108 }
109
110 bool
cpu_hatched_p(u_int cpuindex)111 cpu_hatched_p(u_int cpuindex)
112 {
113 const u_int off = cpuindex / CPUINDEX_DIVISOR;
114 const u_int bit = cpuindex % CPUINDEX_DIVISOR;
115
116 /* load-acquire matches cpu_set_hatched */
117 return (atomic_load_acquire(&arm_cpu_hatched[off]) & __BIT(bit)) != 0;
118 }
119
120 void
cpu_set_hatched(int cpuindex)121 cpu_set_hatched(int cpuindex)
122 {
123
124 const size_t off = cpuindex / CPUINDEX_DIVISOR;
125 const u_long bit = __BIT(cpuindex % CPUINDEX_DIVISOR);
126
127 dmb(ish); /* store-release matches cpu_hatched_p */
128 atomic_or_ulong(&arm_cpu_hatched[off], bit);
129 dsb(ishst);
130 sev();
131 }
132
133 void
cpu_clr_mbox(int cpuindex)134 cpu_clr_mbox(int cpuindex)
135 {
136
137 const size_t off = cpuindex / CPUINDEX_DIVISOR;
138 const u_long bit = __BIT(cpuindex % CPUINDEX_DIVISOR);
139
140 /* Notify cpu_boot_secondary_processors that we're done */
141 dmb(ish); /* store-release */
142 atomic_and_ulong(&arm_cpu_mbox[off], ~bit);
143 dsb(ishst);
144 sev();
145 }
146
147 #endif
148