1 /* $OpenBSD: bus_dma.c,v 1.41 2021/03/25 04:12:00 jsg Exp $ */
2 /* $NetBSD: bus_dma.c,v 1.38 2003/10/30 08:44:13 scw Exp $ */
3
4 /*-
5 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10 * NASA Ames Research Center.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #define _ARM32_BUS_DMA_PRIVATE
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/proc.h>
39 #include <sys/malloc.h>
40 #include <sys/mbuf.h>
41
42 #include <uvm/uvm_extern.h>
43
44 #include <machine/bus.h>
45 #include <arm/cpufunc.h>
46
47 /*
48 * Common function for DMA map creation. May be called by bus-specific
49 * DMA map creation functions.
50 */
51 int
_bus_dmamap_create(bus_dma_tag_t t,bus_size_t size,int nsegments,bus_size_t maxsegsz,bus_size_t boundary,int flags,bus_dmamap_t * dmamp)52 _bus_dmamap_create(bus_dma_tag_t t, bus_size_t size, int nsegments,
53 bus_size_t maxsegsz, bus_size_t boundary, int flags, bus_dmamap_t *dmamp)
54 {
55 struct arm32_bus_dmamap *map;
56 void *mapstore;
57 size_t mapsize;
58
59 #ifdef DEBUG_DMA
60 printf("dmamap_create: t=%p size=%lx nseg=%x msegsz=%lx boundary=%lx flags=%x\n",
61 t, size, nsegments, maxsegsz, boundary, flags);
62 #endif /* DEBUG_DMA */
63
64 /*
65 * Allocate and initialize the DMA map. The end of the map
66 * is a variable-sized array of segments, so we allocate enough
67 * room for them in one shot.
68 *
69 * Note we don't preserve the WAITOK or NOWAIT flags. Preservation
70 * of ALLOCNOW notifies others that we've reserved these resources,
71 * and they are not to be freed.
72 *
73 * The bus_dmamap_t includes one bus_dma_segment_t, hence
74 * the (nsegments - 1).
75 */
76 mapsize = sizeof(struct arm32_bus_dmamap) +
77 (sizeof(bus_dma_segment_t) * (nsegments - 1));
78 if ((mapstore = malloc(mapsize, M_DEVBUF, (flags & BUS_DMA_NOWAIT) ?
79 (M_NOWAIT | M_ZERO) : (M_WAITOK | M_ZERO))) == NULL)
80 return (ENOMEM);
81
82 map = (struct arm32_bus_dmamap *)mapstore;
83 map->_dm_size = size;
84 map->_dm_segcnt = nsegments;
85 map->_dm_maxsegsz = maxsegsz;
86 map->_dm_boundary = boundary;
87 map->_dm_flags = flags & ~(BUS_DMA_WAITOK|BUS_DMA_NOWAIT);
88 map->_dm_origbuf = NULL;
89 map->_dm_buftype = ARM32_BUFTYPE_INVALID;
90 map->_dm_proc = NULL;
91 map->dm_mapsize = 0; /* no valid mappings */
92 map->dm_nsegs = 0;
93
94 *dmamp = map;
95 #ifdef DEBUG_DMA
96 printf("dmamap_create:map=%p\n", map);
97 #endif /* DEBUG_DMA */
98 return (0);
99 }
100
101 /*
102 * Common function for DMA map destruction. May be called by bus-specific
103 * DMA map destruction functions.
104 */
105 void
_bus_dmamap_destroy(bus_dma_tag_t t,bus_dmamap_t map)106 _bus_dmamap_destroy(bus_dma_tag_t t, bus_dmamap_t map)
107 {
108 size_t mapsize;
109
110 #ifdef DEBUG_DMA
111 printf("dmamap_destroy: t=%p map=%p\n", t, map);
112 #endif /* DEBUG_DMA */
113
114 mapsize = sizeof(struct arm32_bus_dmamap) +
115 (sizeof(bus_dma_segment_t) * (map->_dm_segcnt - 1));
116 free(map, M_DEVBUF, mapsize);
117 }
118
119 /*
120 * Common function for loading a DMA map with a linear buffer. May
121 * be called by bus-specific DMA map load functions.
122 */
123 int
_bus_dmamap_load(bus_dma_tag_t t,bus_dmamap_t map,void * buf,bus_size_t buflen,struct proc * p,int flags)124 _bus_dmamap_load(bus_dma_tag_t t, bus_dmamap_t map, void *buf,
125 bus_size_t buflen, struct proc *p, int flags)
126 {
127 paddr_t lastaddr;
128 int seg, error;
129
130 #ifdef DEBUG_DMA
131 printf("dmamap_load: t=%p map=%p buf=%p len=%lx p=%p f=%d\n",
132 t, map, buf, buflen, p, flags);
133 #endif /* DEBUG_DMA */
134
135 /*
136 * Make sure that on error condition we return "no valid mappings".
137 */
138 map->dm_mapsize = 0;
139 map->dm_nsegs = 0;
140
141 if (buflen > map->_dm_size)
142 return (EINVAL);
143
144 /* _bus_dmamap_load_buffer() clears this if we're not... */
145 map->_dm_flags |= ARM32_DMAMAP_COHERENT;
146
147 seg = 0;
148 error = (*t->_dmamap_load_buffer)(t, map, buf, buflen, p, flags,
149 &lastaddr, &seg, 1);
150 if (error == 0) {
151 map->dm_mapsize = buflen;
152 map->dm_nsegs = seg + 1;
153 map->_dm_origbuf = buf;
154 map->_dm_buftype = ARM32_BUFTYPE_LINEAR;
155 map->_dm_proc = p;
156 }
157 #ifdef DEBUG_DMA
158 printf("dmamap_load: error=%d\n", error);
159 #endif /* DEBUG_DMA */
160 return (error);
161 }
162
163 /*
164 * Like _bus_dmamap_load(), but for mbufs.
165 */
166 int
_bus_dmamap_load_mbuf(bus_dma_tag_t t,bus_dmamap_t map,struct mbuf * m0,int flags)167 _bus_dmamap_load_mbuf(bus_dma_tag_t t, bus_dmamap_t map, struct mbuf *m0,
168 int flags)
169 {
170 paddr_t lastaddr;
171 int seg, error, first;
172 struct mbuf *m;
173
174 #ifdef DEBUG_DMA
175 printf("dmamap_load_mbuf: t=%p map=%p m0=%p f=%d\n",
176 t, map, m0, flags);
177 #endif /* DEBUG_DMA */
178
179 /*
180 * Make sure that on error condition we return "no valid mappings."
181 */
182 map->dm_mapsize = 0;
183 map->dm_nsegs = 0;
184
185 #ifdef DIAGNOSTIC
186 if ((m0->m_flags & M_PKTHDR) == 0)
187 panic("_bus_dmamap_load_mbuf: no packet header");
188 #endif /* DIAGNOSTIC */
189
190 if (m0->m_pkthdr.len > map->_dm_size)
191 return (EINVAL);
192
193 /*
194 * Mbuf chains should almost never have coherent (i.e.
195 * un-cached) mappings, so clear that flag now.
196 */
197 map->_dm_flags &= ~ARM32_DMAMAP_COHERENT;
198
199 first = 1;
200 seg = 0;
201 error = 0;
202 for (m = m0; m != NULL && error == 0; m = m->m_next) {
203 if (m->m_len == 0)
204 continue;
205 error = (*t->_dmamap_load_buffer)(t, map, m->m_data, m->m_len,
206 NULL, flags, &lastaddr, &seg, first);
207 first = 0;
208 }
209 if (error == 0) {
210 map->dm_mapsize = m0->m_pkthdr.len;
211 map->dm_nsegs = seg + 1;
212 map->_dm_origbuf = m0;
213 map->_dm_buftype = ARM32_BUFTYPE_MBUF;
214 map->_dm_proc = NULL; /* always kernel */
215 }
216 #ifdef DEBUG_DMA
217 printf("dmamap_load_mbuf: error=%d\n", error);
218 #endif /* DEBUG_DMA */
219 return (error);
220 }
221
222 /*
223 * Like _bus_dmamap_load(), but for uios.
224 */
225 int
_bus_dmamap_load_uio(bus_dma_tag_t t,bus_dmamap_t map,struct uio * uio,int flags)226 _bus_dmamap_load_uio(bus_dma_tag_t t, bus_dmamap_t map, struct uio *uio,
227 int flags)
228 {
229 paddr_t lastaddr;
230 int seg, i, error, first;
231 bus_size_t minlen, resid;
232 struct proc *p = NULL;
233 struct iovec *iov;
234 caddr_t addr;
235
236 /*
237 * Make sure that on error condition we return "no valid mappings."
238 */
239 map->dm_mapsize = 0;
240 map->dm_nsegs = 0;
241
242 resid = uio->uio_resid;
243 iov = uio->uio_iov;
244
245 if (uio->uio_segflg == UIO_USERSPACE) {
246 p = uio->uio_procp;
247 #ifdef DIAGNOSTIC
248 if (p == NULL)
249 panic("_bus_dmamap_load_uio: USERSPACE but no proc");
250 #endif
251 }
252
253 /* _bus_dmamap_load_buffer() clears this if we're not... */
254 map->_dm_flags |= ARM32_DMAMAP_COHERENT;
255
256 first = 1;
257 seg = 0;
258 error = 0;
259 for (i = 0; i < uio->uio_iovcnt && resid != 0 && error == 0; i++) {
260 /*
261 * Now at the first iovec to load. Load each iovec
262 * until we have exhausted the residual count.
263 */
264 minlen = resid < iov[i].iov_len ? resid : iov[i].iov_len;
265 addr = (caddr_t)iov[i].iov_base;
266
267 error = (*t->_dmamap_load_buffer)(t, map, addr, minlen,
268 p, flags, &lastaddr, &seg, first);
269 first = 0;
270
271 resid -= minlen;
272 }
273 if (error == 0) {
274 map->dm_mapsize = uio->uio_resid;
275 map->dm_nsegs = seg + 1;
276 map->_dm_origbuf = uio;
277 map->_dm_buftype = ARM32_BUFTYPE_UIO;
278 map->_dm_proc = p;
279 }
280 return (error);
281 }
282
283 /*
284 * Like _bus_dmamap_load(), but for raw memory allocated with
285 * bus_dmamem_alloc().
286 */
287 int
_bus_dmamap_load_raw(bus_dma_tag_t t,bus_dmamap_t map,bus_dma_segment_t * segs,int nsegs,bus_size_t size,int flags)288 _bus_dmamap_load_raw(bus_dma_tag_t t, bus_dmamap_t map,
289 bus_dma_segment_t *segs, int nsegs, bus_size_t size, int flags)
290 {
291 bus_addr_t paddr, baddr, bmask, lastaddr = 0;
292 bus_size_t plen, sgsize, mapsize;
293 vaddr_t vaddr;
294 int first = 1;
295 int i, seg = 0;
296
297 /*
298 * Make sure that on error condition we return "no valid mappings".
299 */
300 map->dm_mapsize = 0;
301 map->dm_nsegs = 0;
302
303 if (nsegs > map->_dm_segcnt || size > map->_dm_size)
304 return (EINVAL);
305
306 mapsize = size;
307 bmask = ~(map->_dm_boundary - 1);
308
309 /*
310 * Assume to be coherent at first. If one of the segments
311 * isn't, we clear the flag for the whole map.
312 */
313 map->_dm_flags |= ARM32_DMAMAP_COHERENT;
314
315 for (i = 0; i < nsegs && size > 0; i++) {
316 paddr = segs[i].ds_addr;
317 vaddr = segs[i]._ds_vaddr;
318 plen = MIN(segs[i].ds_len, size);
319
320 if (!segs[i]._ds_coherent)
321 map->_dm_flags &= ~ARM32_DMAMAP_COHERENT;
322
323 while (plen > 0) {
324 /*
325 * Compute the segment size, and adjust counts.
326 */
327 sgsize = PAGE_SIZE - ((u_long)paddr & PGOFSET);
328 if (plen < sgsize)
329 sgsize = plen;
330
331 /*
332 * Make sure we don't cross any boundaries.
333 */
334 if (map->_dm_boundary > 0) {
335 baddr = (paddr + map->_dm_boundary) & bmask;
336 if (sgsize > (baddr - paddr))
337 sgsize = (baddr - paddr);
338 }
339
340 /*
341 * Insert chunk into a segment, coalescing with
342 * previous segment if possible.
343 */
344 if (first) {
345 map->dm_segs[seg].ds_addr = paddr;
346 map->dm_segs[seg].ds_len = sgsize;
347 map->dm_segs[seg]._ds_vaddr = vaddr;
348 first = 0;
349 } else {
350 if (paddr == lastaddr &&
351 (map->dm_segs[seg].ds_len + sgsize) <=
352 map->_dm_maxsegsz &&
353 (map->_dm_boundary == 0 ||
354 (map->dm_segs[seg].ds_addr & bmask) ==
355 (paddr & bmask)))
356 map->dm_segs[seg].ds_len += sgsize;
357 else {
358 if (++seg >= map->_dm_segcnt)
359 return (EINVAL);
360 map->dm_segs[seg].ds_addr = paddr;
361 map->dm_segs[seg].ds_len = sgsize;
362 map->dm_segs[seg]._ds_vaddr = vaddr;
363 }
364 }
365
366 paddr += sgsize;
367 vaddr += sgsize;
368 plen -= sgsize;
369 size -= sgsize;
370
371 lastaddr = paddr;
372 }
373 }
374
375 map->dm_mapsize = mapsize;
376 map->dm_nsegs = seg + 1;
377 map->_dm_buftype = ARM32_BUFTYPE_RAW;
378 map->_dm_origbuf = NULL;
379 map->_dm_proc = NULL;
380 return (0);
381 }
382
383 /*
384 * Common function for unloading a DMA map. May be called by
385 * bus-specific DMA map unload functions.
386 */
387 void
_bus_dmamap_unload(bus_dma_tag_t t,bus_dmamap_t map)388 _bus_dmamap_unload(bus_dma_tag_t t, bus_dmamap_t map)
389 {
390
391 #ifdef DEBUG_DMA
392 printf("dmamap_unload: t=%p map=%p\n", t, map);
393 #endif /* DEBUG_DMA */
394
395 /*
396 * No resources to free; just mark the mappings as
397 * invalid.
398 */
399 map->dm_mapsize = 0;
400 map->dm_nsegs = 0;
401 map->_dm_origbuf = NULL;
402 map->_dm_buftype = ARM32_BUFTYPE_INVALID;
403 map->_dm_proc = NULL;
404 }
405
406 static void
_bus_dmamap_sync_segment(vaddr_t va,paddr_t pa,vsize_t len,int ops)407 _bus_dmamap_sync_segment(vaddr_t va, paddr_t pa, vsize_t len, int ops)
408 {
409 KASSERT((va & PAGE_MASK) == (pa & PAGE_MASK));
410
411 #ifdef DEBUG_DMA
412 printf("sync_segment: va=%#lx pa=%#lx len=%#lx ops=%#x\n",
413 va, pa, len, ops);
414 #endif
415
416 switch (ops) {
417 case BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE:
418 cpu_dcache_wbinv_range(va, len);
419 cpu_sdcache_wbinv_range(va, pa, len);
420 break;
421
422 case BUS_DMASYNC_PREREAD: {
423 const size_t line_size = arm_dcache_align;
424 const size_t line_mask = arm_dcache_align_mask;
425 vsize_t misalignment = va & line_mask;
426 if (misalignment) {
427 va -= misalignment;
428 pa -= misalignment;
429 len += misalignment;
430 cpu_dcache_wbinv_range(va, line_size);
431 cpu_sdcache_wbinv_range(va, pa, line_size);
432 if (len <= line_size)
433 break;
434 va += line_size;
435 pa += line_size;
436 len -= line_size;
437 }
438 misalignment = len & line_mask;
439 len -= misalignment;
440 if (len > 0) {
441 cpu_dcache_inv_range(va, len);
442 cpu_sdcache_inv_range(va, pa, len);
443 }
444 if (misalignment) {
445 va += len;
446 pa += len;
447 cpu_dcache_wbinv_range(va, line_size);
448 cpu_sdcache_wbinv_range(va, pa, line_size);
449 }
450 break;
451 }
452
453 case BUS_DMASYNC_PREWRITE:
454 cpu_dcache_wb_range(va, len);
455 cpu_sdcache_wb_range(va, pa, len);
456 break;
457
458 /*
459 * Cortex CPUs can do speculative loads so we need to clean the cache
460 * after a DMA read to deal with any speculatively loaded cache lines.
461 * Since these can't be dirty, we can just invalidate them and don't
462 * have to worry about having to write back their contents.
463 */
464 case BUS_DMASYNC_POSTREAD:
465 case BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE:
466 membar_sync();
467 cpu_dcache_inv_range(va, len);
468 cpu_sdcache_inv_range(va, pa, len);
469 break;
470 }
471 }
472
473 static __inline void
_bus_dmamap_sync_linear(bus_dma_tag_t t,bus_dmamap_t map,bus_addr_t offset,bus_size_t len,int ops)474 _bus_dmamap_sync_linear(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
475 bus_size_t len, int ops)
476 {
477 bus_dma_segment_t *ds = map->dm_segs;
478 vaddr_t va = (vaddr_t) map->_dm_origbuf;
479
480 while (len > 0) {
481 while (offset >= ds->ds_len) {
482 offset -= ds->ds_len;
483 va += ds->ds_len;
484 ds++;
485 }
486
487 paddr_t pa = ds->ds_addr + offset;
488 size_t seglen = min(len, ds->ds_len - offset);
489
490 _bus_dmamap_sync_segment(va + offset, pa, seglen, ops);
491
492 offset += seglen;
493 len -= seglen;
494 }
495 }
496
497 static __inline void
_bus_dmamap_sync_mbuf(bus_dma_tag_t t,bus_dmamap_t map,bus_addr_t offset,bus_size_t len,int ops)498 _bus_dmamap_sync_mbuf(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
499 bus_size_t len, int ops)
500 {
501 bus_dma_segment_t *ds = map->dm_segs;
502 struct mbuf *m = map->_dm_origbuf;
503 bus_size_t voff = offset;
504 bus_size_t ds_off = offset;
505
506 while (len > 0) {
507 /* Find the current dma segment */
508 while (ds_off >= ds->ds_len) {
509 ds_off -= ds->ds_len;
510 ds++;
511 }
512 /* Find the current mbuf. */
513 while (voff >= m->m_len) {
514 voff -= m->m_len;
515 m = m->m_next;
516 }
517
518 /*
519 * Now at the first mbuf to sync; nail each one until
520 * we have exhausted the length.
521 */
522 vsize_t seglen = min(len, min(m->m_len - voff, ds->ds_len - ds_off));
523 vaddr_t va = mtod(m, vaddr_t) + voff;
524 paddr_t pa = ds->ds_addr + ds_off;
525
526 /*
527 * We can save a lot of work here if we know the mapping
528 * is read-only at the MMU:
529 *
530 * If a mapping is read-only, no dirty cache blocks will
531 * exist for it. If a writable mapping was made read-only,
532 * we know any dirty cache lines for the range will have
533 * been cleaned for us already. Therefore, if the upper
534 * layer can tell us we have a read-only mapping, we can
535 * skip all cache cleaning.
536 *
537 * NOTE: This only works if we know the pmap cleans pages
538 * before making a read-write -> read-only transition. If
539 * this ever becomes non-true (e.g. Physically Indexed
540 * cache), this will have to be revisited.
541 */
542 _bus_dmamap_sync_segment(va, pa, seglen, ops);
543
544 voff += seglen;
545 ds_off += seglen;
546 len -= seglen;
547 }
548 }
549
550 static __inline void
_bus_dmamap_sync_uio(bus_dma_tag_t t,bus_dmamap_t map,bus_addr_t offset,bus_size_t len,int ops)551 _bus_dmamap_sync_uio(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
552 bus_size_t len, int ops)
553 {
554 bus_dma_segment_t *ds = map->dm_segs;
555 struct uio *uio = map->_dm_origbuf;
556 struct iovec *iov = uio->uio_iov;
557 bus_size_t voff = offset;
558 bus_size_t ds_off = offset;
559
560 while (len > 0) {
561 /* Find the current dma segment */
562 while (ds_off >= ds->ds_len) {
563 ds_off -= ds->ds_len;
564 ds++;
565 }
566
567 /* Find the current iovec. */
568 while (voff >= iov->iov_len) {
569 voff -= iov->iov_len;
570 iov++;
571 }
572
573 /*
574 * Now at the first iovec to sync; nail each one until
575 * we have exhausted the length.
576 */
577 vsize_t seglen = min(len, min(iov->iov_len - voff, ds->ds_len - ds_off));
578 vaddr_t va = (vaddr_t) iov->iov_base + voff;
579 paddr_t pa = ds->ds_addr + ds_off;
580
581 _bus_dmamap_sync_segment(va, pa, seglen, ops);
582
583 voff += seglen;
584 ds_off += seglen;
585 len -= seglen;
586 }
587 }
588
589 static __inline void
_bus_dmamap_sync_raw(bus_dma_tag_t t,bus_dmamap_t map,bus_addr_t offset,bus_size_t len,int ops)590 _bus_dmamap_sync_raw(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
591 bus_size_t len, int ops)
592 {
593 bus_dma_segment_t *ds = map->dm_segs;
594
595 while (len > 0) {
596 while (offset >= ds->ds_len) {
597 offset -= ds->ds_len;
598 ds++;
599 }
600
601 vaddr_t va = ds->_ds_vaddr + offset;
602 paddr_t pa = ds->ds_addr + offset;
603 size_t seglen = min(len, ds->ds_len - offset);
604
605 _bus_dmamap_sync_segment(va, pa, seglen, ops);
606
607 offset += seglen;
608 len -= seglen;
609 }
610 }
611
612 /*
613 * Common function for DMA map synchronization. May be called
614 * by bus-specific DMA map synchronization functions.
615 *
616 * This version works for the Virtually Indexed Virtually Tagged
617 * cache found on 32-bit ARM processors.
618 *
619 * XXX Should have separate versions for write-through vs.
620 * XXX write-back caches. We currently assume write-back
621 * XXX here, which is not as efficient as it could be for
622 * XXX the write-through case.
623 */
624 void
_bus_dmamap_sync(bus_dma_tag_t t,bus_dmamap_t map,bus_addr_t offset,bus_size_t len,int ops)625 _bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
626 bus_size_t len, int ops)
627 {
628
629 #ifdef DEBUG_DMA
630 printf("dmamap_sync: t=%p map=%p offset=%lx len=%lx ops=%x\n",
631 t, map, offset, len, ops);
632 #endif /* DEBUG_DMA */
633
634 /*
635 * Mixing of PRE and POST operations is not allowed.
636 */
637 if ((ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) != 0 &&
638 (ops & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) != 0)
639 panic("_bus_dmamap_sync: mix PRE and POST");
640
641 #ifdef DIAGNOSTIC
642 if (offset >= map->dm_mapsize)
643 panic("_bus_dmamap_sync: bad offset %lu (map size is %lu)",
644 offset, map->dm_mapsize);
645 if ((offset + len) > map->dm_mapsize)
646 panic("_bus_dmamap_sync: bad length");
647 #endif
648
649 /*
650 * For a virtually-indexed write-back cache, we need
651 * to do the following things:
652 *
653 * PREREAD -- Invalidate the D-cache. We do this
654 * here in case a write-back is required by the back-end.
655 *
656 * PREWRITE -- Write-back the D-cache. Note that if
657 * we are doing a PREREAD|PREWRITE, we can collapse
658 * the whole thing into a single Wb-Inv.
659 *
660 * POSTREAD -- Invalidate the D-Cache. Contents of
661 * the cache could be from before a device wrote
662 * to the memory.
663 *
664 * POSTWRITE -- Nothing.
665 */
666
667 /* Skip cache frobbing if mapping was COHERENT. */
668 if (map->_dm_flags & ARM32_DMAMAP_COHERENT) {
669 /* Drain the write buffer. */
670 cpu_drain_writebuf();
671 cpu_sdcache_drain_writebuf();
672 return;
673 }
674
675 /*
676 * If the mapping belongs to a non-kernel vmspace, and the
677 * vmspace has not been active since the last time a full
678 * cache flush was performed, we don't need to do anything.
679 */
680 if (__predict_false(map->_dm_proc != NULL &&
681 map->_dm_proc->p_vmspace->vm_map.pmap->pm_cstate.cs_cache_d == 0))
682 return;
683
684 switch (map->_dm_buftype) {
685 case ARM32_BUFTYPE_LINEAR:
686 _bus_dmamap_sync_linear(t, map, offset, len, ops);
687 break;
688
689 case ARM32_BUFTYPE_MBUF:
690 _bus_dmamap_sync_mbuf(t, map, offset, len, ops);
691 break;
692
693 case ARM32_BUFTYPE_UIO:
694 _bus_dmamap_sync_uio(t, map, offset, len, ops);
695 break;
696
697 case ARM32_BUFTYPE_RAW:
698 _bus_dmamap_sync_raw(t, map, offset, len, ops);
699 break;
700
701 case ARM32_BUFTYPE_INVALID:
702 panic("_bus_dmamap_sync: ARM32_BUFTYPE_INVALID");
703 break;
704
705 default:
706 printf("unknown buffer type %d\n", map->_dm_buftype);
707 panic("_bus_dmamap_sync");
708 }
709
710 /* Drain the write buffer. */
711 cpu_drain_writebuf();
712 }
713
714 /*
715 * Common function for DMA-safe memory allocation. May be called
716 * by bus-specific DMA memory allocation functions.
717 */
718
719 int
_bus_dmamem_alloc(bus_dma_tag_t t,bus_size_t size,bus_size_t alignment,bus_size_t boundary,bus_dma_segment_t * segs,int nsegs,int * rsegs,int flags)720 _bus_dmamem_alloc(bus_dma_tag_t t, bus_size_t size, bus_size_t alignment,
721 bus_size_t boundary, bus_dma_segment_t *segs, int nsegs, int *rsegs,
722 int flags)
723 {
724 int error;
725
726 #ifdef DEBUG_DMA
727 printf("dmamem_alloc t=%p size=%lx align=%lx boundary=%lx "
728 "segs=%p nsegs=%x rsegs=%p flags=%x\n", t, size, alignment,
729 boundary, segs, nsegs, rsegs, flags);
730 #endif
731
732 error = _bus_dmamem_alloc_range(t, size, alignment, boundary,
733 segs, nsegs, rsegs, flags, 0, -1);
734
735 #ifdef DEBUG_DMA
736 printf("dmamem_alloc: =%d\n", error);
737 #endif
738
739 return(error);
740 }
741
742 /*
743 * Common function for freeing DMA-safe memory. May be called by
744 * bus-specific DMA memory free functions.
745 */
746 void
_bus_dmamem_free(bus_dma_tag_t t,bus_dma_segment_t * segs,int nsegs)747 _bus_dmamem_free(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs)
748 {
749 struct vm_page *m;
750 bus_addr_t addr;
751 struct pglist mlist;
752 int curseg;
753
754 #ifdef DEBUG_DMA
755 printf("dmamem_free: t=%p segs=%p nsegs=%x\n", t, segs, nsegs);
756 #endif /* DEBUG_DMA */
757
758 /*
759 * Build a list of pages to free back to the VM system.
760 */
761 TAILQ_INIT(&mlist);
762 for (curseg = 0; curseg < nsegs; curseg++) {
763 for (addr = segs[curseg].ds_addr;
764 addr < (segs[curseg].ds_addr + segs[curseg].ds_len);
765 addr += PAGE_SIZE) {
766 m = PHYS_TO_VM_PAGE(addr);
767 TAILQ_INSERT_TAIL(&mlist, m, pageq);
768 }
769 }
770 uvm_pglistfree(&mlist);
771 }
772
773 /*
774 * Common function for mapping DMA-safe memory. May be called by
775 * bus-specific DMA memory map functions.
776 */
777 int
_bus_dmamem_map(bus_dma_tag_t t,bus_dma_segment_t * segs,int nsegs,size_t size,caddr_t * kvap,int flags)778 _bus_dmamem_map(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs,
779 size_t size, caddr_t *kvap, int flags)
780 {
781 vaddr_t va, sva;
782 size_t ssize;
783 bus_addr_t addr;
784 int curseg;
785 const struct kmem_dyn_mode *kd;
786 #ifdef DEBUG_DMA
787 pt_entry_t *ptep;
788 #endif
789
790 #ifdef DEBUG_DMA
791 printf("dmamem_map: t=%p segs=%p nsegs=%x size=%lx flags=%x\n", t,
792 segs, nsegs, (unsigned long)size, flags);
793 #endif /* DEBUG_DMA */
794
795 size = round_page(size);
796 kd = flags & BUS_DMA_NOWAIT ? &kd_trylock : &kd_waitok;
797 va = (vaddr_t)km_alloc(size, &kv_any, &kp_none, kd);
798 if (va == 0)
799 return (ENOMEM);
800
801 *kvap = (caddr_t)va;
802
803 sva = va;
804 ssize = size;
805 for (curseg = 0; curseg < nsegs; curseg++) {
806 for (addr = segs[curseg].ds_addr;
807 addr < (segs[curseg].ds_addr + segs[curseg].ds_len);
808 addr += PAGE_SIZE, va += PAGE_SIZE, size -= PAGE_SIZE) {
809 #ifdef DEBUG_DMA
810 printf("wiring p%lx to v%lx", addr, va);
811 #endif /* DEBUG_DMA */
812 if (size == 0)
813 panic("_bus_dmamem_map: size botch");
814 segs[curseg]._ds_coherent =
815 !!(flags & BUS_DMA_COHERENT);
816 segs[curseg]._ds_vaddr = va;
817 pmap_kenter_cache(va, addr,
818 PROT_READ | PROT_WRITE,
819 !(flags & BUS_DMA_COHERENT));
820
821 #ifdef DEBUG_DMA
822 ptep = vtopte(va);
823 printf(" pte=v%p *pte=%x\n", ptep, *ptep);
824 #endif /* DEBUG_DMA */
825 }
826 }
827 pmap_update(pmap_kernel());
828 #ifdef DEBUG_DMA
829 printf("dmamem_map: =%p\n", *kvap);
830 #endif /* DEBUG_DMA */
831 return (0);
832 }
833
834 /*
835 * Common function for unmapping DMA-safe memory. May be called by
836 * bus-specific DMA memory unmapping functions.
837 */
838 void
_bus_dmamem_unmap(bus_dma_tag_t t,caddr_t kva,size_t size)839 _bus_dmamem_unmap(bus_dma_tag_t t, caddr_t kva, size_t size)
840 {
841
842 #ifdef DEBUG_DMA
843 printf("dmamem_unmap: t=%p kva=%p size=%lx\n", t, kva,
844 (unsigned long)size);
845 #endif /* DEBUG_DMA */
846 #ifdef DIAGNOSTIC
847 if ((u_long)kva & PGOFSET)
848 panic("_bus_dmamem_unmap");
849 #endif /* DIAGNOSTIC */
850
851 km_free(kva, round_page(size), &kv_any, &kp_none);
852 }
853
854 /*
855 * Common function for mmap(2)'ing DMA-safe memory. May be called by
856 * bus-specific DMA mmap(2)'ing functions.
857 */
858 paddr_t
_bus_dmamem_mmap(bus_dma_tag_t t,bus_dma_segment_t * segs,int nsegs,off_t off,int prot,int flags)859 _bus_dmamem_mmap(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs,
860 off_t off, int prot, int flags)
861 {
862 int i;
863
864 for (i = 0; i < nsegs; i++) {
865 #ifdef DIAGNOSTIC
866 if (off & PGOFSET)
867 panic("_bus_dmamem_mmap: offset unaligned");
868 if (segs[i].ds_addr & PGOFSET)
869 panic("_bus_dmamem_mmap: segment unaligned");
870 if (segs[i].ds_len & PGOFSET)
871 panic("_bus_dmamem_mmap: segment size not multiple"
872 " of page size");
873 #endif /* DIAGNOSTIC */
874 if (off >= segs[i].ds_len) {
875 off -= segs[i].ds_len;
876 continue;
877 }
878
879 return (segs[i].ds_addr + off);
880 }
881
882 /* Page not found. */
883 return (-1);
884 }
885
886 /**********************************************************************
887 * DMA utility functions
888 **********************************************************************/
889
890 /*
891 * Utility function to load a linear buffer. lastaddrp holds state
892 * between invocations (for multiple-buffer loads). segp contains
893 * the starting segment on entrance, and the ending segment on exit.
894 * first indicates if this is the first invocation of this function.
895 */
896 int
_bus_dmamap_load_buffer(bus_dma_tag_t t,bus_dmamap_t map,void * buf,bus_size_t buflen,struct proc * p,int flags,paddr_t * lastaddrp,int * segp,int first)897 _bus_dmamap_load_buffer(bus_dma_tag_t t, bus_dmamap_t map, void *buf,
898 bus_size_t buflen, struct proc *p, int flags, paddr_t *lastaddrp,
899 int *segp, int first)
900 {
901 bus_size_t sgsize;
902 bus_addr_t curaddr, lastaddr, baddr, bmask;
903 vaddr_t vaddr = (vaddr_t)buf;
904 pd_entry_t *pde;
905 pt_entry_t pte;
906 int seg;
907 pmap_t pmap;
908 pt_entry_t *ptep;
909
910 #ifdef DEBUG_DMA
911 printf("_bus_dmamem_load_buffer(buf=%p, len=%lx, flags=%d, 1st=%d)\n",
912 buf, buflen, flags, first);
913 #endif /* DEBUG_DMA */
914
915 if (p != NULL)
916 pmap = p->p_vmspace->vm_map.pmap;
917 else
918 pmap = pmap_kernel();
919
920 lastaddr = *lastaddrp;
921 bmask = ~(map->_dm_boundary - 1);
922
923 for (seg = *segp; buflen > 0; ) {
924 /*
925 * Get the physical address for this segment.
926 *
927 * XXX Don't support checking for coherent mappings
928 * XXX in user address space.
929 */
930 if (__predict_true(pmap == pmap_kernel())) {
931 (void) pmap_get_pde_pte(pmap, vaddr, &pde, &ptep);
932 if (__predict_false(pmap_pde_section(pde))) {
933 curaddr = (*pde & L1_S_FRAME) |
934 (vaddr & L1_S_OFFSET);
935 if (*pde & L1_S_COHERENT) {
936 map->_dm_flags &=
937 ~ARM32_DMAMAP_COHERENT;
938 }
939 } else {
940 pte = *ptep;
941 KDASSERT((pte & L2_TYPE_MASK) != L2_TYPE_INV);
942 if (__predict_false((pte & L2_TYPE_MASK)
943 == L2_TYPE_L)) {
944 curaddr = (pte & L2_L_FRAME) |
945 (vaddr & L2_L_OFFSET);
946 if (pte & L2_L_COHERENT) {
947 map->_dm_flags &=
948 ~ARM32_DMAMAP_COHERENT;
949 }
950 } else {
951 curaddr = (pte & L2_S_FRAME) |
952 (vaddr & L2_S_OFFSET);
953 if (pte & L2_S_COHERENT) {
954 map->_dm_flags &=
955 ~ARM32_DMAMAP_COHERENT;
956 }
957 }
958 }
959 } else {
960 (void) pmap_extract(pmap, vaddr, &curaddr);
961 map->_dm_flags &= ~ARM32_DMAMAP_COHERENT;
962 }
963
964 /*
965 * Compute the segment size, and adjust counts.
966 */
967 sgsize = PAGE_SIZE - ((u_long)vaddr & PGOFSET);
968 if (buflen < sgsize)
969 sgsize = buflen;
970
971 /*
972 * Make sure we don't cross any boundaries.
973 */
974 if (map->_dm_boundary > 0) {
975 baddr = (curaddr + map->_dm_boundary) & bmask;
976 if (sgsize > (baddr - curaddr))
977 sgsize = (baddr - curaddr);
978 }
979
980 /*
981 * Insert chunk into a segment, coalescing with
982 * previous segment if possible.
983 */
984 if (first) {
985 map->dm_segs[seg].ds_addr = curaddr;
986 map->dm_segs[seg].ds_len = sgsize;
987 first = 0;
988 } else {
989 if (curaddr == lastaddr &&
990 (map->dm_segs[seg].ds_len + sgsize) <=
991 map->_dm_maxsegsz &&
992 (map->_dm_boundary == 0 ||
993 (map->dm_segs[seg].ds_addr & bmask) ==
994 (curaddr & bmask)))
995 map->dm_segs[seg].ds_len += sgsize;
996 else {
997 if (++seg >= map->_dm_segcnt)
998 break;
999 map->dm_segs[seg].ds_addr = curaddr;
1000 map->dm_segs[seg].ds_len = sgsize;
1001 }
1002 }
1003
1004 lastaddr = curaddr + sgsize;
1005 vaddr += sgsize;
1006 buflen -= sgsize;
1007 }
1008
1009 *segp = seg;
1010 *lastaddrp = lastaddr;
1011
1012 /*
1013 * Did we fit?
1014 */
1015 if (buflen != 0)
1016 return (EFBIG); /* XXX better return value here? */
1017 return (0);
1018 }
1019
1020 /*
1021 * Allocate physical memory from the given physical address range.
1022 * Called by DMA-safe memory allocation methods.
1023 */
1024 int
_bus_dmamem_alloc_range(bus_dma_tag_t t,bus_size_t size,bus_size_t alignment,bus_size_t boundary,bus_dma_segment_t * segs,int nsegs,int * rsegs,int flags,paddr_t low,paddr_t high)1025 _bus_dmamem_alloc_range(bus_dma_tag_t t, bus_size_t size, bus_size_t alignment,
1026 bus_size_t boundary, bus_dma_segment_t *segs, int nsegs, int *rsegs,
1027 int flags, paddr_t low, paddr_t high)
1028 {
1029 paddr_t curaddr, lastaddr;
1030 struct vm_page *m;
1031 struct pglist mlist;
1032 int curseg, error, plaflag;
1033
1034 #ifdef DEBUG_DMA
1035 printf("alloc_range: t=%p size=%lx align=%lx boundary=%lx segs=%p nsegs=%x rsegs=%p flags=%x lo=%lx hi=%lx\n",
1036 t, size, alignment, boundary, segs, nsegs, rsegs, flags, low, high);
1037 #endif /* DEBUG_DMA */
1038
1039 /* Always round the size. */
1040 size = round_page(size);
1041
1042 /*
1043 * Allocate pages from the VM system.
1044 */
1045 plaflag = flags & BUS_DMA_NOWAIT ? UVM_PLA_NOWAIT : UVM_PLA_WAITOK;
1046 if (flags & BUS_DMA_ZERO)
1047 plaflag |= UVM_PLA_ZERO;
1048
1049 TAILQ_INIT(&mlist);
1050 error = uvm_pglistalloc(size, low, high, alignment, boundary,
1051 &mlist, nsegs, plaflag);
1052 if (error)
1053 return (error);
1054
1055 /*
1056 * Compute the location, size, and number of segments actually
1057 * returned by the VM code.
1058 */
1059 m = TAILQ_FIRST(&mlist);
1060 curseg = 0;
1061 lastaddr = segs[curseg].ds_addr = VM_PAGE_TO_PHYS(m);
1062 segs[curseg].ds_len = PAGE_SIZE;
1063 #ifdef DEBUG_DMA
1064 printf("alloc: page %lx\n", lastaddr);
1065 #endif /* DEBUG_DMA */
1066 m = TAILQ_NEXT(m, pageq);
1067
1068 for (; m != NULL; m = TAILQ_NEXT(m, pageq)) {
1069 curaddr = VM_PAGE_TO_PHYS(m);
1070 #ifdef DIAGNOSTIC
1071 if (curaddr < low || curaddr >= high) {
1072 printf("uvm_pglistalloc returned non-sensical"
1073 " address 0x%lx\n", curaddr);
1074 panic("_bus_dmamem_alloc_range");
1075 }
1076 #endif /* DIAGNOSTIC */
1077 #ifdef DEBUG_DMA
1078 printf("alloc: page %lx\n", curaddr);
1079 #endif /* DEBUG_DMA */
1080 if (curaddr == (lastaddr + PAGE_SIZE))
1081 segs[curseg].ds_len += PAGE_SIZE;
1082 else {
1083 curseg++;
1084 segs[curseg].ds_addr = curaddr;
1085 segs[curseg].ds_len = PAGE_SIZE;
1086 }
1087 lastaddr = curaddr;
1088 }
1089
1090 *rsegs = curseg + 1;
1091
1092 return (0);
1093 }
1094
1095 /*
1096 * probably should be ppc_space_copy
1097 */
1098
1099 #define _CONCAT(A,B) A ## B
1100 #define __C(A,B) _CONCAT(A,B)
1101
1102 #define BUS_SPACE_READ_RAW_MULTI_N(BYTES,SHIFT,TYPE) \
1103 void \
1104 __C(bus_space_read_raw_multi_,BYTES)(bus_space_tag_t bst, \
1105 bus_space_handle_t h, bus_addr_t o, u_int8_t *dst, bus_size_t size) \
1106 { \
1107 TYPE *rdst = (TYPE *)dst; \
1108 int i; \
1109 int count = size >> SHIFT; \
1110 \
1111 for (i = 0; i < count; i++) { \
1112 rdst[i] = __bs_rs(BYTES, bst, h, o); \
1113 } \
1114 }
1115 BUS_SPACE_READ_RAW_MULTI_N(2,1,u_int16_t)
1116 BUS_SPACE_READ_RAW_MULTI_N(4,2,u_int32_t)
1117
1118 #define BUS_SPACE_WRITE_RAW_MULTI_N(BYTES,SHIFT,TYPE) \
1119 void \
1120 __C(bus_space_write_raw_multi_,BYTES)( bus_space_tag_t bst, \
1121 bus_space_handle_t h, bus_addr_t o, const u_int8_t *src, \
1122 bus_size_t size) \
1123 { \
1124 int i; \
1125 TYPE *rsrc = (TYPE *)src; \
1126 int count = size >> SHIFT; \
1127 \
1128 for (i = 0; i < count; i++) { \
1129 __bs_ws(BYTES, bst, h, o, rsrc[i]); \
1130 } \
1131 }
1132
1133 BUS_SPACE_WRITE_RAW_MULTI_N(2,1,u_int16_t)
1134 BUS_SPACE_WRITE_RAW_MULTI_N(4,2,u_int32_t)
1135