1 /* $NetBSD: mesong12_aoclkc.c,v 1.3 2024/02/07 04:20:26 msaitoh Exp $ */
2
3 /*
4 * Copyright (c) 2021 Ryo Shimizu
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
17 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: mesong12_aoclkc.c,v 1.3 2024/02/07 04:20:26 msaitoh Exp $");
31
32 #include <sys/param.h>
33 #include <sys/types.h>
34 #include <sys/bus.h>
35 #include <sys/device.h>
36
37 #include <dev/fdt/fdtvar.h>
38
39 #include <arm/amlogic/meson_clk.h>
40 #include <arm/amlogic/mesong12_aoclkc.h>
41
42 #define AO_SOFT_RESET_REG 0x40
43 #define AO_DOMAIN_CLOCK_GATEING0_REG 0x4c
44 #define AO_DOMAIN_CLOCK_GATEING1_REG 0x50
45
46 #define GATE_PARENT "mpeg-clk"
47
48 static int mesong12_aoclkc_match(device_t, cfdata_t, void *);
49 static void mesong12_aoclkc_attach(device_t, device_t, void *);
50
51 static const struct device_compatible_entry compat_data[] = {
52 { .compat = "amlogic,meson-g12a-aoclkc" },
53 DEVICE_COMPAT_EOL
54 };
55
56 CFATTACH_DECL_NEW(mesong12_aoclkc, sizeof(struct meson_clk_softc),
57 mesong12_aoclkc_match, mesong12_aoclkc_attach, NULL, NULL);
58
59 static struct meson_clk_reset mesong12_aoclkc_resets[] = {
60 MESON_CLK_RESET(MESONG12_RESET_AO_IR_IN, AO_SOFT_RESET_REG, 16),
61 MESON_CLK_RESET(MESONG12_RESET_AO_UART, AO_SOFT_RESET_REG, 17),
62 MESON_CLK_RESET(MESONG12_RESET_AO_I2C_M, AO_SOFT_RESET_REG, 18),
63 MESON_CLK_RESET(MESONG12_RESET_AO_I2C_S, AO_SOFT_RESET_REG, 19),
64 MESON_CLK_RESET(MESONG12_RESET_AO_SAR_ADC, AO_SOFT_RESET_REG, 20),
65 MESON_CLK_RESET(MESONG12_RESET_AO_UART2, AO_SOFT_RESET_REG, 22),
66 MESON_CLK_RESET(MESONG12_RESET_AO_IR_OUT, AO_SOFT_RESET_REG, 23),
67 };
68
69 static struct meson_clk_clk mesong12_aoclkc_clks[] = {
70 MESON_CLK_GATE(MESONG12_CLOCK_AO_AHB, "ahb_ao",
71 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING0_REG, 0),
72 MESON_CLK_GATE(MESONG12_CLOCK_AO_IR_IN,"ir_in_ao",
73 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING0_REG, 1),
74 MESON_CLK_GATE(MESONG12_CLOCK_AO_I2C_M0, "i2c_m0_ao",
75 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING0_REG, 2),
76 MESON_CLK_GATE(MESONG12_CLOCK_AO_I2C_S0, "i2c_s0_ao",
77 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING0_REG, 3),
78 MESON_CLK_GATE(MESONG12_CLOCK_AO_UART, "uart_ao",
79 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING0_REG, 4),
80 MESON_CLK_GATE(MESONG12_CLOCK_AO_PROD_I2C, "prod_i2c_ao",
81 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING0_REG, 5),
82 MESON_CLK_GATE(MESONG12_CLOCK_AO_UART2, "uart2_ao",
83 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING0_REG, 6),
84 MESON_CLK_GATE(MESONG12_CLOCK_AO_IR_OUT, "ir_out_ao",
85 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING0_REG, 7),
86 MESON_CLK_GATE(MESONG12_CLOCK_AO_SAR_ADC, "sar_adc_ao",
87 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING0_REG, 8),
88 MESON_CLK_GATE(MESONG12_CLOCK_AO_MAILBOX, "mailbox_ao",
89 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING1_REG, 0),
90 MESON_CLK_GATE(MESONG12_CLOCK_AO_M3, "m3_ao",
91 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING1_REG, 1),
92 MESON_CLK_GATE(MESONG12_CLOCK_AO_AHB_SRAM, "ahb_sram_ao",
93 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING1_REG, 2),
94 MESON_CLK_GATE(MESONG12_CLOCK_AO_RTI, "rti_ao",
95 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING1_REG, 3),
96 MESON_CLK_GATE(MESONG12_CLOCK_AO_M4_FCLK, "m4_fclk_ao",
97 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING1_REG, 4),
98 MESON_CLK_GATE(MESONG12_CLOCK_AO_M4_HCLK, "m4_hclk_ao",
99 GATE_PARENT, AO_DOMAIN_CLOCK_GATEING1_REG, 5),
100 };
101
102 static int
mesong12_aoclkc_match(device_t parent,cfdata_t cf,void * aux)103 mesong12_aoclkc_match(device_t parent, cfdata_t cf, void *aux)
104 {
105 struct fdt_attach_args * const faa = aux;
106
107 return of_compatible_match(faa->faa_phandle, compat_data);
108 }
109
110 static void
mesong12_aoclkc_attach(device_t parent,device_t self,void * aux)111 mesong12_aoclkc_attach(device_t parent, device_t self, void *aux)
112 {
113 struct meson_clk_softc * const sc = device_private(self);
114 struct fdt_attach_args * const faa = aux;
115
116 sc->sc_dev = self;
117 sc->sc_phandle = faa->faa_phandle;
118 sc->sc_syscon = fdtbus_syscon_lookup(OF_parent(sc->sc_phandle));
119 if (sc->sc_syscon == NULL) {
120 aprint_error(": couldn't get syscon registers\n");
121 return;
122 }
123
124 sc->sc_resets = mesong12_aoclkc_resets;
125 sc->sc_nresets = __arraycount(mesong12_aoclkc_resets);
126
127 sc->sc_clks = mesong12_aoclkc_clks;
128 sc->sc_nclks = __arraycount(mesong12_aoclkc_clks);
129
130 aprint_naive("\n");
131 aprint_normal(": Meson G12A AO clock controller\n");
132
133 meson_clk_attach(sc);
134 meson_clk_print(sc);
135 }
136