xref: /plan9-contrib/sys/src/9k/k10/apic.h (revision 9ef1f84b659abcb917c5c090acbce0772e494f21)
1 /*
2  * There are 2 flavours of APIC, Local APIC and IOAPIC,
3  * which don't necessarily share one APIC ID space.
4  * Each IOAPIC has a unique address, Local APICs are all
5  * at the same address as they can only be accessed by
6  * the local CPU.
7 To do: probably split this into 2 structs, Apic and IOApic;
8 	x2APIC...
9  */
10 typedef struct {
11 	int	useable;			/* en */
12 
13 	Lock;					/* IOAPIC: register access */
14 	u32int*	addr;				/* IOAPIC: register base */
15 	int	nrdt;				/* IOAPIC: size of RDT */
16 	int	gsib;				/* IOAPIC: global RDT index */
17 
18 	int	machno;				/* APIC */
19 	u32int	lvt[10];
20 	int	nlvt;
21 	int	ver;				/* unused */
22 
23 	vlong	hz;				/* APIC Timer frequency */
24 	vlong	max;
25 	vlong	min;
26 	vlong	div;
27 } Apic;
28 
29 enum {
30 	Nbus		= 256,
31 	Napic		= 254,			/* xAPIC architectural limit */
32 	Nrdt		= 64,
33 };
34 
35 /*
36  * Common bits for
37  *	IOAPIC Redirection Table Entry (RDT);
38  *	APIC Local Vector Table Entry (LVT);
39  *	APIC Interrupt Command Register (ICR).
40  * [10:8] Message Type
41  * [11] Destination Mode (RW)
42  * [12] Delivery Status (RO)
43  * [13] Interrupt Input Pin Polarity (RW)
44  * [14] Remote IRR (RO)
45  * [15] Trigger Mode (RW)
46  * [16] Interrupt Mask
47  */
48 enum {
49 	MTf		= 0x00000000,		/* Fixed */
50 	MTlp		= 0x00000100,		/* Lowest Priority */
51 	MTsmi		= 0x00000200,		/* SMI */
52 	MTrr		= 0x00000300,		/* Remote Read */
53 	MTnmi		= 0x00000400,		/* NMI */
54 	MTir		= 0x00000500,		/* INIT/RESET */
55 	MTsipi		= 0x00000600,		/* Startup IPI */
56 	MTei		= 0x00000700,		/* ExtINT */
57 
58 	Pm		= 0x00000000,		/* Physical Mode */
59 	Lm		= 0x00000800,		/* Logical Mode */
60 
61 	Ds		= 0x00001000,		/* Delivery Status */
62 	IPhigh		= 0x00000000,		/* IIPP High */
63 	IPlow		= 0x00002000,		/* IIPP Low */
64 	Rirr		= 0x00004000,		/* Remote IRR Status */
65 	TMedge		= 0x00000000,		/* Trigger Mode Edge */
66 	TMlevel		= 0x00008000,		/* Trigger Mode Level */
67 	Im		= 0x00010000,		/* Interrupt Mask */
68 };
69 
70 Apic xapic[Napic];
71 Apic ioapic[Napic];
72 
73 #define l16get(p)	(((p)[1]<<8)|(p)[0])
74 #define	l32get(p)	(((u32int)l16get(p+2)<<16)|l16get(p))
75 #define	l64get(p)	(((u64int)l32get(p+4)<<32)|l32get(p))
76 
77 extern void apicdump(void);
78 extern void ioapicdump(void);
79