1 /* $NetBSD: amdgpu_vega20_baco.c,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */
2
3 /*
4 * Copyright 2018 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25 #include <sys/cdefs.h>
26 __KERNEL_RCSID(0, "$NetBSD: amdgpu_vega20_baco.c,v 1.2 2021/12/18 23:45:26 riastradh Exp $");
27
28 #include "amdgpu.h"
29 #include "soc15.h"
30 #include "soc15_hw_ip.h"
31 #include "soc15_common.h"
32 #include "vega20_inc.h"
33 #include "vega20_ppsmc.h"
34 #include "vega20_baco.h"
35 #include "vega20_smumgr.h"
36
37 #include "amdgpu_ras.h"
38
39 static const struct soc15_baco_cmd_entry clean_baco_tbl[] =
40 {
41 {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0},
42 {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_7), 0, 0, 0, 0},
43 };
44
vega20_baco_get_capability(struct pp_hwmgr * hwmgr,bool * cap)45 int vega20_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
46 {
47 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
48 uint32_t reg;
49
50 *cap = false;
51 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
52 return 0;
53
54 if (((RREG32(0x17569) & 0x20000000) >> 29) == 0x1) {
55 reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);
56
57 if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
58 *cap = true;
59 }
60
61 return 0;
62 }
63
vega20_baco_get_state(struct pp_hwmgr * hwmgr,enum BACO_STATE * state)64 int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
65 {
66 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
67 uint32_t reg;
68
69 reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);
70
71 if (reg & BACO_CNTL__BACO_MODE_MASK)
72 /* gfx has already entered BACO state */
73 *state = BACO_STATE_IN;
74 else
75 *state = BACO_STATE_OUT;
76 return 0;
77 }
78
vega20_baco_set_state(struct pp_hwmgr * hwmgr,enum BACO_STATE state)79 int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
80 {
81 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
82 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
83 enum BACO_STATE cur_state;
84 uint32_t data;
85
86 vega20_baco_get_state(hwmgr, &cur_state);
87
88 if (cur_state == state)
89 /* aisc already in the target state */
90 return 0;
91
92 if (state == BACO_STATE_IN) {
93 if (!ras || !ras->supported) {
94 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
95 data |= 0x80000000;
96 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
97
98 if(smum_send_msg_to_smc_with_parameter(hwmgr,
99 PPSMC_MSG_EnterBaco, 0))
100 return -EINVAL;
101 } else {
102 if(smum_send_msg_to_smc_with_parameter(hwmgr,
103 PPSMC_MSG_EnterBaco, 1))
104 return -EINVAL;
105 }
106
107 } else if (state == BACO_STATE_OUT) {
108 if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ExitBaco))
109 return -EINVAL;
110 if (!soc15_baco_program_registers(hwmgr, clean_baco_tbl,
111 ARRAY_SIZE(clean_baco_tbl)))
112 return -EINVAL;
113 }
114
115 return 0;
116 }
117
vega20_baco_apply_vdci_flush_workaround(struct pp_hwmgr * hwmgr)118 int vega20_baco_apply_vdci_flush_workaround(struct pp_hwmgr *hwmgr)
119 {
120 int ret = 0;
121
122 ret = vega20_set_pptable_driver_address(hwmgr);
123 if (ret)
124 return ret;
125
126 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_BacoWorkAroundFlushVDCI);
127 }
128