1 /* $NetBSD: amdgpu_vega10_thermal.c,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */
2
3 /*
4 * Copyright 2016 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_vega10_thermal.c,v 1.2 2021/12/18 23:45:26 riastradh Exp $");
28
29 #include "vega10_thermal.h"
30 #include "vega10_hwmgr.h"
31 #include "vega10_smumgr.h"
32 #include "vega10_ppsmc.h"
33 #include "vega10_inc.h"
34 #include "soc15_common.h"
35 #include "pp_debug.h"
36
vega10_get_current_rpm(struct pp_hwmgr * hwmgr,uint32_t * current_rpm)37 static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
38 {
39 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentRpm);
40 *current_rpm = smum_get_argument(hwmgr);
41 return 0;
42 }
43
vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr * hwmgr,struct phm_fan_speed_info * fan_speed_info)44 int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
45 struct phm_fan_speed_info *fan_speed_info)
46 {
47
48 if (hwmgr->thermal_controller.fanInfo.bNoFan)
49 return 0;
50
51 fan_speed_info->supports_percent_read = true;
52 fan_speed_info->supports_percent_write = true;
53 fan_speed_info->min_percent = 0;
54 fan_speed_info->max_percent = 100;
55
56 if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
57 hwmgr->thermal_controller.fanInfo.
58 ucTachometerPulsesPerRevolution) {
59 fan_speed_info->supports_rpm_read = true;
60 fan_speed_info->supports_rpm_write = true;
61 fan_speed_info->min_rpm =
62 hwmgr->thermal_controller.fanInfo.ulMinRPM;
63 fan_speed_info->max_rpm =
64 hwmgr->thermal_controller.fanInfo.ulMaxRPM;
65 } else {
66 fan_speed_info->min_rpm = 0;
67 fan_speed_info->max_rpm = 0;
68 }
69
70 return 0;
71 }
72
vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr * hwmgr,uint32_t * speed)73 int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
74 uint32_t *speed)
75 {
76 uint32_t current_rpm;
77 uint32_t percent = 0;
78
79 if (hwmgr->thermal_controller.fanInfo.bNoFan)
80 return 0;
81
82 if (vega10_get_current_rpm(hwmgr, ¤t_rpm))
83 return -1;
84
85 if (hwmgr->thermal_controller.
86 advanceFanControlParameters.usMaxFanRPM != 0)
87 percent = current_rpm * 100 /
88 hwmgr->thermal_controller.
89 advanceFanControlParameters.usMaxFanRPM;
90
91 *speed = percent > 100 ? 100 : percent;
92
93 return 0;
94 }
95
vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr * hwmgr,uint32_t * speed)96 int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
97 {
98 struct amdgpu_device *adev = hwmgr->adev;
99 struct vega10_hwmgr *data = hwmgr->backend;
100 uint32_t tach_period;
101 uint32_t crystal_clock_freq;
102 int result = 0;
103
104 if (hwmgr->thermal_controller.fanInfo.bNoFan)
105 return -1;
106
107 if (data->smu_features[GNLD_FAN_CONTROL].supported) {
108 result = vega10_get_current_rpm(hwmgr, speed);
109 } else {
110 tach_period =
111 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS),
112 CG_TACH_STATUS,
113 TACH_PERIOD);
114
115 if (tach_period == 0)
116 return -EINVAL;
117
118 crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
119
120 *speed = 60 * crystal_clock_freq * 10000 / tach_period;
121 }
122
123 return result;
124 }
125
126 /**
127 * Set Fan Speed Control to static mode,
128 * so that the user can decide what speed to use.
129 * @param hwmgr the address of the powerplay hardware manager.
130 * mode the fan control mode, 0 default, 1 by percent, 5, by RPM
131 * @exception Should always succeed.
132 */
vega10_fan_ctrl_set_static_mode(struct pp_hwmgr * hwmgr,uint32_t mode)133 int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
134 {
135 struct amdgpu_device *adev = hwmgr->adev;
136
137 if (hwmgr->fan_ctrl_is_in_default_mode) {
138 hwmgr->fan_ctrl_default_mode =
139 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
140 CG_FDO_CTRL2, FDO_PWM_MODE);
141 hwmgr->tmin =
142 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
143 CG_FDO_CTRL2, TMIN);
144 hwmgr->fan_ctrl_is_in_default_mode = false;
145 }
146
147 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
148 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
149 CG_FDO_CTRL2, TMIN, 0));
150 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
151 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
152 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
153
154 return 0;
155 }
156
157 /**
158 * Reset Fan Speed Control to default mode.
159 * @param hwmgr the address of the powerplay hardware manager.
160 * @exception Should always succeed.
161 */
vega10_fan_ctrl_set_default_mode(struct pp_hwmgr * hwmgr)162 int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
163 {
164 struct amdgpu_device *adev = hwmgr->adev;
165
166 if (!hwmgr->fan_ctrl_is_in_default_mode) {
167 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
168 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
169 CG_FDO_CTRL2, FDO_PWM_MODE,
170 hwmgr->fan_ctrl_default_mode));
171 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
172 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
173 CG_FDO_CTRL2, TMIN,
174 hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT));
175 hwmgr->fan_ctrl_is_in_default_mode = true;
176 }
177
178 return 0;
179 }
180
181 /**
182 * @fn vega10_enable_fan_control_feature
183 * @brief Enables the SMC Fan Control Feature.
184 *
185 * @param hwmgr - the address of the powerplay hardware manager.
186 * @return 0 on success. -1 otherwise.
187 */
vega10_enable_fan_control_feature(struct pp_hwmgr * hwmgr)188 static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
189 {
190 struct vega10_hwmgr *data = hwmgr->backend;
191
192 if (data->smu_features[GNLD_FAN_CONTROL].supported) {
193 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
194 hwmgr, true,
195 data->smu_features[GNLD_FAN_CONTROL].
196 smu_feature_bitmap),
197 "Attempt to Enable FAN CONTROL feature Failed!",
198 return -1);
199 data->smu_features[GNLD_FAN_CONTROL].enabled = true;
200 }
201
202 return 0;
203 }
204
vega10_disable_fan_control_feature(struct pp_hwmgr * hwmgr)205 static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
206 {
207 struct vega10_hwmgr *data = hwmgr->backend;
208
209 if (data->smu_features[GNLD_FAN_CONTROL].supported) {
210 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
211 hwmgr, false,
212 data->smu_features[GNLD_FAN_CONTROL].
213 smu_feature_bitmap),
214 "Attempt to Enable FAN CONTROL feature Failed!",
215 return -1);
216 data->smu_features[GNLD_FAN_CONTROL].enabled = false;
217 }
218
219 return 0;
220 }
221
vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr * hwmgr)222 int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
223 {
224 if (hwmgr->thermal_controller.fanInfo.bNoFan)
225 return -1;
226
227 PP_ASSERT_WITH_CODE(!vega10_enable_fan_control_feature(hwmgr),
228 "Attempt to Enable SMC FAN CONTROL Feature Failed!",
229 return -1);
230
231 return 0;
232 }
233
234
vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr * hwmgr)235 int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
236 {
237 struct vega10_hwmgr *data = hwmgr->backend;
238
239 if (hwmgr->thermal_controller.fanInfo.bNoFan)
240 return -1;
241
242 if (data->smu_features[GNLD_FAN_CONTROL].supported) {
243 PP_ASSERT_WITH_CODE(!vega10_disable_fan_control_feature(hwmgr),
244 "Attempt to Disable SMC FAN CONTROL Feature Failed!",
245 return -1);
246 }
247 return 0;
248 }
249
250 /**
251 * Set Fan Speed in percent.
252 * @param hwmgr the address of the powerplay hardware manager.
253 * @param speed is the percentage value (0% - 100%) to be set.
254 * @exception Fails is the 100% setting appears to be 0.
255 */
vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr * hwmgr,uint32_t speed)256 int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
257 uint32_t speed)
258 {
259 struct amdgpu_device *adev = hwmgr->adev;
260 uint32_t duty100;
261 uint32_t duty;
262 uint64_t tmp64;
263
264 if (hwmgr->thermal_controller.fanInfo.bNoFan)
265 return 0;
266
267 if (speed > 100)
268 speed = 100;
269
270 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
271 vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
272
273 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
274 CG_FDO_CTRL1, FMAX_DUTY100);
275
276 if (duty100 == 0)
277 return -EINVAL;
278
279 tmp64 = (uint64_t)speed * duty100;
280 do_div(tmp64, 100);
281 duty = (uint32_t)tmp64;
282
283 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
284 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
285 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
286
287 return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
288 }
289
290 /**
291 * Reset Fan Speed to default.
292 * @param hwmgr the address of the powerplay hardware manager.
293 * @exception Always succeeds.
294 */
vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr * hwmgr)295 int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
296 {
297 if (hwmgr->thermal_controller.fanInfo.bNoFan)
298 return 0;
299
300 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
301 return vega10_fan_ctrl_start_smc_fan_control(hwmgr);
302 else
303 return vega10_fan_ctrl_set_default_mode(hwmgr);
304 }
305
306 /**
307 * Set Fan Speed in RPM.
308 * @param hwmgr the address of the powerplay hardware manager.
309 * @param speed is the percentage value (min - max) to be set.
310 * @exception Fails is the speed not lie between min and max.
311 */
vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr * hwmgr,uint32_t speed)312 int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
313 {
314 struct amdgpu_device *adev = hwmgr->adev;
315 uint32_t tach_period;
316 uint32_t crystal_clock_freq;
317 int result = 0;
318
319 if (hwmgr->thermal_controller.fanInfo.bNoFan ||
320 speed == 0 ||
321 (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
322 (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
323 return -1;
324
325 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
326 result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
327
328 if (!result) {
329 crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
330 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
331 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
332 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
333 CG_TACH_CTRL, TARGET_PERIOD,
334 tach_period));
335 }
336 return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
337 }
338
339 /**
340 * Reads the remote temperature from the SIslands thermal controller.
341 *
342 * @param hwmgr The address of the hardware manager.
343 */
vega10_thermal_get_temperature(struct pp_hwmgr * hwmgr)344 int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
345 {
346 struct amdgpu_device *adev = hwmgr->adev;
347 int temp;
348
349 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
350
351 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
352 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
353
354 temp = temp & 0x1ff;
355
356 temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
357
358 return temp;
359 }
360
361 /**
362 * Set the requested temperature range for high and low alert signals
363 *
364 * @param hwmgr The address of the hardware manager.
365 * @param range Temperature range to be programmed for
366 * high and low alert signals
367 * @exception PP_Result_BadInput if the input data is not valid.
368 */
vega10_thermal_set_temperature_range(struct pp_hwmgr * hwmgr,struct PP_TemperatureRange * range)369 static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
370 struct PP_TemperatureRange *range)
371 {
372 struct amdgpu_device *adev = hwmgr->adev;
373 int low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP *
374 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
375 int high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP *
376 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
377 uint32_t val;
378
379 if (low < range->min)
380 low = range->min;
381 if (high > range->max)
382 high = range->max;
383
384 if (low > high)
385 return -EINVAL;
386
387 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
388
389 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
390 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
391 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
392 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
393 val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) &
394 (~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK) &
395 (~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
396
397 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
398
399 return 0;
400 }
401
402 /**
403 * Programs thermal controller one-time setting registers
404 *
405 * @param hwmgr The address of the hardware manager.
406 */
vega10_thermal_initialize(struct pp_hwmgr * hwmgr)407 static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
408 {
409 struct amdgpu_device *adev = hwmgr->adev;
410
411 if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
412 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
413 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
414 CG_TACH_CTRL, EDGE_PER_REV,
415 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution - 1));
416 }
417
418 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
419 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
420 CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28));
421
422 return 0;
423 }
424
425 /**
426 * Enable thermal alerts on the RV770 thermal controller.
427 *
428 * @param hwmgr The address of the hardware manager.
429 */
vega10_thermal_enable_alert(struct pp_hwmgr * hwmgr)430 static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
431 {
432 struct amdgpu_device *adev = hwmgr->adev;
433 struct vega10_hwmgr *data = hwmgr->backend;
434 uint32_t val = 0;
435
436 if (data->smu_features[GNLD_FW_CTF].supported) {
437 if (data->smu_features[GNLD_FW_CTF].enabled)
438 printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n");
439
440 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
441 true,
442 data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
443 "Attempt to Enable FW CTF feature Failed!",
444 return -1);
445 data->smu_features[GNLD_FW_CTF].enabled = true;
446 }
447
448 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
449 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
450 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
451
452 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
453
454 return 0;
455 }
456
457 /**
458 * Disable thermal alerts on the RV770 thermal controller.
459 * @param hwmgr The address of the hardware manager.
460 */
vega10_thermal_disable_alert(struct pp_hwmgr * hwmgr)461 int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
462 {
463 struct amdgpu_device *adev = hwmgr->adev;
464 struct vega10_hwmgr *data = hwmgr->backend;
465
466 if (data->smu_features[GNLD_FW_CTF].supported) {
467 if (!data->smu_features[GNLD_FW_CTF].enabled)
468 printk("[Thermal_EnableAlert] FW CTF Already disabled!\n");
469
470
471 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
472 false,
473 data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
474 "Attempt to disable FW CTF feature Failed!",
475 return -1);
476 data->smu_features[GNLD_FW_CTF].enabled = false;
477 }
478
479 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
480
481 return 0;
482 }
483
484 /**
485 * Uninitialize the thermal controller.
486 * Currently just disables alerts.
487 * @param hwmgr The address of the hardware manager.
488 */
vega10_thermal_stop_thermal_controller(struct pp_hwmgr * hwmgr)489 int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
490 {
491 int result = vega10_thermal_disable_alert(hwmgr);
492
493 if (!hwmgr->thermal_controller.fanInfo.bNoFan)
494 vega10_fan_ctrl_set_default_mode(hwmgr);
495
496 return result;
497 }
498
499 /**
500 * Set up the fan table to control the fan using the SMC.
501 * @param hwmgr the address of the powerplay hardware manager.
502 * @param pInput the pointer to input data
503 * @param pOutput the pointer to output data
504 * @param pStorage the pointer to temporary storage
505 * @param Result the last failure code
506 * @return result from set temperature range routine
507 */
vega10_thermal_setup_fan_table(struct pp_hwmgr * hwmgr)508 int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
509 {
510 int ret;
511 struct vega10_hwmgr *data = hwmgr->backend;
512 PPTable_t *table = &(data->smc_state_table.pp_table);
513
514 if (!data->smu_features[GNLD_FAN_CONTROL].supported)
515 return 0;
516
517 table->FanMaximumRpm = (uint16_t)hwmgr->thermal_controller.
518 advanceFanControlParameters.usMaxFanRPM;
519 table->FanThrottlingRpm = hwmgr->thermal_controller.
520 advanceFanControlParameters.usFanRPMMaxLimit;
521 table->FanAcousticLimitRpm = (uint16_t)(hwmgr->thermal_controller.
522 advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
523 table->FanTargetTemperature = hwmgr->thermal_controller.
524 advanceFanControlParameters.usTMax;
525
526 smum_send_msg_to_smc_with_parameter(hwmgr,
527 PPSMC_MSG_SetFanTemperatureTarget,
528 (uint32_t)table->FanTargetTemperature);
529
530 table->FanPwmMin = hwmgr->thermal_controller.
531 advanceFanControlParameters.usPWMMin * 255 / 100;
532 table->FanTargetGfxclk = (uint16_t)(hwmgr->thermal_controller.
533 advanceFanControlParameters.ulTargetGfxClk);
534 table->FanGainEdge = hwmgr->thermal_controller.
535 advanceFanControlParameters.usFanGainEdge;
536 table->FanGainHotspot = hwmgr->thermal_controller.
537 advanceFanControlParameters.usFanGainHotspot;
538 table->FanGainLiquid = hwmgr->thermal_controller.
539 advanceFanControlParameters.usFanGainLiquid;
540 table->FanGainVrVddc = hwmgr->thermal_controller.
541 advanceFanControlParameters.usFanGainVrVddc;
542 table->FanGainVrMvdd = hwmgr->thermal_controller.
543 advanceFanControlParameters.usFanGainVrMvdd;
544 table->FanGainPlx = hwmgr->thermal_controller.
545 advanceFanControlParameters.usFanGainPlx;
546 table->FanGainHbm = hwmgr->thermal_controller.
547 advanceFanControlParameters.usFanGainHbm;
548 table->FanZeroRpmEnable = hwmgr->thermal_controller.
549 advanceFanControlParameters.ucEnableZeroRPM;
550 table->FanStopTemp = hwmgr->thermal_controller.
551 advanceFanControlParameters.usZeroRPMStopTemperature;
552 table->FanStartTemp = hwmgr->thermal_controller.
553 advanceFanControlParameters.usZeroRPMStartTemperature;
554
555 ret = smum_smc_table_manager(hwmgr,
556 (uint8_t *)(&(data->smc_state_table.pp_table)),
557 PPTABLE, false);
558 if (ret)
559 pr_info("Failed to update Fan Control Table in PPTable!");
560
561 return ret;
562 }
563
vega10_enable_mgpu_fan_boost(struct pp_hwmgr * hwmgr)564 int vega10_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
565 {
566 struct vega10_hwmgr *data = hwmgr->backend;
567 PPTable_t *table = &(data->smc_state_table.pp_table);
568 int ret;
569
570 if (!data->smu_features[GNLD_FAN_CONTROL].supported)
571 return 0;
572
573 if (!hwmgr->thermal_controller.advanceFanControlParameters.
574 usMGpuThrottlingRPMLimit)
575 return 0;
576
577 table->FanThrottlingRpm = hwmgr->thermal_controller.
578 advanceFanControlParameters.usMGpuThrottlingRPMLimit;
579
580 ret = smum_smc_table_manager(hwmgr,
581 (uint8_t *)(&(data->smc_state_table.pp_table)),
582 PPTABLE, false);
583 if (ret) {
584 pr_info("Failed to update fan control table in pptable!");
585 return ret;
586 }
587
588 ret = vega10_disable_fan_control_feature(hwmgr);
589 if (ret) {
590 pr_info("Attempt to disable SMC fan control feature failed!");
591 return ret;
592 }
593
594 ret = vega10_enable_fan_control_feature(hwmgr);
595 if (ret)
596 pr_info("Attempt to enable SMC fan control feature failed!");
597
598 return ret;
599 }
600
601 /**
602 * Start the fan control on the SMC.
603 * @param hwmgr the address of the powerplay hardware manager.
604 * @param pInput the pointer to input data
605 * @param pOutput the pointer to output data
606 * @param pStorage the pointer to temporary storage
607 * @param Result the last failure code
608 * @return result from set temperature range routine
609 */
vega10_thermal_start_smc_fan_control(struct pp_hwmgr * hwmgr)610 int vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
611 {
612 /* If the fantable setup has failed we could have disabled
613 * PHM_PlatformCaps_MicrocodeFanControl even after
614 * this function was included in the table.
615 * Make sure that we still think controlling the fan is OK.
616 */
617 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
618 vega10_fan_ctrl_start_smc_fan_control(hwmgr);
619
620 return 0;
621 }
622
623
vega10_start_thermal_controller(struct pp_hwmgr * hwmgr,struct PP_TemperatureRange * range)624 int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr,
625 struct PP_TemperatureRange *range)
626 {
627 int ret = 0;
628
629 if (range == NULL)
630 return -EINVAL;
631
632 vega10_thermal_initialize(hwmgr);
633 ret = vega10_thermal_set_temperature_range(hwmgr, range);
634 if (ret)
635 return -EINVAL;
636
637 vega10_thermal_enable_alert(hwmgr);
638 /* We should restrict performance levels to low before we halt the SMC.
639 * On the other hand we are still in boot state when we do this
640 * so it would be pointless.
641 * If this assumption changes we have to revisit this table.
642 */
643 ret = vega10_thermal_setup_fan_table(hwmgr);
644 if (ret)
645 return -EINVAL;
646
647 vega10_thermal_start_smc_fan_control(hwmgr);
648
649 return 0;
650 };
651
652
653
654
vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr * hwmgr)655 int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
656 {
657 if (!hwmgr->thermal_controller.fanInfo.bNoFan) {
658 vega10_fan_ctrl_set_default_mode(hwmgr);
659 vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
660 }
661 return 0;
662 }
663