1 /* $NetBSD: amdgpu_smu9_baco.c,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */
2
3 /*
4 * Copyright 2018 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25 #include <sys/cdefs.h>
26 __KERNEL_RCSID(0, "$NetBSD: amdgpu_smu9_baco.c,v 1.2 2021/12/18 23:45:26 riastradh Exp $");
27
28 #include "amdgpu.h"
29 #include "soc15.h"
30 #include "soc15_hw_ip.h"
31 #include "vega10_ip_offset.h"
32 #include "soc15_common.h"
33 #include "vega10_inc.h"
34 #include "smu9_baco.h"
35
smu9_baco_get_capability(struct pp_hwmgr * hwmgr,bool * cap)36 int smu9_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
37 {
38 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
39 uint32_t reg, data;
40
41 *cap = false;
42 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
43 return 0;
44
45 WREG32(0x12074, 0xFFF0003B);
46 data = RREG32(0x12075);
47
48 if (data == 0x1) {
49 reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);
50
51 if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
52 *cap = true;
53 }
54
55 return 0;
56 }
57
smu9_baco_get_state(struct pp_hwmgr * hwmgr,enum BACO_STATE * state)58 int smu9_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
59 {
60 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
61 uint32_t reg;
62
63 reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);
64
65 if (reg & BACO_CNTL__BACO_MODE_MASK)
66 /* gfx has already entered BACO state */
67 *state = BACO_STATE_IN;
68 else
69 *state = BACO_STATE_OUT;
70 return 0;
71 }
72