1 /* $NetBSD: amdgpu_smu7_baco.c,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */
2
3 /*
4 * Copyright 2019 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25 #include <sys/cdefs.h>
26 __KERNEL_RCSID(0, "$NetBSD: amdgpu_smu7_baco.c,v 1.2 2021/12/18 23:45:26 riastradh Exp $");
27
28 #include "amdgpu.h"
29 #include "smu7_baco.h"
30 #include "tonga_baco.h"
31 #include "fiji_baco.h"
32 #include "polaris_baco.h"
33 #include "ci_baco.h"
34
35 #include "bif/bif_5_0_d.h"
36 #include "bif/bif_5_0_sh_mask.h"
37
38 #include "smu/smu_7_1_2_d.h"
39 #include "smu/smu_7_1_2_sh_mask.h"
40
smu7_baco_get_capability(struct pp_hwmgr * hwmgr,bool * cap)41 int smu7_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
42 {
43 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
44 uint32_t reg;
45
46 *cap = false;
47 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
48 return 0;
49
50 reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
51
52 if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
53 *cap = true;
54
55 return 0;
56 }
57
smu7_baco_get_state(struct pp_hwmgr * hwmgr,enum BACO_STATE * state)58 int smu7_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
59 {
60 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
61 uint32_t reg;
62
63 reg = RREG32(mmBACO_CNTL);
64
65 if (reg & BACO_CNTL__BACO_MODE_MASK)
66 /* gfx has already entered BACO state */
67 *state = BACO_STATE_IN;
68 else
69 *state = BACO_STATE_OUT;
70 return 0;
71 }
72
smu7_baco_set_state(struct pp_hwmgr * hwmgr,enum BACO_STATE state)73 int smu7_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
74 {
75 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
76
77 switch (adev->asic_type) {
78 case CHIP_TOPAZ:
79 case CHIP_TONGA:
80 return tonga_baco_set_state(hwmgr, state);
81 case CHIP_FIJI:
82 return fiji_baco_set_state(hwmgr, state);
83 case CHIP_POLARIS10:
84 case CHIP_POLARIS11:
85 case CHIP_POLARIS12:
86 case CHIP_VEGAM:
87 return polaris_baco_set_state(hwmgr, state);
88 #ifdef CONFIG_DRM_AMDGPU_CIK
89 case CHIP_BONAIRE:
90 case CHIP_HAWAII:
91 return ci_baco_set_state(hwmgr, state);
92 #endif
93 default:
94 return -EINVAL;
95 }
96 }
97