1 /* $NetBSD: amdgpu_sdma_v5_0.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $ */
2
3 /*
4 * Copyright 2019 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_sdma_v5_0.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $");
28
29 #include <linux/delay.h>
30 #include <linux/firmware.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33
34 #include "amdgpu.h"
35 #include "amdgpu_ucode.h"
36 #include "amdgpu_trace.h"
37
38 #include "gc/gc_10_1_0_offset.h"
39 #include "gc/gc_10_1_0_sh_mask.h"
40 #include "hdp/hdp_5_0_0_offset.h"
41 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
42 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
43
44 #include "soc15_common.h"
45 #include "soc15.h"
46 #include "navi10_sdma_pkt_open.h"
47 #include "nbio_v2_3.h"
48 #include "sdma_v5_0.h"
49
50 #include <linux/nbsd-namespace.h>
51
52 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
54
55 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
56 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
57
58 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
59 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
60
61 #define SDMA1_REG_OFFSET 0x600
62 #define SDMA0_HYP_DEC_REG_START 0x5880
63 #define SDMA0_HYP_DEC_REG_END 0x5893
64 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
65
66 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
67 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
68 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
69 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
70
71 static const struct soc15_reg_golden golden_settings_sdma_5[] = {
72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
76 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
77 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
78 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
80 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
81 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
82 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
83 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
84 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
88 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
89 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
90 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
91 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
92 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
93 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
94 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
96 };
97
98 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
101 };
102
103 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
106 };
107
108 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
111 };
112
sdma_v5_0_get_reg_offset(struct amdgpu_device * adev,u32 instance,u32 internal_offset)113 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
114 {
115 u32 base;
116
117 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
118 internal_offset <= SDMA0_HYP_DEC_REG_END) {
119 base = adev->reg_offset[GC_HWIP][0][1];
120 if (instance == 1)
121 internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
122 } else {
123 base = adev->reg_offset[GC_HWIP][0][0];
124 if (instance == 1)
125 internal_offset += SDMA1_REG_OFFSET;
126 }
127
128 return base + internal_offset;
129 }
130
sdma_v5_0_init_golden_registers(struct amdgpu_device * adev)131 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
132 {
133 switch (adev->asic_type) {
134 case CHIP_NAVI10:
135 soc15_program_register_sequence(adev,
136 golden_settings_sdma_5,
137 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
138 soc15_program_register_sequence(adev,
139 golden_settings_sdma_nv10,
140 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
141 break;
142 case CHIP_NAVI14:
143 soc15_program_register_sequence(adev,
144 golden_settings_sdma_5,
145 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
146 soc15_program_register_sequence(adev,
147 golden_settings_sdma_nv14,
148 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
149 break;
150 case CHIP_NAVI12:
151 soc15_program_register_sequence(adev,
152 golden_settings_sdma_5,
153 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
154 soc15_program_register_sequence(adev,
155 golden_settings_sdma_nv12,
156 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
157 break;
158 default:
159 break;
160 }
161 }
162
163 /**
164 * sdma_v5_0_init_microcode - load ucode images from disk
165 *
166 * @adev: amdgpu_device pointer
167 *
168 * Use the firmware interface to load the ucode images into
169 * the driver (not loaded into hw).
170 * Returns 0 on success, error on failure.
171 */
172
173 // emulation only, won't work on real chip
174 // navi10 real chip need to use PSP to load firmware
sdma_v5_0_init_microcode(struct amdgpu_device * adev)175 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
176 {
177 const char *chip_name;
178 char fw_name[30];
179 int err = 0, i;
180 struct amdgpu_firmware_info *info = NULL;
181 const struct common_firmware_header *header = NULL;
182 const struct sdma_firmware_header_v1_0 *hdr;
183
184 DRM_DEBUG("\n");
185
186 switch (adev->asic_type) {
187 case CHIP_NAVI10:
188 chip_name = "navi10";
189 break;
190 case CHIP_NAVI14:
191 chip_name = "navi14";
192 break;
193 case CHIP_NAVI12:
194 chip_name = "navi12";
195 break;
196 default:
197 BUG();
198 }
199
200 for (i = 0; i < adev->sdma.num_instances; i++) {
201 if (i == 0)
202 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
203 else
204 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
205 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
206 if (err)
207 goto out;
208 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
209 if (err)
210 goto out;
211 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
212 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
213 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
214 if (adev->sdma.instance[i].feature_version >= 20)
215 adev->sdma.instance[i].burst_nop = true;
216 DRM_DEBUG("psp_load == '%s'\n",
217 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
218
219 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
220 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
221 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
222 info->fw = adev->sdma.instance[i].fw;
223 header = (const struct common_firmware_header *)info->fw->data;
224 adev->firmware.fw_size +=
225 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
226 }
227 }
228 out:
229 if (err) {
230 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name);
231 for (i = 0; i < adev->sdma.num_instances; i++) {
232 release_firmware(adev->sdma.instance[i].fw);
233 adev->sdma.instance[i].fw = NULL;
234 }
235 }
236 return err;
237 }
238
sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring * ring)239 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
240 {
241 unsigned ret;
242
243 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
244 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
245 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
246 amdgpu_ring_write(ring, 1);
247 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
248 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
249
250 return ret;
251 }
252
sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring * ring,unsigned offset)253 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
254 unsigned offset)
255 {
256 unsigned cur;
257
258 BUG_ON(offset > ring->buf_mask);
259 BUG_ON(ring->ring[offset] != 0x55aa55aa);
260
261 cur = (ring->wptr - 1) & ring->buf_mask;
262 if (cur > offset)
263 ring->ring[offset] = cur - offset;
264 else
265 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
266 }
267
268 /**
269 * sdma_v5_0_ring_get_rptr - get the current read pointer
270 *
271 * @ring: amdgpu ring pointer
272 *
273 * Get the current rptr from the hardware (NAVI10+).
274 */
sdma_v5_0_ring_get_rptr(struct amdgpu_ring * ring)275 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
276 {
277 volatile u64 *rptr;
278
279 /* XXX check if swapping is necessary on BE */
280 rptr = ((volatile u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
281
282 DRM_DEBUG("rptr before shift == 0x%016"PRIx64"\n", *rptr);
283 return ((*rptr) >> 2);
284 }
285
286 /**
287 * sdma_v5_0_ring_get_wptr - get the current write pointer
288 *
289 * @ring: amdgpu ring pointer
290 *
291 * Get the current wptr from the hardware (NAVI10+).
292 */
sdma_v5_0_ring_get_wptr(struct amdgpu_ring * ring)293 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
294 {
295 struct amdgpu_device *adev = ring->adev;
296 volatile u64 *wptr = NULL;
297 uint64_t local_wptr = 0;
298
299 if (ring->use_doorbell) {
300 /* XXX check if swapping is necessary on BE */
301 wptr = ((volatile u64 *)&adev->wb.wb[ring->wptr_offs]);
302 DRM_DEBUG("wptr/doorbell before shift == 0x%016"PRIx64"\n", *wptr);
303 *wptr = (*wptr) >> 2;
304 DRM_DEBUG("wptr/doorbell after shift == 0x%016"PRIx64"\n", *wptr);
305 } else {
306 u32 lowbit, highbit;
307
308 wptr = &local_wptr;
309 lowbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;
310 highbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
311
312 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
313 ring->me, highbit, lowbit);
314 *wptr = highbit;
315 *wptr = (*wptr) << 32;
316 *wptr |= lowbit;
317 }
318
319 return *wptr;
320 }
321
322 /**
323 * sdma_v5_0_ring_set_wptr - commit the write pointer
324 *
325 * @ring: amdgpu ring pointer
326 *
327 * Write the wptr back to the hardware (NAVI10+).
328 */
sdma_v5_0_ring_set_wptr(struct amdgpu_ring * ring)329 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
330 {
331 struct amdgpu_device *adev = ring->adev;
332
333 DRM_DEBUG("Setting write pointer\n");
334 if (ring->use_doorbell) {
335 DRM_DEBUG("Using doorbell -- "
336 "wptr_offs == 0x%08x "
337 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
338 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
339 ring->wptr_offs,
340 lower_32_bits(ring->wptr << 2),
341 upper_32_bits(ring->wptr << 2));
342 /* XXX check if swapping is necessary on BE */
343 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
344 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
345 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016"PRIx64")\n",
346 ring->doorbell_index, ring->wptr << 2);
347 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
348 } else {
349 DRM_DEBUG("Not using doorbell -- "
350 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
351 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
352 ring->me,
353 lower_32_bits(ring->wptr << 2),
354 ring->me,
355 upper_32_bits(ring->wptr << 2));
356 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
357 lower_32_bits(ring->wptr << 2));
358 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
359 upper_32_bits(ring->wptr << 2));
360 }
361 }
362
sdma_v5_0_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)363 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
364 {
365 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
366 int i;
367
368 for (i = 0; i < count; i++)
369 if (sdma && sdma->burst_nop && (i == 0))
370 amdgpu_ring_write(ring, ring->funcs->nop |
371 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
372 else
373 amdgpu_ring_write(ring, ring->funcs->nop);
374 }
375
376 /**
377 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
378 *
379 * @ring: amdgpu ring pointer
380 * @ib: IB object to schedule
381 *
382 * Schedule an IB in the DMA ring (NAVI10).
383 */
sdma_v5_0_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)384 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
385 struct amdgpu_job *job,
386 struct amdgpu_ib *ib,
387 uint32_t flags)
388 {
389 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
390 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
391
392 /* An IB packet must end on a 8 DW boundary--the next dword
393 * must be on a 8-dword boundary. Our IB packet below is 6
394 * dwords long, thus add x number of NOPs, such that, in
395 * modular arithmetic,
396 * wptr + 6 + x = 8k, k >= 0, which in C is,
397 * (wptr + 6 + x) % 8 = 0.
398 * The expression below, is a solution of x.
399 */
400 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
401
402 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
403 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
404 /* base must be 32 byte aligned */
405 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
406 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
407 amdgpu_ring_write(ring, ib->length_dw);
408 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
409 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
410 }
411
412 /**
413 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
414 *
415 * @ring: amdgpu ring pointer
416 *
417 * Emit an hdp flush packet on the requested DMA ring.
418 */
sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)419 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
420 {
421 struct amdgpu_device *adev = ring->adev;
422 u32 ref_and_mask = 0;
423 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
424
425 if (ring->me == 0)
426 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
427 else
428 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
429
430 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
431 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
432 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
433 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
434 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
435 amdgpu_ring_write(ring, ref_and_mask); /* reference */
436 amdgpu_ring_write(ring, ref_and_mask); /* mask */
437 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
438 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
439 }
440
441 /**
442 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
443 *
444 * @ring: amdgpu ring pointer
445 * @fence: amdgpu fence object
446 *
447 * Add a DMA fence packet to the ring to write
448 * the fence seq number and DMA trap packet to generate
449 * an interrupt if needed (NAVI10).
450 */
sdma_v5_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)451 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
452 unsigned flags)
453 {
454 struct amdgpu_device *adev = ring->adev;
455 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
456 /* write the fence */
457 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
458 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
459 /* zero in first two bits */
460 BUG_ON(addr & 0x3);
461 amdgpu_ring_write(ring, lower_32_bits(addr));
462 amdgpu_ring_write(ring, upper_32_bits(addr));
463 amdgpu_ring_write(ring, lower_32_bits(seq));
464
465 /* optionally write high bits as well */
466 if (write64bit) {
467 addr += 4;
468 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
469 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
470 /* zero in first two bits */
471 BUG_ON(addr & 0x3);
472 amdgpu_ring_write(ring, lower_32_bits(addr));
473 amdgpu_ring_write(ring, upper_32_bits(addr));
474 amdgpu_ring_write(ring, upper_32_bits(seq));
475 }
476
477 /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
478 if ((flags & AMDGPU_FENCE_FLAG_INT) && adev->pdev->device != 0x50) {
479 /* generate an interrupt */
480 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
481 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
482 }
483 }
484
485
486 /**
487 * sdma_v5_0_gfx_stop - stop the gfx async dma engines
488 *
489 * @adev: amdgpu_device pointer
490 *
491 * Stop the gfx async dma ring buffers (NAVI10).
492 */
sdma_v5_0_gfx_stop(struct amdgpu_device * adev)493 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
494 {
495 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
496 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
497 u32 rb_cntl, ib_cntl;
498 int i;
499
500 if ((adev->mman.buffer_funcs_ring == sdma0) ||
501 (adev->mman.buffer_funcs_ring == sdma1))
502 amdgpu_ttm_set_buffer_funcs_status(adev, false);
503
504 for (i = 0; i < adev->sdma.num_instances; i++) {
505 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
506 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
507 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
508 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
509 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
510 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
511 }
512
513 sdma0->sched.ready = false;
514 sdma1->sched.ready = false;
515 }
516
517 /**
518 * sdma_v5_0_rlc_stop - stop the compute async dma engines
519 *
520 * @adev: amdgpu_device pointer
521 *
522 * Stop the compute async dma queues (NAVI10).
523 */
sdma_v5_0_rlc_stop(struct amdgpu_device * adev)524 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
525 {
526 /* XXX todo */
527 }
528
529 /**
530 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
531 *
532 * @adev: amdgpu_device pointer
533 * @enable: enable/disable the DMA MEs context switch.
534 *
535 * Halt or unhalt the async dma engines context switch (NAVI10).
536 */
sdma_v5_0_ctx_switch_enable(struct amdgpu_device * adev,bool enable)537 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
538 {
539 u32 f32_cntl, phase_quantum = 0;
540 int i;
541
542 if (amdgpu_sdma_phase_quantum) {
543 unsigned value = amdgpu_sdma_phase_quantum;
544 unsigned unit = 0;
545
546 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
547 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
548 value = (value + 1) >> 1;
549 unit++;
550 }
551 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
552 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
553 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
554 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
555 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
556 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
557 WARN_ONCE(1,
558 "clamping sdma_phase_quantum to %uK clock cycles\n",
559 value << unit);
560 }
561 phase_quantum =
562 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
563 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
564 }
565
566 for (i = 0; i < adev->sdma.num_instances; i++) {
567 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
568 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
569 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
570 if (enable && amdgpu_sdma_phase_quantum) {
571 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
572 phase_quantum);
573 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
574 phase_quantum);
575 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
576 phase_quantum);
577 }
578 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
579 }
580
581 }
582
583 /**
584 * sdma_v5_0_enable - stop the async dma engines
585 *
586 * @adev: amdgpu_device pointer
587 * @enable: enable/disable the DMA MEs.
588 *
589 * Halt or unhalt the async dma engines (NAVI10).
590 */
sdma_v5_0_enable(struct amdgpu_device * adev,bool enable)591 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
592 {
593 u32 f32_cntl;
594 int i;
595
596 if (enable == false) {
597 sdma_v5_0_gfx_stop(adev);
598 sdma_v5_0_rlc_stop(adev);
599 }
600
601 for (i = 0; i < adev->sdma.num_instances; i++) {
602 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
603 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
604 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
605 }
606 }
607
608 /**
609 * sdma_v5_0_gfx_resume - setup and start the async dma engines
610 *
611 * @adev: amdgpu_device pointer
612 *
613 * Set up the gfx DMA ring buffers and enable them (NAVI10).
614 * Returns 0 for success, error for failure.
615 */
sdma_v5_0_gfx_resume(struct amdgpu_device * adev)616 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
617 {
618 struct amdgpu_ring *ring;
619 u32 rb_cntl, ib_cntl;
620 u32 rb_bufsz;
621 u32 wb_offset;
622 u32 doorbell;
623 u32 doorbell_offset;
624 u32 temp;
625 u32 wptr_poll_cntl;
626 u64 wptr_gpu_addr;
627 int i, r;
628
629 for (i = 0; i < adev->sdma.num_instances; i++) {
630 ring = &adev->sdma.instance[i].ring;
631 wb_offset = (ring->rptr_offs * 4);
632
633 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
634
635 /* Set ring buffer size in dwords */
636 rb_bufsz = order_base_2(ring->ring_size / 4);
637 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
638 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
639 #ifdef __BIG_ENDIAN
640 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
641 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
642 RPTR_WRITEBACK_SWAP_ENABLE, 1);
643 #endif
644 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
645
646 /* Initialize the ring buffer's read and write pointers */
647 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
648 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
649 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
650 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
651
652 /* setup the wptr shadow polling */
653 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
654 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
655 lower_32_bits(wptr_gpu_addr));
656 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
657 upper_32_bits(wptr_gpu_addr));
658 wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i,
659 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
660 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
661 SDMA0_GFX_RB_WPTR_POLL_CNTL,
662 F32_POLL_ENABLE, 1);
663 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
664 wptr_poll_cntl);
665
666 /* set the wb address whether it's enabled or not */
667 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
668 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
669 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
670 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
671
672 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
673
674 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
675 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
676
677 ring->wptr = 0;
678
679 /* before programing wptr to a less value, need set minor_ptr_update first */
680 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
681
682 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
683 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
684 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
685 }
686
687 doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
688 doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
689
690 if (ring->use_doorbell) {
691 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
692 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
693 OFFSET, ring->doorbell_index);
694 } else {
695 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
696 }
697 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
698 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
699
700 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
701 ring->doorbell_index, 20);
702
703 if (amdgpu_sriov_vf(adev))
704 sdma_v5_0_ring_set_wptr(ring);
705
706 /* set minor_ptr_update to 0 after wptr programed */
707 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
708
709 /* set utc l1 enable flag always to 1 */
710 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
711 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
712
713 /* enable MCBP */
714 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
715 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
716
717 /* Set up RESP_MODE to non-copy addresses */
718 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
719 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
720 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
721 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
722
723 /* program default cache read and write policy */
724 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
725 /* clean read policy and write policy bits */
726 temp &= 0xFF0FFF;
727 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
728 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
729
730 if (!amdgpu_sriov_vf(adev)) {
731 /* unhalt engine */
732 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
733 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
734 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
735 }
736
737 /* enable DMA RB */
738 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
739 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
740
741 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
742 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
743 #ifdef __BIG_ENDIAN
744 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
745 #endif
746 /* enable DMA IBs */
747 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
748
749 ring->sched.ready = true;
750
751 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
752 sdma_v5_0_ctx_switch_enable(adev, true);
753 sdma_v5_0_enable(adev, true);
754 }
755
756 r = amdgpu_ring_test_ring(ring);
757 if (r) {
758 ring->sched.ready = false;
759 return r;
760 }
761
762 if (adev->mman.buffer_funcs_ring == ring)
763 amdgpu_ttm_set_buffer_funcs_status(adev, true);
764 }
765
766 return 0;
767 }
768
769 /**
770 * sdma_v5_0_rlc_resume - setup and start the async dma engines
771 *
772 * @adev: amdgpu_device pointer
773 *
774 * Set up the compute DMA queues and enable them (NAVI10).
775 * Returns 0 for success, error for failure.
776 */
sdma_v5_0_rlc_resume(struct amdgpu_device * adev)777 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
778 {
779 return 0;
780 }
781
782 /**
783 * sdma_v5_0_load_microcode - load the sDMA ME ucode
784 *
785 * @adev: amdgpu_device pointer
786 *
787 * Loads the sDMA0/1 ucode.
788 * Returns 0 for success, -EINVAL if the ucode is not available.
789 */
sdma_v5_0_load_microcode(struct amdgpu_device * adev)790 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
791 {
792 const struct sdma_firmware_header_v1_0 *hdr;
793 const __le32 *fw_data;
794 u32 fw_size;
795 int i, j;
796
797 /* halt the MEs */
798 sdma_v5_0_enable(adev, false);
799
800 for (i = 0; i < adev->sdma.num_instances; i++) {
801 if (!adev->sdma.instance[i].fw)
802 return -EINVAL;
803
804 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
805 amdgpu_ucode_print_sdma_hdr(&hdr->header);
806 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
807
808 fw_data = (const __le32 *)
809 (adev->sdma.instance[i].fw->data +
810 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
811
812 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
813
814 for (j = 0; j < fw_size; j++) {
815 if (amdgpu_emu_mode == 1 && j % 500 == 0)
816 msleep(1);
817 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
818 }
819
820 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
821 }
822
823 return 0;
824 }
825
826 /**
827 * sdma_v5_0_start - setup and start the async dma engines
828 *
829 * @adev: amdgpu_device pointer
830 *
831 * Set up the DMA engines and enable them (NAVI10).
832 * Returns 0 for success, error for failure.
833 */
sdma_v5_0_start(struct amdgpu_device * adev)834 static int sdma_v5_0_start(struct amdgpu_device *adev)
835 {
836 int r = 0;
837
838 if (amdgpu_sriov_vf(adev)) {
839 sdma_v5_0_ctx_switch_enable(adev, false);
840 sdma_v5_0_enable(adev, false);
841
842 /* set RB registers */
843 r = sdma_v5_0_gfx_resume(adev);
844 return r;
845 }
846
847 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
848 r = sdma_v5_0_load_microcode(adev);
849 if (r)
850 return r;
851
852 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
853 if (amdgpu_emu_mode == 1 && adev->pdev->device == 0x4d)
854 msleep(1000);
855 }
856
857 /* unhalt the MEs */
858 sdma_v5_0_enable(adev, true);
859 /* enable sdma ring preemption */
860 sdma_v5_0_ctx_switch_enable(adev, true);
861
862 /* start the gfx rings and rlc compute queues */
863 r = sdma_v5_0_gfx_resume(adev);
864 if (r)
865 return r;
866 r = sdma_v5_0_rlc_resume(adev);
867
868 return r;
869 }
870
871 /**
872 * sdma_v5_0_ring_test_ring - simple async dma engine test
873 *
874 * @ring: amdgpu_ring structure holding ring information
875 *
876 * Test the DMA engine by writing using it to write an
877 * value to memory. (NAVI10).
878 * Returns 0 for success, error for failure.
879 */
sdma_v5_0_ring_test_ring(struct amdgpu_ring * ring)880 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
881 {
882 struct amdgpu_device *adev = ring->adev;
883 unsigned i;
884 unsigned index;
885 int r;
886 u32 tmp;
887 u64 gpu_addr;
888
889 r = amdgpu_device_wb_get(adev, &index);
890 if (r) {
891 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
892 return r;
893 }
894
895 gpu_addr = adev->wb.gpu_addr + (index * 4);
896 tmp = 0xCAFEDEAD;
897 adev->wb.wb[index] = cpu_to_le32(tmp);
898
899 r = amdgpu_ring_alloc(ring, 5);
900 if (r) {
901 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
902 amdgpu_device_wb_free(adev, index);
903 return r;
904 }
905
906 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
907 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
908 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
909 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
910 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
911 amdgpu_ring_write(ring, 0xDEADBEEF);
912 amdgpu_ring_commit(ring);
913
914 for (i = 0; i < adev->usec_timeout; i++) {
915 tmp = le32_to_cpu(adev->wb.wb[index]);
916 if (tmp == 0xDEADBEEF)
917 break;
918 if (amdgpu_emu_mode == 1)
919 msleep(1);
920 else
921 udelay(1);
922 }
923
924 if (i >= adev->usec_timeout)
925 r = -ETIMEDOUT;
926
927 amdgpu_device_wb_free(adev, index);
928
929 return r;
930 }
931
932 /**
933 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
934 *
935 * @ring: amdgpu_ring structure holding ring information
936 *
937 * Test a simple IB in the DMA ring (NAVI10).
938 * Returns 0 on success, error on failure.
939 */
sdma_v5_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)940 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
941 {
942 struct amdgpu_device *adev = ring->adev;
943 struct amdgpu_ib ib;
944 struct dma_fence *f = NULL;
945 unsigned index;
946 long r;
947 u32 tmp = 0;
948 u64 gpu_addr;
949
950 r = amdgpu_device_wb_get(adev, &index);
951 if (r) {
952 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
953 return r;
954 }
955
956 gpu_addr = adev->wb.gpu_addr + (index * 4);
957 tmp = 0xCAFEDEAD;
958 adev->wb.wb[index] = cpu_to_le32(tmp);
959 memset(&ib, 0, sizeof(ib));
960 r = amdgpu_ib_get(adev, NULL, 256, &ib);
961 if (r) {
962 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
963 goto err0;
964 }
965
966 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
967 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
968 ib.ptr[1] = lower_32_bits(gpu_addr);
969 ib.ptr[2] = upper_32_bits(gpu_addr);
970 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
971 ib.ptr[4] = 0xDEADBEEF;
972 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
973 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
974 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
975 ib.length_dw = 8;
976
977 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
978 if (r)
979 goto err1;
980
981 r = dma_fence_wait_timeout(f, false, timeout);
982 if (r == 0) {
983 DRM_ERROR("amdgpu: IB test timed out\n");
984 r = -ETIMEDOUT;
985 goto err1;
986 } else if (r < 0) {
987 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
988 goto err1;
989 }
990 tmp = le32_to_cpu(adev->wb.wb[index]);
991 if (tmp == 0xDEADBEEF)
992 r = 0;
993 else
994 r = -EINVAL;
995
996 err1:
997 amdgpu_ib_free(adev, &ib, NULL);
998 dma_fence_put(f);
999 err0:
1000 amdgpu_device_wb_free(adev, index);
1001 return r;
1002 }
1003
1004
1005 /**
1006 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1007 *
1008 * @ib: indirect buffer to fill with commands
1009 * @pe: addr of the page entry
1010 * @src: src addr to copy from
1011 * @count: number of page entries to update
1012 *
1013 * Update PTEs by copying them from the GART using sDMA (NAVI10).
1014 */
sdma_v5_0_vm_copy_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t src,unsigned count)1015 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
1016 uint64_t pe, uint64_t src,
1017 unsigned count)
1018 {
1019 unsigned bytes = count * 8;
1020
1021 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1022 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1023 ib->ptr[ib->length_dw++] = bytes - 1;
1024 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1025 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1026 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1027 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1028 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1029
1030 }
1031
1032 /**
1033 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1034 *
1035 * @ib: indirect buffer to fill with commands
1036 * @pe: addr of the page entry
1037 * @addr: dst addr to write into pe
1038 * @count: number of page entries to update
1039 * @incr: increase next addr by incr bytes
1040 * @flags: access flags
1041 *
1042 * Update PTEs by writing them manually using sDMA (NAVI10).
1043 */
sdma_v5_0_vm_write_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t value,unsigned count,uint32_t incr)1044 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1045 uint64_t value, unsigned count,
1046 uint32_t incr)
1047 {
1048 unsigned ndw = count * 2;
1049
1050 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1051 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1052 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1053 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1054 ib->ptr[ib->length_dw++] = ndw - 1;
1055 for (; ndw > 0; ndw -= 2) {
1056 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1057 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1058 value += incr;
1059 }
1060 }
1061
1062 /**
1063 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1064 *
1065 * @ib: indirect buffer to fill with commands
1066 * @pe: addr of the page entry
1067 * @addr: dst addr to write into pe
1068 * @count: number of page entries to update
1069 * @incr: increase next addr by incr bytes
1070 * @flags: access flags
1071 *
1072 * Update the page tables using sDMA (NAVI10).
1073 */
sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib * ib,uint64_t pe,uint64_t addr,unsigned count,uint32_t incr,uint64_t flags)1074 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1075 uint64_t pe,
1076 uint64_t addr, unsigned count,
1077 uint32_t incr, uint64_t flags)
1078 {
1079 /* for physically contiguous pages (vram) */
1080 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1081 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1082 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1083 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1084 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1085 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1086 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1087 ib->ptr[ib->length_dw++] = incr; /* increment size */
1088 ib->ptr[ib->length_dw++] = 0;
1089 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1090 }
1091
1092 /**
1093 * sdma_v5_0_ring_pad_ib - pad the IB
1094 * @ib: indirect buffer to fill with padding
1095 *
1096 * Pad the IB with NOPs to a boundary multiple of 8.
1097 */
sdma_v5_0_ring_pad_ib(struct amdgpu_ring * ring,struct amdgpu_ib * ib)1098 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1099 {
1100 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1101 u32 pad_count;
1102 int i;
1103
1104 pad_count = (-ib->length_dw) & 0x7;
1105 for (i = 0; i < pad_count; i++)
1106 if (sdma && sdma->burst_nop && (i == 0))
1107 ib->ptr[ib->length_dw++] =
1108 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1109 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1110 else
1111 ib->ptr[ib->length_dw++] =
1112 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1113 }
1114
1115
1116 /**
1117 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1118 *
1119 * @ring: amdgpu_ring pointer
1120 *
1121 * Make sure all previous operations are completed (CIK).
1122 */
sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)1123 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1124 {
1125 uint32_t seq = ring->fence_drv.sync_seq;
1126 uint64_t addr = ring->fence_drv.gpu_addr;
1127
1128 /* wait for idle */
1129 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1130 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1131 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1132 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1133 amdgpu_ring_write(ring, addr & 0xfffffffc);
1134 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1135 amdgpu_ring_write(ring, seq); /* reference */
1136 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1137 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1138 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1139 }
1140
1141
1142 /**
1143 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1144 *
1145 * @ring: amdgpu_ring pointer
1146 * @vm: amdgpu_vm pointer
1147 *
1148 * Update the page table base and flush the VM TLB
1149 * using sDMA (NAVI10).
1150 */
sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1151 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1152 unsigned vmid, uint64_t pd_addr)
1153 {
1154 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1155 }
1156
sdma_v5_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1157 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1158 uint32_t reg, uint32_t val)
1159 {
1160 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1161 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1162 amdgpu_ring_write(ring, reg);
1163 amdgpu_ring_write(ring, val);
1164 }
1165
sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1166 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1167 uint32_t val, uint32_t mask)
1168 {
1169 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1170 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1171 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1172 amdgpu_ring_write(ring, reg << 2);
1173 amdgpu_ring_write(ring, 0);
1174 amdgpu_ring_write(ring, val); /* reference */
1175 amdgpu_ring_write(ring, mask); /* mask */
1176 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1177 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1178 }
1179
sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)1180 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1181 uint32_t reg0, uint32_t reg1,
1182 uint32_t ref, uint32_t mask)
1183 {
1184 amdgpu_ring_emit_wreg(ring, reg0, ref);
1185 /* wait for a cycle to reset vm_inv_eng*_ack */
1186 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1187 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1188 }
1189
sdma_v5_0_early_init(void * handle)1190 static int sdma_v5_0_early_init(void *handle)
1191 {
1192 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1193
1194 adev->sdma.num_instances = 2;
1195
1196 sdma_v5_0_set_ring_funcs(adev);
1197 sdma_v5_0_set_buffer_funcs(adev);
1198 sdma_v5_0_set_vm_pte_funcs(adev);
1199 sdma_v5_0_set_irq_funcs(adev);
1200
1201 return 0;
1202 }
1203
1204
sdma_v5_0_sw_init(void * handle)1205 static int sdma_v5_0_sw_init(void *handle)
1206 {
1207 struct amdgpu_ring *ring;
1208 int r, i;
1209 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1210
1211 /* SDMA trap event */
1212 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1213 SDMA0_5_0__SRCID__SDMA_TRAP,
1214 &adev->sdma.trap_irq);
1215 if (r)
1216 return r;
1217
1218 /* SDMA trap event */
1219 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1220 SDMA1_5_0__SRCID__SDMA_TRAP,
1221 &adev->sdma.trap_irq);
1222 if (r)
1223 return r;
1224
1225 r = sdma_v5_0_init_microcode(adev);
1226 if (r) {
1227 DRM_ERROR("Failed to load sdma firmware!\n");
1228 return r;
1229 }
1230
1231 for (i = 0; i < adev->sdma.num_instances; i++) {
1232 ring = &adev->sdma.instance[i].ring;
1233 ring->ring_obj = NULL;
1234 ring->use_doorbell = true;
1235
1236 DRM_INFO("use_doorbell being set to: [%s]\n",
1237 ring->use_doorbell?"true":"false");
1238
1239 ring->doorbell_index = (i == 0) ?
1240 (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1241 : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1242
1243 snprintf(ring->name, sizeof(ring->name), "sdma%d", i);
1244 r = amdgpu_ring_init(adev, ring, 1024,
1245 &adev->sdma.trap_irq,
1246 (i == 0) ?
1247 AMDGPU_SDMA_IRQ_INSTANCE0 :
1248 AMDGPU_SDMA_IRQ_INSTANCE1);
1249 if (r)
1250 return r;
1251 }
1252
1253 return r;
1254 }
1255
sdma_v5_0_sw_fini(void * handle)1256 static int sdma_v5_0_sw_fini(void *handle)
1257 {
1258 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1259 int i;
1260
1261 for (i = 0; i < adev->sdma.num_instances; i++)
1262 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1263
1264 return 0;
1265 }
1266
sdma_v5_0_hw_init(void * handle)1267 static int sdma_v5_0_hw_init(void *handle)
1268 {
1269 int r;
1270 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1271
1272 sdma_v5_0_init_golden_registers(adev);
1273
1274 r = sdma_v5_0_start(adev);
1275
1276 return r;
1277 }
1278
sdma_v5_0_hw_fini(void * handle)1279 static int sdma_v5_0_hw_fini(void *handle)
1280 {
1281 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1282
1283 if (amdgpu_sriov_vf(adev))
1284 return 0;
1285
1286 sdma_v5_0_ctx_switch_enable(adev, false);
1287 sdma_v5_0_enable(adev, false);
1288
1289 return 0;
1290 }
1291
sdma_v5_0_suspend(void * handle)1292 static int sdma_v5_0_suspend(void *handle)
1293 {
1294 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1295
1296 return sdma_v5_0_hw_fini(adev);
1297 }
1298
sdma_v5_0_resume(void * handle)1299 static int sdma_v5_0_resume(void *handle)
1300 {
1301 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1302
1303 return sdma_v5_0_hw_init(adev);
1304 }
1305
sdma_v5_0_is_idle(void * handle)1306 static bool sdma_v5_0_is_idle(void *handle)
1307 {
1308 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1309 u32 i;
1310
1311 for (i = 0; i < adev->sdma.num_instances; i++) {
1312 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1313
1314 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1315 return false;
1316 }
1317
1318 return true;
1319 }
1320
sdma_v5_0_wait_for_idle(void * handle)1321 static int sdma_v5_0_wait_for_idle(void *handle)
1322 {
1323 unsigned i;
1324 u32 sdma0, sdma1;
1325 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1326
1327 for (i = 0; i < adev->usec_timeout; i++) {
1328 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1329 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1330
1331 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1332 return 0;
1333 udelay(1);
1334 }
1335 return -ETIMEDOUT;
1336 }
1337
sdma_v5_0_soft_reset(void * handle)1338 static int sdma_v5_0_soft_reset(void *handle)
1339 {
1340 /* todo */
1341
1342 return 0;
1343 }
1344
sdma_v5_0_ring_preempt_ib(struct amdgpu_ring * ring)1345 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1346 {
1347 int i, r = 0;
1348 struct amdgpu_device *adev = ring->adev;
1349 u32 index = 0;
1350 u64 sdma_gfx_preempt;
1351
1352 amdgpu_sdma_get_index_from_ring(ring, &index);
1353 if (index == 0)
1354 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1355 else
1356 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1357
1358 /* assert preemption condition */
1359 amdgpu_ring_set_preempt_cond_exec(ring, false);
1360
1361 /* emit the trailing fence */
1362 ring->trail_seq += 1;
1363 amdgpu_ring_alloc(ring, 10);
1364 sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1365 ring->trail_seq, 0);
1366 amdgpu_ring_commit(ring);
1367
1368 /* assert IB preemption */
1369 WREG32(sdma_gfx_preempt, 1);
1370
1371 /* poll the trailing fence */
1372 for (i = 0; i < adev->usec_timeout; i++) {
1373 if (ring->trail_seq ==
1374 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1375 break;
1376 udelay(1);
1377 }
1378
1379 if (i >= adev->usec_timeout) {
1380 r = -EINVAL;
1381 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1382 }
1383
1384 /* deassert IB preemption */
1385 WREG32(sdma_gfx_preempt, 0);
1386
1387 /* deassert the preemption condition */
1388 amdgpu_ring_set_preempt_cond_exec(ring, true);
1389 return r;
1390 }
1391
sdma_v5_0_set_trap_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1392 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1393 struct amdgpu_irq_src *source,
1394 unsigned type,
1395 enum amdgpu_interrupt_state state)
1396 {
1397 u32 sdma_cntl;
1398
1399 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1400 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1401 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1402
1403 sdma_cntl = RREG32(reg_offset);
1404 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1405 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1406 WREG32(reg_offset, sdma_cntl);
1407
1408 return 0;
1409 }
1410
sdma_v5_0_process_trap_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1411 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1412 struct amdgpu_irq_src *source,
1413 struct amdgpu_iv_entry *entry)
1414 {
1415 DRM_DEBUG("IH: SDMA trap\n");
1416 switch (entry->client_id) {
1417 case SOC15_IH_CLIENTID_SDMA0:
1418 switch (entry->ring_id) {
1419 case 0:
1420 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1421 break;
1422 case 1:
1423 /* XXX compute */
1424 break;
1425 case 2:
1426 /* XXX compute */
1427 break;
1428 case 3:
1429 /* XXX page queue*/
1430 break;
1431 }
1432 break;
1433 case SOC15_IH_CLIENTID_SDMA1:
1434 switch (entry->ring_id) {
1435 case 0:
1436 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1437 break;
1438 case 1:
1439 /* XXX compute */
1440 break;
1441 case 2:
1442 /* XXX compute */
1443 break;
1444 case 3:
1445 /* XXX page queue*/
1446 break;
1447 }
1448 break;
1449 }
1450 return 0;
1451 }
1452
sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1453 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1454 struct amdgpu_irq_src *source,
1455 struct amdgpu_iv_entry *entry)
1456 {
1457 return 0;
1458 }
1459
sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)1460 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1461 bool enable)
1462 {
1463 uint32_t data, def;
1464 int i;
1465
1466 for (i = 0; i < adev->sdma.num_instances; i++) {
1467 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1468 /* Enable sdma clock gating */
1469 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1470 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1471 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1472 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1473 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1474 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1475 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1476 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1477 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1478 if (def != data)
1479 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1480 } else {
1481 /* Disable sdma clock gating */
1482 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1483 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1484 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1485 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1486 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1487 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1488 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1489 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1490 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1491 if (def != data)
1492 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1493 }
1494 }
1495 }
1496
sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)1497 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1498 bool enable)
1499 {
1500 uint32_t data, def;
1501 int i;
1502
1503 for (i = 0; i < adev->sdma.num_instances; i++) {
1504 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1505 /* Enable sdma mem light sleep */
1506 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1507 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1508 if (def != data)
1509 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1510
1511 } else {
1512 /* Disable sdma mem light sleep */
1513 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1514 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1515 if (def != data)
1516 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1517
1518 }
1519 }
1520 }
1521
sdma_v5_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)1522 static int sdma_v5_0_set_clockgating_state(void *handle,
1523 enum amd_clockgating_state state)
1524 {
1525 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1526
1527 if (amdgpu_sriov_vf(adev))
1528 return 0;
1529
1530 switch (adev->asic_type) {
1531 case CHIP_NAVI10:
1532 case CHIP_NAVI14:
1533 case CHIP_NAVI12:
1534 sdma_v5_0_update_medium_grain_clock_gating(adev,
1535 state == AMD_CG_STATE_GATE);
1536 sdma_v5_0_update_medium_grain_light_sleep(adev,
1537 state == AMD_CG_STATE_GATE);
1538 break;
1539 default:
1540 break;
1541 }
1542
1543 return 0;
1544 }
1545
sdma_v5_0_set_powergating_state(void * handle,enum amd_powergating_state state)1546 static int sdma_v5_0_set_powergating_state(void *handle,
1547 enum amd_powergating_state state)
1548 {
1549 return 0;
1550 }
1551
sdma_v5_0_get_clockgating_state(void * handle,u32 * flags)1552 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags)
1553 {
1554 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1555 int data;
1556
1557 if (amdgpu_sriov_vf(adev))
1558 *flags = 0;
1559
1560 /* AMD_CG_SUPPORT_SDMA_MGCG */
1561 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1562 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1563 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1564
1565 /* AMD_CG_SUPPORT_SDMA_LS */
1566 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1567 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1568 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1569 }
1570
1571 const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1572 .name = "sdma_v5_0",
1573 .early_init = sdma_v5_0_early_init,
1574 .late_init = NULL,
1575 .sw_init = sdma_v5_0_sw_init,
1576 .sw_fini = sdma_v5_0_sw_fini,
1577 .hw_init = sdma_v5_0_hw_init,
1578 .hw_fini = sdma_v5_0_hw_fini,
1579 .suspend = sdma_v5_0_suspend,
1580 .resume = sdma_v5_0_resume,
1581 .is_idle = sdma_v5_0_is_idle,
1582 .wait_for_idle = sdma_v5_0_wait_for_idle,
1583 .soft_reset = sdma_v5_0_soft_reset,
1584 .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1585 .set_powergating_state = sdma_v5_0_set_powergating_state,
1586 .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1587 };
1588
1589 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1590 .type = AMDGPU_RING_TYPE_SDMA,
1591 .align_mask = 0xf,
1592 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1593 .support_64bit_ptrs = true,
1594 .vmhub = AMDGPU_GFXHUB_0,
1595 .get_rptr = sdma_v5_0_ring_get_rptr,
1596 .get_wptr = sdma_v5_0_ring_get_wptr,
1597 .set_wptr = sdma_v5_0_ring_set_wptr,
1598 .emit_frame_size =
1599 5 + /* sdma_v5_0_ring_init_cond_exec */
1600 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1601 3 + /* hdp_invalidate */
1602 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1603 /* sdma_v5_0_ring_emit_vm_flush */
1604 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1605 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1606 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1607 .emit_ib_size = 7 + 6, /* sdma_v5_0_ring_emit_ib */
1608 .emit_ib = sdma_v5_0_ring_emit_ib,
1609 .emit_fence = sdma_v5_0_ring_emit_fence,
1610 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1611 .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1612 .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1613 .test_ring = sdma_v5_0_ring_test_ring,
1614 .test_ib = sdma_v5_0_ring_test_ib,
1615 .insert_nop = sdma_v5_0_ring_insert_nop,
1616 .pad_ib = sdma_v5_0_ring_pad_ib,
1617 .emit_wreg = sdma_v5_0_ring_emit_wreg,
1618 .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1619 .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
1620 .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1621 .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
1622 .preempt_ib = sdma_v5_0_ring_preempt_ib,
1623 };
1624
sdma_v5_0_set_ring_funcs(struct amdgpu_device * adev)1625 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1626 {
1627 int i;
1628
1629 for (i = 0; i < adev->sdma.num_instances; i++) {
1630 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1631 adev->sdma.instance[i].ring.me = i;
1632 }
1633 }
1634
1635 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1636 .set = sdma_v5_0_set_trap_irq_state,
1637 .process = sdma_v5_0_process_trap_irq,
1638 };
1639
1640 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1641 .process = sdma_v5_0_process_illegal_inst_irq,
1642 };
1643
sdma_v5_0_set_irq_funcs(struct amdgpu_device * adev)1644 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1645 {
1646 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1647 adev->sdma.num_instances;
1648 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1649 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1650 }
1651
1652 /**
1653 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1654 *
1655 * @ring: amdgpu_ring structure holding ring information
1656 * @src_offset: src GPU address
1657 * @dst_offset: dst GPU address
1658 * @byte_count: number of bytes to xfer
1659 *
1660 * Copy GPU buffers using the DMA engine (NAVI10).
1661 * Used by the amdgpu ttm implementation to move pages if
1662 * registered as the asic copy callback.
1663 */
sdma_v5_0_emit_copy_buffer(struct amdgpu_ib * ib,uint64_t src_offset,uint64_t dst_offset,uint32_t byte_count)1664 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1665 uint64_t src_offset,
1666 uint64_t dst_offset,
1667 uint32_t byte_count)
1668 {
1669 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1670 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1671 ib->ptr[ib->length_dw++] = byte_count - 1;
1672 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1673 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1674 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1675 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1676 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1677 }
1678
1679 /**
1680 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1681 *
1682 * @ring: amdgpu_ring structure holding ring information
1683 * @src_data: value to write to buffer
1684 * @dst_offset: dst GPU address
1685 * @byte_count: number of bytes to xfer
1686 *
1687 * Fill GPU buffers using the DMA engine (NAVI10).
1688 */
sdma_v5_0_emit_fill_buffer(struct amdgpu_ib * ib,uint32_t src_data,uint64_t dst_offset,uint32_t byte_count)1689 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1690 uint32_t src_data,
1691 uint64_t dst_offset,
1692 uint32_t byte_count)
1693 {
1694 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1695 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1696 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1697 ib->ptr[ib->length_dw++] = src_data;
1698 ib->ptr[ib->length_dw++] = byte_count - 1;
1699 }
1700
1701 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1702 .copy_max_bytes = 0x400000,
1703 .copy_num_dw = 7,
1704 .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1705
1706 .fill_max_bytes = 0x400000,
1707 .fill_num_dw = 5,
1708 .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1709 };
1710
sdma_v5_0_set_buffer_funcs(struct amdgpu_device * adev)1711 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1712 {
1713 if (adev->mman.buffer_funcs == NULL) {
1714 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1715 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1716 }
1717 }
1718
1719 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1720 .copy_pte_num_dw = 7,
1721 .copy_pte = sdma_v5_0_vm_copy_pte,
1722 .write_pte = sdma_v5_0_vm_write_pte,
1723 .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1724 };
1725
sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device * adev)1726 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1727 {
1728 unsigned i;
1729
1730 if (adev->vm_manager.vm_pte_funcs == NULL) {
1731 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1732 for (i = 0; i < adev->sdma.num_instances; i++) {
1733 adev->vm_manager.vm_pte_scheds[i] =
1734 &adev->sdma.instance[i].ring.sched;
1735 }
1736 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1737 }
1738 }
1739
1740 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1741 .type = AMD_IP_BLOCK_TYPE_SDMA,
1742 .major = 5,
1743 .minor = 0,
1744 .rev = 0,
1745 .funcs = &sdma_v5_0_ip_funcs,
1746 };
1747