1 /* $NetBSD: amdgpu_psp_v11_0.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $ */
2
3 /*
4 * Copyright 2018 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include <sys/cdefs.h>
26 __KERNEL_RCSID(0, "$NetBSD: amdgpu_psp_v11_0.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $");
27
28 #include <asm/io.h>
29 #include <linux/firmware.h>
30 #include <linux/module.h>
31 #include <linux/vmalloc.h>
32
33 #include "amdgpu.h"
34 #include "amdgpu_psp.h"
35 #include "amdgpu_ucode.h"
36 #include "soc15_common.h"
37 #include "psp_v11_0.h"
38
39 #include "mp/mp_11_0_offset.h"
40 #include "mp/mp_11_0_sh_mask.h"
41 #include "gc/gc_9_0_offset.h"
42 #include "sdma0/sdma0_4_0_offset.h"
43 #include "nbio/nbio_7_4_offset.h"
44
45 #include "oss/osssys_4_0_offset.h"
46 #include "oss/osssys_4_0_sh_mask.h"
47
48 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
49 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
50 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
51 MODULE_FIRMWARE("amdgpu/navi10_sos.bin");
52 MODULE_FIRMWARE("amdgpu/navi10_asd.bin");
53 MODULE_FIRMWARE("amdgpu/navi10_ta.bin");
54 MODULE_FIRMWARE("amdgpu/navi14_sos.bin");
55 MODULE_FIRMWARE("amdgpu/navi14_asd.bin");
56 MODULE_FIRMWARE("amdgpu/navi14_ta.bin");
57 MODULE_FIRMWARE("amdgpu/navi12_sos.bin");
58 MODULE_FIRMWARE("amdgpu/navi12_asd.bin");
59 MODULE_FIRMWARE("amdgpu/navi12_ta.bin");
60 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
61 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
62 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
63
64 /* address block */
65 #define smnMP1_FIRMWARE_FLAGS 0x3010024
66 /* navi10 reg offset define */
67 #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61
68 #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62
69 #define mmSDMA0_UCODE_ADDR_NV10 0x5880
70 #define mmSDMA0_UCODE_DATA_NV10 0x5881
71 /* memory training timeout define */
72 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000
73
psp_v11_0_init_microcode(struct psp_context * psp)74 static int psp_v11_0_init_microcode(struct psp_context *psp)
75 {
76 struct amdgpu_device *adev = psp->adev;
77 const char *chip_name;
78 char fw_name[30];
79 int err = 0;
80 const struct psp_firmware_header_v1_0 *sos_hdr;
81 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
82 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
83 const struct psp_firmware_header_v1_0 *asd_hdr;
84 const struct ta_firmware_header_v1_0 *ta_hdr;
85
86 DRM_DEBUG("\n");
87
88 switch (adev->asic_type) {
89 case CHIP_VEGA20:
90 chip_name = "vega20";
91 break;
92 case CHIP_NAVI10:
93 chip_name = "navi10";
94 break;
95 case CHIP_NAVI14:
96 chip_name = "navi14";
97 break;
98 case CHIP_NAVI12:
99 chip_name = "navi12";
100 break;
101 case CHIP_ARCTURUS:
102 chip_name = "arcturus";
103 break;
104 default:
105 BUG();
106 }
107
108 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
109 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
110 if (err)
111 goto out;
112
113 err = amdgpu_ucode_validate(adev->psp.sos_fw);
114 if (err)
115 goto out;
116
117 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
118 amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
119
120 switch (sos_hdr->header.header_version_major) {
121 case 1:
122 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
123 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version);
124 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes);
125 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes);
126 adev->psp.sys_start_addr = (const uint8_t *)sos_hdr +
127 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
128 adev->psp.sos_start_addr = (const uint8_t *)adev->psp.sys_start_addr +
129 le32_to_cpu(sos_hdr->sos_offset_bytes);
130 if (sos_hdr->header.header_version_minor == 1) {
131 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
132 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes);
133 adev->psp.toc_start_addr = (const uint8_t *)adev->psp.sys_start_addr +
134 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes);
135 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes);
136 adev->psp.kdb_start_addr = (const uint8_t *)adev->psp.sys_start_addr +
137 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes);
138 }
139 if (sos_hdr->header.header_version_minor == 2) {
140 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
141 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes);
142 adev->psp.kdb_start_addr = (const uint8_t *)adev->psp.sys_start_addr +
143 le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes);
144 }
145 break;
146 default:
147 dev_err(adev->dev,
148 "Unsupported psp sos firmware\n");
149 err = -EINVAL;
150 goto out;
151 }
152
153 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
154 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
155 if (err)
156 goto out1;
157
158 err = amdgpu_ucode_validate(adev->psp.asd_fw);
159 if (err)
160 goto out1;
161
162 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
163 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
164 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
165 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
166 adev->psp.asd_start_addr = (const uint8_t *)asd_hdr +
167 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
168
169 switch (adev->asic_type) {
170 case CHIP_VEGA20:
171 case CHIP_ARCTURUS:
172 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
173 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
174 if (err) {
175 release_firmware(adev->psp.ta_fw);
176 adev->psp.ta_fw = NULL;
177 dev_info(adev->dev,
178 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
179 } else {
180 err = amdgpu_ucode_validate(adev->psp.ta_fw);
181 if (err)
182 goto out2;
183
184 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
185 adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
186 adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
187 adev->psp.ta_xgmi_start_addr = (const uint8_t *)ta_hdr +
188 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
189 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
190 adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version);
191 adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes);
192 adev->psp.ta_ras_start_addr = (const uint8_t *)adev->psp.ta_xgmi_start_addr +
193 le32_to_cpu(ta_hdr->ta_ras_offset_bytes);
194 }
195 break;
196 case CHIP_NAVI10:
197 case CHIP_NAVI14:
198 case CHIP_NAVI12:
199 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
200 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
201 if (err) {
202 release_firmware(adev->psp.ta_fw);
203 adev->psp.ta_fw = NULL;
204 dev_info(adev->dev,
205 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
206 } else {
207 err = amdgpu_ucode_validate(adev->psp.ta_fw);
208 if (err)
209 goto out2;
210
211 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
212 adev->psp.ta_hdcp_ucode_version = le32_to_cpu(ta_hdr->ta_hdcp_ucode_version);
213 adev->psp.ta_hdcp_ucode_size = le32_to_cpu(ta_hdr->ta_hdcp_size_bytes);
214 adev->psp.ta_hdcp_start_addr = (const uint8_t *)ta_hdr +
215 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
216
217 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
218
219 adev->psp.ta_dtm_ucode_version = le32_to_cpu(ta_hdr->ta_dtm_ucode_version);
220 adev->psp.ta_dtm_ucode_size = le32_to_cpu(ta_hdr->ta_dtm_size_bytes);
221 adev->psp.ta_dtm_start_addr = (const uint8_t *)adev->psp.ta_hdcp_start_addr +
222 le32_to_cpu(ta_hdr->ta_dtm_offset_bytes);
223 }
224 break;
225 default:
226 BUG();
227 }
228
229 return 0;
230
231 out2:
232 release_firmware(adev->psp.ta_fw);
233 adev->psp.ta_fw = NULL;
234 out1:
235 release_firmware(adev->psp.asd_fw);
236 adev->psp.asd_fw = NULL;
237 out:
238 dev_err(adev->dev,
239 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
240 release_firmware(adev->psp.sos_fw);
241 adev->psp.sos_fw = NULL;
242
243 return err;
244 }
245
psp_v11_0_wait_for_bootloader(struct psp_context * psp)246 int psp_v11_0_wait_for_bootloader(struct psp_context *psp)
247 {
248 struct amdgpu_device *adev = psp->adev;
249
250 int ret;
251 int retry_loop;
252
253 for (retry_loop = 0; retry_loop < 10; retry_loop++) {
254 /* Wait for bootloader to signify that is
255 ready having bit 31 of C2PMSG_35 set to 1 */
256 ret = psp_wait_for(psp,
257 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
258 0x80000000,
259 0x80000000,
260 false);
261
262 if (ret == 0)
263 return 0;
264 }
265
266 return ret;
267 }
268
psp_v11_0_is_sos_alive(struct psp_context * psp)269 static bool psp_v11_0_is_sos_alive(struct psp_context *psp)
270 {
271 struct amdgpu_device *adev = psp->adev;
272 uint32_t sol_reg;
273
274 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
275
276 return sol_reg != 0x0;
277 }
278
psp_v11_0_bootloader_load_kdb(struct psp_context * psp)279 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
280 {
281 int ret;
282 uint32_t psp_gfxdrv_command_reg = 0;
283 struct amdgpu_device *adev = psp->adev;
284
285 /* Check tOS sign of life register to confirm sys driver and sOS
286 * are already been loaded.
287 */
288 if (psp_v11_0_is_sos_alive(psp)) {
289 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
290 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
291 return 0;
292 }
293
294 ret = psp_v11_0_wait_for_bootloader(psp);
295 if (ret)
296 return ret;
297
298 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
299
300 /* Copy PSP KDB binary to memory */
301 memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size);
302
303 /* Provide the PSP KDB to bootloader */
304 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
305 (uint32_t)(psp->fw_pri_mc_addr >> 20));
306 psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE;
307 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
308 psp_gfxdrv_command_reg);
309
310 ret = psp_v11_0_wait_for_bootloader(psp);
311
312 return ret;
313 }
314
psp_v11_0_bootloader_load_sysdrv(struct psp_context * psp)315 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
316 {
317 int ret;
318 uint32_t psp_gfxdrv_command_reg = 0;
319 struct amdgpu_device *adev = psp->adev;
320
321 /* Check sOS sign of life register to confirm sys driver and sOS
322 * are already been loaded.
323 */
324 if (psp_v11_0_is_sos_alive(psp)) {
325 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
326 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
327 return 0;
328 }
329
330 ret = psp_v11_0_wait_for_bootloader(psp);
331 if (ret)
332 return ret;
333
334 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
335
336 /* Copy PSP System Driver binary to memory */
337 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
338
339 /* Provide the sys driver to bootloader */
340 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
341 (uint32_t)(psp->fw_pri_mc_addr >> 20));
342 psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
343 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
344 psp_gfxdrv_command_reg);
345
346 /* there might be handshake issue with hardware which needs delay */
347 mdelay(20);
348
349 ret = psp_v11_0_wait_for_bootloader(psp);
350
351 return ret;
352 }
353
psp_v11_0_bootloader_load_sos(struct psp_context * psp)354 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
355 {
356 int ret;
357 unsigned int psp_gfxdrv_command_reg = 0;
358 struct amdgpu_device *adev = psp->adev;
359
360 /* Check sOS sign of life register to confirm sys driver and sOS
361 * are already been loaded.
362 */
363 if (psp_v11_0_is_sos_alive(psp))
364 return 0;
365
366 ret = psp_v11_0_wait_for_bootloader(psp);
367 if (ret)
368 return ret;
369
370 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
371
372 /* Copy Secure OS binary to PSP memory */
373 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
374
375 /* Provide the PSP secure OS to bootloader */
376 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
377 (uint32_t)(psp->fw_pri_mc_addr >> 20));
378 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
379 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
380 psp_gfxdrv_command_reg);
381
382 /* there might be handshake issue with hardware which needs delay */
383 mdelay(20);
384 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
385 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
386 0, true);
387
388 return ret;
389 }
390
psp_v11_0_reroute_ih(struct psp_context * psp)391 static void psp_v11_0_reroute_ih(struct psp_context *psp)
392 {
393 struct amdgpu_device *adev = psp->adev;
394 uint32_t tmp;
395
396 /* Change IH ring for VMC */
397 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
398 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
399 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
400
401 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
402 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
403 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
404
405 mdelay(20);
406 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
407 0x80000000, 0x8000FFFF, false);
408
409 /* Change IH ring for UMC */
410 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
411 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
412
413 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
414 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
415 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
416
417 mdelay(20);
418 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
419 0x80000000, 0x8000FFFF, false);
420 }
421
psp_v11_0_ring_init(struct psp_context * psp,enum psp_ring_type ring_type)422 static int psp_v11_0_ring_init(struct psp_context *psp,
423 enum psp_ring_type ring_type)
424 {
425 int ret = 0;
426 struct psp_ring *ring;
427 struct amdgpu_device *adev = psp->adev;
428
429 psp_v11_0_reroute_ih(psp);
430
431 ring = &psp->km_ring;
432
433 ring->ring_type = ring_type;
434
435 /* allocate 4k Page of Local Frame Buffer memory for ring */
436 ring->ring_size = 0x1000;
437 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
438 AMDGPU_GEM_DOMAIN_VRAM,
439 &adev->firmware.rbuf,
440 &ring->ring_mem_mc_addr,
441 (void **)&ring->ring_mem);
442 if (ret) {
443 ring->ring_size = 0;
444 return ret;
445 }
446
447 return 0;
448 }
449
psp_v11_0_support_vmr_ring(struct psp_context * psp)450 static bool psp_v11_0_support_vmr_ring(struct psp_context *psp)
451 {
452 if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
453 return true;
454 return false;
455 }
456
psp_v11_0_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)457 static int psp_v11_0_ring_stop(struct psp_context *psp,
458 enum psp_ring_type ring_type)
459 {
460 int ret = 0;
461 struct amdgpu_device *adev = psp->adev;
462
463 /* Write the ring destroy command*/
464 if (psp_v11_0_support_vmr_ring(psp))
465 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
466 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
467 else
468 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
469 GFX_CTRL_CMD_ID_DESTROY_RINGS);
470
471 /* there might be handshake issue with hardware which needs delay */
472 mdelay(20);
473
474 /* Wait for response flag (bit 31) */
475 if (psp_v11_0_support_vmr_ring(psp))
476 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
477 0x80000000, 0x80000000, false);
478 else
479 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
480 0x80000000, 0x80000000, false);
481
482 return ret;
483 }
484
psp_v11_0_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)485 static int psp_v11_0_ring_create(struct psp_context *psp,
486 enum psp_ring_type ring_type)
487 {
488 int ret = 0;
489 unsigned int psp_ring_reg = 0;
490 struct psp_ring *ring = &psp->km_ring;
491 struct amdgpu_device *adev = psp->adev;
492
493 if (psp_v11_0_support_vmr_ring(psp)) {
494 ret = psp_v11_0_ring_stop(psp, ring_type);
495 if (ret) {
496 DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n");
497 return ret;
498 }
499
500 /* Write low address of the ring to C2PMSG_102 */
501 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
502 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
503 /* Write high address of the ring to C2PMSG_103 */
504 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
505 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
506
507 /* Write the ring initialization command to C2PMSG_101 */
508 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
509 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
510
511 /* there might be handshake issue with hardware which needs delay */
512 mdelay(20);
513
514 /* Wait for response flag (bit 31) in C2PMSG_101 */
515 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
516 0x80000000, 0x8000FFFF, false);
517
518 } else {
519 /* Wait for sOS ready for ring creation */
520 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
521 0x80000000, 0x80000000, false);
522 if (ret) {
523 DRM_ERROR("Failed to wait for sOS ready for ring creation\n");
524 return ret;
525 }
526
527 /* Write low address of the ring to C2PMSG_69 */
528 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
529 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
530 /* Write high address of the ring to C2PMSG_70 */
531 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
532 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
533 /* Write size of ring to C2PMSG_71 */
534 psp_ring_reg = ring->ring_size;
535 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
536 /* Write the ring initialization command to C2PMSG_64 */
537 psp_ring_reg = ring_type;
538 psp_ring_reg = psp_ring_reg << 16;
539 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
540
541 /* there might be handshake issue with hardware which needs delay */
542 mdelay(20);
543
544 /* Wait for response flag (bit 31) in C2PMSG_64 */
545 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
546 0x80000000, 0x8000FFFF, false);
547 }
548
549 return ret;
550 }
551
552
psp_v11_0_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)553 static int psp_v11_0_ring_destroy(struct psp_context *psp,
554 enum psp_ring_type ring_type)
555 {
556 int ret = 0;
557 struct psp_ring *ring = &psp->km_ring;
558 struct amdgpu_device *adev = psp->adev;
559
560 ret = psp_v11_0_ring_stop(psp, ring_type);
561 if (ret)
562 DRM_ERROR("Fail to stop psp ring\n");
563
564 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
565 &ring->ring_mem_mc_addr,
566 (void **)&ring->ring_mem);
567
568 return ret;
569 }
570
571 static int
psp_v11_0_sram_map(struct amdgpu_device * adev,unsigned int * sram_offset,unsigned int * sram_addr_reg_offset,unsigned int * sram_data_reg_offset,enum AMDGPU_UCODE_ID ucode_id)572 psp_v11_0_sram_map(struct amdgpu_device *adev,
573 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
574 unsigned int *sram_data_reg_offset,
575 enum AMDGPU_UCODE_ID ucode_id)
576 {
577 int ret = 0;
578
579 switch (ucode_id) {
580 /* TODO: needs to confirm */
581 #if 0
582 case AMDGPU_UCODE_ID_SMC:
583 *sram_offset = 0;
584 *sram_addr_reg_offset = 0;
585 *sram_data_reg_offset = 0;
586 break;
587 #endif
588
589 case AMDGPU_UCODE_ID_CP_CE:
590 *sram_offset = 0x0;
591 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
592 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
593 break;
594
595 case AMDGPU_UCODE_ID_CP_PFP:
596 *sram_offset = 0x0;
597 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
598 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
599 break;
600
601 case AMDGPU_UCODE_ID_CP_ME:
602 *sram_offset = 0x0;
603 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
604 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
605 break;
606
607 case AMDGPU_UCODE_ID_CP_MEC1:
608 *sram_offset = 0x10000;
609 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
610 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
611 break;
612
613 case AMDGPU_UCODE_ID_CP_MEC2:
614 *sram_offset = 0x10000;
615 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
616 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
617 break;
618
619 case AMDGPU_UCODE_ID_RLC_G:
620 *sram_offset = 0x2000;
621 if (adev->asic_type < CHIP_NAVI10) {
622 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
623 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
624 } else {
625 *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_ADDR_NV10;
626 *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_DATA_NV10;
627 }
628 break;
629
630 case AMDGPU_UCODE_ID_SDMA0:
631 *sram_offset = 0x0;
632 if (adev->asic_type < CHIP_NAVI10) {
633 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
634 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
635 } else {
636 *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_ADDR_NV10;
637 *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_DATA_NV10;
638 }
639 break;
640
641 /* TODO: needs to confirm */
642 #if 0
643 case AMDGPU_UCODE_ID_SDMA1:
644 *sram_offset = ;
645 *sram_addr_reg_offset = ;
646 break;
647
648 case AMDGPU_UCODE_ID_UVD:
649 *sram_offset = ;
650 *sram_addr_reg_offset = ;
651 break;
652
653 case AMDGPU_UCODE_ID_VCE:
654 *sram_offset = ;
655 *sram_addr_reg_offset = ;
656 break;
657 #endif
658
659 case AMDGPU_UCODE_ID_MAXIMUM:
660 default:
661 ret = -EINVAL;
662 break;
663 }
664
665 return ret;
666 }
667
psp_v11_0_compare_sram_data(struct psp_context * psp,struct amdgpu_firmware_info * ucode,enum AMDGPU_UCODE_ID ucode_type)668 static bool psp_v11_0_compare_sram_data(struct psp_context *psp,
669 struct amdgpu_firmware_info *ucode,
670 enum AMDGPU_UCODE_ID ucode_type)
671 {
672 int err = 0;
673 unsigned int fw_sram_reg_val = 0;
674 unsigned int fw_sram_addr_reg_offset = 0;
675 unsigned int fw_sram_data_reg_offset = 0;
676 unsigned int ucode_size;
677 uint32_t *ucode_mem = NULL;
678 struct amdgpu_device *adev = psp->adev;
679
680 err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
681 &fw_sram_data_reg_offset, ucode_type);
682 if (err)
683 return false;
684
685 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
686
687 ucode_size = ucode->ucode_size;
688 ucode_mem = (uint32_t *)ucode->kaddr;
689 while (ucode_size) {
690 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
691
692 if (*ucode_mem != fw_sram_reg_val)
693 return false;
694
695 ucode_mem++;
696 /* 4 bytes */
697 ucode_size -= 4;
698 }
699
700 return true;
701 }
702
psp_v11_0_mode1_reset(struct psp_context * psp)703 static int psp_v11_0_mode1_reset(struct psp_context *psp)
704 {
705 int ret;
706 uint32_t offset;
707 struct amdgpu_device *adev = psp->adev;
708
709 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
710
711 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
712
713 if (ret) {
714 DRM_INFO("psp is not working correctly before mode1 reset!\n");
715 return -EINVAL;
716 }
717
718 /*send the mode 1 reset command*/
719 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
720
721 msleep(500);
722
723 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
724
725 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
726
727 if (ret) {
728 DRM_INFO("psp mode 1 reset failed!\n");
729 return -EINVAL;
730 }
731
732 DRM_INFO("psp mode1 reset succeed \n");
733
734 return 0;
735 }
736
737 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready.
738 * For now, return success and hack the hive_id so high level code can
739 * start testing
740 */
psp_v11_0_xgmi_get_topology_info(struct psp_context * psp,int number_devices,struct psp_xgmi_topology_info * topology)741 static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp,
742 int number_devices, struct psp_xgmi_topology_info *topology)
743 {
744 struct ta_xgmi_shared_memory *xgmi_cmd;
745 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
746 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
747 int i;
748 int ret;
749
750 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
751 return -EINVAL;
752
753 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
754 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
755
756 /* Fill in the shared memory with topology information as input */
757 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
758 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
759 topology_info_input->num_nodes = number_devices;
760
761 for (i = 0; i < topology_info_input->num_nodes; i++) {
762 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
763 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
764 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
765 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
766 }
767
768 /* Invoke xgmi ta to get the topology information */
769 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
770 if (ret)
771 return ret;
772
773 /* Read the output topology information from the shared memory */
774 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
775 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
776 for (i = 0; i < topology->num_nodes; i++) {
777 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
778 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
779 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
780 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
781 }
782
783 return 0;
784 }
785
psp_v11_0_xgmi_set_topology_info(struct psp_context * psp,int number_devices,struct psp_xgmi_topology_info * topology)786 static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp,
787 int number_devices, struct psp_xgmi_topology_info *topology)
788 {
789 struct ta_xgmi_shared_memory *xgmi_cmd;
790 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
791 int i;
792
793 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
794 return -EINVAL;
795
796 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
797 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
798
799 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
800 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
801 topology_info_input->num_nodes = number_devices;
802
803 for (i = 0; i < topology_info_input->num_nodes; i++) {
804 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
805 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
806 topology_info_input->nodes[i].is_sharing_enabled = 1;
807 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
808 }
809
810 /* Invoke xgmi ta to set topology information */
811 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
812 }
813
psp_v11_0_xgmi_get_hive_id(struct psp_context * psp,uint64_t * hive_id)814 static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
815 {
816 struct ta_xgmi_shared_memory *xgmi_cmd;
817 int ret;
818
819 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
820 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
821
822 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
823
824 /* Invoke xgmi ta to get hive id */
825 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
826 if (ret)
827 return ret;
828
829 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
830
831 return 0;
832 }
833
psp_v11_0_xgmi_get_node_id(struct psp_context * psp,uint64_t * node_id)834 static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
835 {
836 struct ta_xgmi_shared_memory *xgmi_cmd;
837 int ret;
838
839 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
840 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
841
842 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
843
844 /* Invoke xgmi ta to get the node id */
845 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
846 if (ret)
847 return ret;
848
849 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
850
851 return 0;
852 }
853
psp_v11_0_ras_trigger_error(struct psp_context * psp,struct ta_ras_trigger_error_input * info)854 static int psp_v11_0_ras_trigger_error(struct psp_context *psp,
855 struct ta_ras_trigger_error_input *info)
856 {
857 struct ta_ras_shared_memory *ras_cmd;
858 int ret;
859
860 if (!psp->ras.ras_initialized)
861 return -EINVAL;
862
863 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
864 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
865
866 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
867 ras_cmd->ras_in_message.trigger_error = *info;
868
869 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
870 if (ret)
871 return -EINVAL;
872
873 return ras_cmd->ras_status;
874 }
875
psp_v11_0_ras_cure_posion(struct psp_context * psp,uint64_t * mode_ptr)876 static int psp_v11_0_ras_cure_posion(struct psp_context *psp, uint64_t *mode_ptr)
877 {
878 #if 0
879 // not support yet.
880 struct ta_ras_shared_memory *ras_cmd;
881 int ret;
882
883 if (!psp->ras.ras_initialized)
884 return -EINVAL;
885
886 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
887 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
888
889 ras_cmd->cmd_id = TA_RAS_COMMAND__CURE_POISON;
890 ras_cmd->ras_in_message.cure_poison.mode_ptr = mode_ptr;
891
892 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
893 if (ret)
894 return -EINVAL;
895
896 return ras_cmd->ras_status;
897 #else
898 return -EINVAL;
899 #endif
900 }
901
psp_v11_0_rlc_autoload_start(struct psp_context * psp)902 static int psp_v11_0_rlc_autoload_start(struct psp_context *psp)
903 {
904 return psp_rlc_autoload_start(psp);
905 }
906
psp_v11_0_memory_training_send_msg(struct psp_context * psp,int msg)907 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg)
908 {
909 int ret;
910 int i;
911 uint32_t data_32;
912 int max_wait;
913 struct amdgpu_device *adev = psp->adev;
914
915 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
916 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32);
917 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg);
918
919 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
920 for (i = 0; i < max_wait; i++) {
921 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
922 0x80000000, 0x80000000, false);
923 if (ret == 0)
924 break;
925 }
926 if (i < max_wait)
927 ret = 0;
928 else
929 ret = -ETIME;
930
931 DRM_DEBUG("training %s %s, cost %d @ %d ms\n",
932 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
933 (ret == 0) ? "succeed" : "failed",
934 i, adev->usec_timeout/1000);
935 return ret;
936 }
937
psp_v11_0_memory_training_fini(struct psp_context * psp)938 static void psp_v11_0_memory_training_fini(struct psp_context *psp)
939 {
940 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
941
942 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
943 kfree(ctx->sys_cache);
944 ctx->sys_cache = NULL;
945 }
946
psp_v11_0_memory_training_init(struct psp_context * psp)947 static int psp_v11_0_memory_training_init(struct psp_context *psp)
948 {
949 int ret;
950 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
951
952 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
953 DRM_DEBUG("memory training is not supported!\n");
954 return 0;
955 }
956
957 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
958 if (ctx->sys_cache == NULL) {
959 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
960 ret = -ENOMEM;
961 goto Err_out;
962 }
963
964 DRM_DEBUG("train_data_size:%"PRIx64",p2c_train_data_offset:%"PRIx64",c2p_train_data_offset:%"PRIx64".\n",
965 ctx->train_data_size,
966 ctx->p2c_train_data_offset,
967 ctx->c2p_train_data_offset);
968 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
969 return 0;
970
971 Err_out:
972 psp_v11_0_memory_training_fini(psp);
973 return ret;
974 }
975
976 /*
977 * save and restore proces
978 */
psp_v11_0_memory_training(struct psp_context * psp,uint32_t ops)979 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
980 {
981 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
982 uint32_t *pcache = (uint32_t*)ctx->sys_cache;
983 struct amdgpu_device *adev = psp->adev;
984 uint32_t p2c_header[4];
985 uint32_t sz;
986 void *buf;
987 int ret;
988
989 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
990 DRM_DEBUG("Memory training is not supported.\n");
991 return 0;
992 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
993 DRM_ERROR("Memory training initialization failure.\n");
994 return -EINVAL;
995 }
996
997 if (psp_v11_0_is_sos_alive(psp)) {
998 DRM_DEBUG("SOS is alive, skip memory training.\n");
999 return 0;
1000 }
1001
1002 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
1003 DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
1004 pcache[0], pcache[1], pcache[2], pcache[3],
1005 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
1006
1007 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
1008 DRM_DEBUG("Short training depends on restore.\n");
1009 ops |= PSP_MEM_TRAIN_RESTORE;
1010 }
1011
1012 if ((ops & PSP_MEM_TRAIN_RESTORE) &&
1013 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
1014 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n");
1015 ops |= PSP_MEM_TRAIN_SAVE;
1016 }
1017
1018 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
1019 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
1020 pcache[3] == p2c_header[3])) {
1021 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
1022 ops |= PSP_MEM_TRAIN_SAVE;
1023 }
1024
1025 if ((ops & PSP_MEM_TRAIN_SAVE) &&
1026 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
1027 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n");
1028 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
1029 }
1030
1031 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
1032 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
1033 ops |= PSP_MEM_TRAIN_SAVE;
1034 }
1035
1036 DRM_DEBUG("Memory training ops:%x.\n", ops);
1037
1038 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
1039 /*
1040 * Long traing will encroach certain mount of bottom VRAM,
1041 * saving the content of this bottom VRAM to system memory
1042 * before training, and restoring it after training to avoid
1043 * VRAM corruption.
1044 */
1045 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
1046
1047 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
1048 DRM_ERROR("visible_vram_size %"PRIx64" or aper_base_kaddr %p is not initialized.\n",
1049 adev->gmc.visible_vram_size,
1050 adev->mman.aper_base_kaddr);
1051 return -EINVAL;
1052 }
1053
1054 buf = vmalloc(sz);
1055 if (!buf) {
1056 DRM_ERROR("failed to allocate system memory.\n");
1057 return -ENOMEM;
1058 }
1059
1060 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
1061 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
1062 if (ret) {
1063 DRM_ERROR("Send long training msg failed.\n");
1064 vfree(buf);
1065 return ret;
1066 }
1067
1068 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
1069 adev->nbio.funcs->hdp_flush(adev, NULL);
1070 vfree(buf);
1071 }
1072
1073 if (ops & PSP_MEM_TRAIN_SAVE) {
1074 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
1075 }
1076
1077 if (ops & PSP_MEM_TRAIN_RESTORE) {
1078 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
1079 }
1080
1081 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
1082 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
1083 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
1084 if (ret) {
1085 DRM_ERROR("send training msg failed.\n");
1086 return ret;
1087 }
1088 }
1089 ctx->training_cnt++;
1090 return 0;
1091 }
1092
psp_v11_0_ring_get_wptr(struct psp_context * psp)1093 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)
1094 {
1095 uint32_t data;
1096 struct amdgpu_device *adev = psp->adev;
1097
1098 if (psp_v11_0_support_vmr_ring(psp))
1099 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
1100 else
1101 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
1102
1103 return data;
1104 }
1105
psp_v11_0_ring_set_wptr(struct psp_context * psp,uint32_t value)1106 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
1107 {
1108 struct amdgpu_device *adev = psp->adev;
1109
1110 if (psp_v11_0_support_vmr_ring(psp)) {
1111 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
1112 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
1113 } else
1114 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
1115 }
1116
1117 static const struct psp_funcs psp_v11_0_funcs = {
1118 .init_microcode = psp_v11_0_init_microcode,
1119 .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
1120 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
1121 .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
1122 .ring_init = psp_v11_0_ring_init,
1123 .ring_create = psp_v11_0_ring_create,
1124 .ring_stop = psp_v11_0_ring_stop,
1125 .ring_destroy = psp_v11_0_ring_destroy,
1126 .compare_sram_data = psp_v11_0_compare_sram_data,
1127 .mode1_reset = psp_v11_0_mode1_reset,
1128 .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info,
1129 .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info,
1130 .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id,
1131 .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id,
1132 .support_vmr_ring = psp_v11_0_support_vmr_ring,
1133 .ras_trigger_error = psp_v11_0_ras_trigger_error,
1134 .ras_cure_posion = psp_v11_0_ras_cure_posion,
1135 .rlc_autoload_start = psp_v11_0_rlc_autoload_start,
1136 .mem_training_init = psp_v11_0_memory_training_init,
1137 .mem_training_fini = psp_v11_0_memory_training_fini,
1138 .mem_training = psp_v11_0_memory_training,
1139 .ring_get_wptr = psp_v11_0_ring_get_wptr,
1140 .ring_set_wptr = psp_v11_0_ring_set_wptr,
1141 };
1142
psp_v11_0_set_psp_funcs(struct psp_context * psp)1143 void psp_v11_0_set_psp_funcs(struct psp_context *psp)
1144 {
1145 psp->funcs = &psp_v11_0_funcs;
1146 }
1147