xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/amdgpu_pppcielanes.c (revision 41ec02673d281bbb3d38e6c78504ce6e30c228c1)
1 /*	$NetBSD: amdgpu_pppcielanes.c,v 1.2 2021/12/18 23:45:26 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2015 Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  */
25 
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_pppcielanes.c,v 1.2 2021/12/18 23:45:26 riastradh Exp $");
28 
29 #include <linux/types.h>
30 #include "atom-types.h"
31 #include "atombios.h"
32 #include "pppcielanes.h"
33 
34 /** \file
35  * Functions related to PCIe lane changes.
36  */
37 
38 /* For converting from number of lanes to lane bits.  */
39 static const unsigned char pp_r600_encode_lanes[] = {
40 	0,          /*  0 Not Supported  */
41 	1,          /*  1 Lane  */
42 	2,          /*  2 Lanes  */
43 	0,          /*  3 Not Supported  */
44 	3,          /*  4 Lanes  */
45 	0,          /*  5 Not Supported  */
46 	0,          /*  6 Not Supported  */
47 	0,          /*  7 Not Supported  */
48 	4,          /*  8 Lanes  */
49 	0,          /*  9 Not Supported  */
50 	0,          /* 10 Not Supported  */
51 	0,          /* 11 Not Supported  */
52 	5,          /* 12 Lanes (Not actually supported)  */
53 	0,          /* 13 Not Supported  */
54 	0,          /* 14 Not Supported  */
55 	0,          /* 15 Not Supported  */
56 	6           /* 16 Lanes  */
57 };
58 
59 static const unsigned char pp_r600_decoded_lanes[8] = { 16, 1, 2, 4, 8, 12, 16, };
60 
encode_pcie_lane_width(uint32_t num_lanes)61 uint8_t encode_pcie_lane_width(uint32_t num_lanes)
62 {
63 	return pp_r600_encode_lanes[num_lanes];
64 }
65 
decode_pcie_lane_width(uint32_t num_lanes)66 uint8_t decode_pcie_lane_width(uint32_t num_lanes)
67 {
68 	return pp_r600_decoded_lanes[num_lanes];
69 }
70