1 /* $NetBSD: amdgpu_nbio_v2_3.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
2
3 /*
4 * Copyright 2019 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25 #include <sys/cdefs.h>
26 __KERNEL_RCSID(0, "$NetBSD: amdgpu_nbio_v2_3.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
27
28 #include "amdgpu.h"
29 #include "amdgpu_atombios.h"
30 #include "nbio_v2_3.h"
31
32 #include "nbio/nbio_2_3_default.h"
33 #include "nbio/nbio_2_3_offset.h"
34 #include "nbio/nbio_2_3_sh_mask.h"
35 #include <uapi/linux/kfd_ioctl.h>
36
37 #define smnPCIE_CONFIG_CNTL 0x11180044
38 #define smnCPM_CONTROL 0x11180460
39 #define smnPCIE_CNTL2 0x11180070
40
41
nbio_v2_3_remap_hdp_registers(struct amdgpu_device * adev)42 static void nbio_v2_3_remap_hdp_registers(struct amdgpu_device *adev)
43 {
44 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
45 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
46 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
47 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
48 }
49
nbio_v2_3_get_rev_id(struct amdgpu_device * adev)50 static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev)
51 {
52 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
53
54 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
55 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
56
57 return tmp;
58 }
59
nbio_v2_3_mc_access_enable(struct amdgpu_device * adev,bool enable)60 static void nbio_v2_3_mc_access_enable(struct amdgpu_device *adev, bool enable)
61 {
62 if (enable)
63 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
64 BIF_FB_EN__FB_READ_EN_MASK |
65 BIF_FB_EN__FB_WRITE_EN_MASK);
66 else
67 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
68 }
69
nbio_v2_3_hdp_flush(struct amdgpu_device * adev,struct amdgpu_ring * ring)70 static void nbio_v2_3_hdp_flush(struct amdgpu_device *adev,
71 struct amdgpu_ring *ring)
72 {
73 if (!ring || !ring->funcs->emit_wreg)
74 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
75 else
76 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
77 }
78
nbio_v2_3_get_memsize(struct amdgpu_device * adev)79 static u32 nbio_v2_3_get_memsize(struct amdgpu_device *adev)
80 {
81 return RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);
82 }
83
nbio_v2_3_sdma_doorbell_range(struct amdgpu_device * adev,int instance,bool use_doorbell,int doorbell_index,int doorbell_size)84 static void nbio_v2_3_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
85 bool use_doorbell, int doorbell_index,
86 int doorbell_size)
87 {
88 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
89 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
90
91 u32 doorbell_range = RREG32(reg);
92
93 if (use_doorbell) {
94 doorbell_range = REG_SET_FIELD(doorbell_range,
95 BIF_SDMA0_DOORBELL_RANGE, OFFSET,
96 doorbell_index);
97 doorbell_range = REG_SET_FIELD(doorbell_range,
98 BIF_SDMA0_DOORBELL_RANGE, SIZE,
99 doorbell_size);
100 } else
101 doorbell_range = REG_SET_FIELD(doorbell_range,
102 BIF_SDMA0_DOORBELL_RANGE, SIZE,
103 0);
104
105 WREG32(reg, doorbell_range);
106 }
107
nbio_v2_3_vcn_doorbell_range(struct amdgpu_device * adev,bool use_doorbell,int doorbell_index,int instance)108 static void nbio_v2_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
109 int doorbell_index, int instance)
110 {
111 u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
112
113 u32 doorbell_range = RREG32(reg);
114
115 if (use_doorbell) {
116 doorbell_range = REG_SET_FIELD(doorbell_range,
117 BIF_MMSCH0_DOORBELL_RANGE, OFFSET,
118 doorbell_index);
119 doorbell_range = REG_SET_FIELD(doorbell_range,
120 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8);
121 } else
122 doorbell_range = REG_SET_FIELD(doorbell_range,
123 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0);
124
125 WREG32(reg, doorbell_range);
126 }
127
nbio_v2_3_enable_doorbell_aperture(struct amdgpu_device * adev,bool enable)128 static void nbio_v2_3_enable_doorbell_aperture(struct amdgpu_device *adev,
129 bool enable)
130 {
131 WREG32_FIELD15(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN,
132 enable ? 1 : 0);
133 }
134
nbio_v2_3_enable_doorbell_selfring_aperture(struct amdgpu_device * adev,bool enable)135 static void nbio_v2_3_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
136 bool enable)
137 {
138 u32 tmp = 0;
139
140 if (enable) {
141 tmp = REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
142 DOORBELL_SELFRING_GPA_APER_EN, 1) |
143 REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
144 DOORBELL_SELFRING_GPA_APER_MODE, 1) |
145 REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
146 DOORBELL_SELFRING_GPA_APER_SIZE, 0);
147
148 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
149 lower_32_bits(adev->doorbell.base));
150 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
151 upper_32_bits(adev->doorbell.base));
152 }
153
154 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
155 tmp);
156 }
157
158
nbio_v2_3_ih_doorbell_range(struct amdgpu_device * adev,bool use_doorbell,int doorbell_index)159 static void nbio_v2_3_ih_doorbell_range(struct amdgpu_device *adev,
160 bool use_doorbell, int doorbell_index)
161 {
162 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE);
163
164 if (use_doorbell) {
165 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
166 BIF_IH_DOORBELL_RANGE, OFFSET,
167 doorbell_index);
168 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
169 BIF_IH_DOORBELL_RANGE, SIZE,
170 2);
171 } else
172 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
173 BIF_IH_DOORBELL_RANGE, SIZE,
174 0);
175
176 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
177 }
178
nbio_v2_3_ih_control(struct amdgpu_device * adev)179 static void nbio_v2_3_ih_control(struct amdgpu_device *adev)
180 {
181 u32 interrupt_cntl;
182
183 /* setup interrupt control */
184 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
185
186 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
187 /*
188 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
189 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
190 */
191 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL,
192 IH_DUMMY_RD_OVERRIDE, 0);
193
194 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
195 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL,
196 IH_REQ_NONSNOOP_EN, 0);
197
198 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
199 }
200
nbio_v2_3_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)201 static void nbio_v2_3_update_medium_grain_clock_gating(struct amdgpu_device *adev,
202 bool enable)
203 {
204 uint32_t def, data;
205
206 def = data = RREG32_PCIE(smnCPM_CONTROL);
207 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
208 data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
209 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
210 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
211 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
212 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
213 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
214 } else {
215 data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
216 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
217 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
218 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
219 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
220 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
221 }
222
223 if (def != data)
224 WREG32_PCIE(smnCPM_CONTROL, data);
225 }
226
nbio_v2_3_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)227 static void nbio_v2_3_update_medium_grain_light_sleep(struct amdgpu_device *adev,
228 bool enable)
229 {
230 uint32_t def, data;
231
232 def = data = RREG32_PCIE(smnPCIE_CNTL2);
233 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
234 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
235 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
236 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
237 } else {
238 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
239 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
240 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
241 }
242
243 if (def != data)
244 WREG32_PCIE(smnPCIE_CNTL2, data);
245 }
246
nbio_v2_3_get_clockgating_state(struct amdgpu_device * adev,u32 * flags)247 static void nbio_v2_3_get_clockgating_state(struct amdgpu_device *adev,
248 u32 *flags)
249 {
250 int data;
251
252 /* AMD_CG_SUPPORT_BIF_MGCG */
253 data = RREG32_PCIE(smnCPM_CONTROL);
254 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
255 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
256
257 /* AMD_CG_SUPPORT_BIF_LS */
258 data = RREG32_PCIE(smnPCIE_CNTL2);
259 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
260 *flags |= AMD_CG_SUPPORT_BIF_LS;
261 }
262
nbio_v2_3_get_hdp_flush_req_offset(struct amdgpu_device * adev)263 static u32 nbio_v2_3_get_hdp_flush_req_offset(struct amdgpu_device *adev)
264 {
265 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_REQ);
266 }
267
nbio_v2_3_get_hdp_flush_done_offset(struct amdgpu_device * adev)268 static u32 nbio_v2_3_get_hdp_flush_done_offset(struct amdgpu_device *adev)
269 {
270 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_DONE);
271 }
272
nbio_v2_3_get_pcie_index_offset(struct amdgpu_device * adev)273 static u32 nbio_v2_3_get_pcie_index_offset(struct amdgpu_device *adev)
274 {
275 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
276 }
277
nbio_v2_3_get_pcie_data_offset(struct amdgpu_device * adev)278 static u32 nbio_v2_3_get_pcie_data_offset(struct amdgpu_device *adev)
279 {
280 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
281 }
282
283 const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg = {
284 .ref_and_mask_cp0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK,
285 .ref_and_mask_cp1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK,
286 .ref_and_mask_cp2 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK,
287 .ref_and_mask_cp3 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK,
288 .ref_and_mask_cp4 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK,
289 .ref_and_mask_cp5 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK,
290 .ref_and_mask_cp6 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK,
291 .ref_and_mask_cp7 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK,
292 .ref_and_mask_cp8 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK,
293 .ref_and_mask_cp9 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK,
294 .ref_and_mask_sdma0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
295 .ref_and_mask_sdma1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
296 };
297
nbio_v2_3_detect_hw_virt(struct amdgpu_device * adev)298 static void nbio_v2_3_detect_hw_virt(struct amdgpu_device *adev)
299 {
300 uint32_t reg;
301
302 reg = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER);
303 if (reg & 1)
304 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
305
306 if (reg & 0x80000000)
307 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
308
309 if (!reg) {
310 if (is_virtual_machine()) /* passthrough mode exclus sriov mod */
311 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
312 }
313 }
314
nbio_v2_3_init_registers(struct amdgpu_device * adev)315 static void nbio_v2_3_init_registers(struct amdgpu_device *adev)
316 {
317 uint32_t def, data;
318
319 def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL);
320 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
321 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
322
323 if (def != data)
324 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
325 }
326
327 const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
328 .get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset,
329 .get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset,
330 .get_pcie_index_offset = nbio_v2_3_get_pcie_index_offset,
331 .get_pcie_data_offset = nbio_v2_3_get_pcie_data_offset,
332 .get_rev_id = nbio_v2_3_get_rev_id,
333 .mc_access_enable = nbio_v2_3_mc_access_enable,
334 .hdp_flush = nbio_v2_3_hdp_flush,
335 .get_memsize = nbio_v2_3_get_memsize,
336 .sdma_doorbell_range = nbio_v2_3_sdma_doorbell_range,
337 .vcn_doorbell_range = nbio_v2_3_vcn_doorbell_range,
338 .enable_doorbell_aperture = nbio_v2_3_enable_doorbell_aperture,
339 .enable_doorbell_selfring_aperture = nbio_v2_3_enable_doorbell_selfring_aperture,
340 .ih_doorbell_range = nbio_v2_3_ih_doorbell_range,
341 .update_medium_grain_clock_gating = nbio_v2_3_update_medium_grain_clock_gating,
342 .update_medium_grain_light_sleep = nbio_v2_3_update_medium_grain_light_sleep,
343 .get_clockgating_state = nbio_v2_3_get_clockgating_state,
344 .ih_control = nbio_v2_3_ih_control,
345 .init_registers = nbio_v2_3_init_registers,
346 .detect_hw_virt = nbio_v2_3_detect_hw_virt,
347 .remap_hdp_registers = nbio_v2_3_remap_hdp_registers,
348 };
349