1 /* $NetBSD: amdgpu_nbio.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
2
3 /*
4 * Copyright (C) 2019 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <sys/cdefs.h>
25 __KERNEL_RCSID(0, "$NetBSD: amdgpu_nbio.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
26
27 #include "amdgpu.h"
28 #include "amdgpu_ras.h"
29
amdgpu_nbio_ras_late_init(struct amdgpu_device * adev)30 int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev)
31 {
32 int r;
33 struct ras_ih_if ih_info = {
34 .cb = NULL,
35 };
36 struct ras_fs_if fs_info = {
37 .sysfs_name = "pcie_bif_err_count",
38 .debugfs_name = "pcie_bif_err_inject",
39 };
40
41 if (!adev->nbio.ras_if) {
42 adev->nbio.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
43 if (!adev->nbio.ras_if)
44 return -ENOMEM;
45 adev->nbio.ras_if->block = AMDGPU_RAS_BLOCK__PCIE_BIF;
46 adev->nbio.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
47 adev->nbio.ras_if->sub_block_index = 0;
48 strcpy(adev->nbio.ras_if->name, "pcie_bif");
49 }
50 ih_info.head = fs_info.head = *adev->nbio.ras_if;
51 r = amdgpu_ras_late_init(adev, adev->nbio.ras_if,
52 &fs_info, &ih_info);
53 if (r)
54 goto free;
55
56 if (amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
57 r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0);
58 if (r)
59 goto late_fini;
60 r = amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
61 if (r)
62 goto late_fini;
63 } else {
64 r = 0;
65 goto free;
66 }
67
68 return 0;
69 late_fini:
70 amdgpu_ras_late_fini(adev, adev->nbio.ras_if, &ih_info);
71 free:
72 kfree(adev->nbio.ras_if);
73 adev->nbio.ras_if = NULL;
74 return r;
75 }
76
amdgpu_nbio_ras_fini(struct amdgpu_device * adev)77 void amdgpu_nbio_ras_fini(struct amdgpu_device *adev)
78 {
79 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF) &&
80 adev->nbio.ras_if) {
81 struct ras_common_if *ras_if = adev->nbio.ras_if;
82 struct ras_ih_if ih_info = {
83 .cb = NULL,
84 };
85
86 amdgpu_ras_late_fini(adev, ras_if, &ih_info);
87 kfree(ras_if);
88 }
89 }
90