1 /* $NetBSD: amdgpu_navi14_reg_init.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */
2
3 /*
4 * Copyright 2018 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25 #include <sys/cdefs.h>
26 __KERNEL_RCSID(0, "$NetBSD: amdgpu_navi14_reg_init.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $");
27
28 #include "amdgpu.h"
29 #include "nv.h"
30
31 #include "soc15_common.h"
32 #include "navi14_ip_offset.h"
33
navi14_reg_base_init(struct amdgpu_device * adev)34 int navi14_reg_base_init(struct amdgpu_device *adev)
35 {
36 int i;
37
38 for (i = 0 ; i < MAX_INSTANCE ; ++i) {
39 adev->reg_offset[GC_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i]));
40 adev->reg_offset[HDP_HWIP][i] = (const uint32_t *)(&(HDP_BASE.instance[i]));
41 adev->reg_offset[MMHUB_HWIP][i] = (const uint32_t *)(&(MMHUB_BASE.instance[i]));
42 adev->reg_offset[ATHUB_HWIP][i] = (const uint32_t *)(&(ATHUB_BASE.instance[i]));
43 adev->reg_offset[NBIO_HWIP][i] = (const uint32_t *)(&(NBIF0_BASE.instance[i]));
44 adev->reg_offset[MP0_HWIP][i] = (const uint32_t *)(&(MP0_BASE.instance[i]));
45 adev->reg_offset[MP1_HWIP][i] = (const uint32_t *)(&(MP1_BASE.instance[i]));
46 adev->reg_offset[VCN_HWIP][i] = (const uint32_t *)(&(UVD0_BASE.instance[i]));
47 adev->reg_offset[DF_HWIP][i] = (const uint32_t *)(&(DF_BASE.instance[i]));
48 adev->reg_offset[DCE_HWIP][i] = (const uint32_t *)(&(DMU_BASE.instance[i]));
49 adev->reg_offset[OSSSYS_HWIP][i] = (const uint32_t *)(&(OSSSYS_BASE.instance[i]));
50 adev->reg_offset[SDMA0_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i]));
51 adev->reg_offset[SDMA1_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i]));
52 adev->reg_offset[SMUIO_HWIP][i] = (const uint32_t *)(&(SMUIO_BASE.instance[i]));
53 adev->reg_offset[THM_HWIP][i] = (const uint32_t *)(&(THM_BASE.instance[i]));
54 adev->reg_offset[CLK_HWIP][i] = (const uint32_t *)(&(CLK_BASE.instance[i]));
55 }
56
57 return 0;
58 }
59