1 /* $NetBSD: amdgpu_irq_service_dcn21.c,v 1.2 2021/12/18 23:45:06 riastradh Exp $ */
2
3 /*
4 * Copyright 2018 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_irq_service_dcn21.c,v 1.2 2021/12/18 23:45:06 riastradh Exp $");
30
31 #include <linux/slab.h>
32
33 #include "dm_services.h"
34
35 #include "include/logger_interface.h"
36
37 #include "../dce110/irq_service_dce110.h"
38
39 #include "dcn/dcn_2_1_0_offset.h"
40 #include "dcn/dcn_2_1_0_sh_mask.h"
41 #include "renoir_ip_offset.h"
42
43
44 #include "irq_service_dcn21.h"
45
46 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
47
to_dal_irq_source_dcn21(struct irq_service * irq_service,uint32_t src_id,uint32_t ext_id)48 enum dc_irq_source to_dal_irq_source_dcn21(
49 struct irq_service *irq_service,
50 uint32_t src_id,
51 uint32_t ext_id)
52 {
53 switch (src_id) {
54 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
55 return DC_IRQ_SOURCE_VBLANK1;
56 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
57 return DC_IRQ_SOURCE_VBLANK2;
58 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
59 return DC_IRQ_SOURCE_VBLANK3;
60 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
61 return DC_IRQ_SOURCE_VBLANK4;
62 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
63 return DC_IRQ_SOURCE_VBLANK5;
64 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
65 return DC_IRQ_SOURCE_VBLANK6;
66 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
67 return DC_IRQ_SOURCE_PFLIP1;
68 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
69 return DC_IRQ_SOURCE_PFLIP2;
70 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
71 return DC_IRQ_SOURCE_PFLIP3;
72 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
73 return DC_IRQ_SOURCE_PFLIP4;
74 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
75 return DC_IRQ_SOURCE_PFLIP5;
76 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
77 return DC_IRQ_SOURCE_PFLIP6;
78 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
79 return DC_IRQ_SOURCE_VUPDATE1;
80 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
81 return DC_IRQ_SOURCE_VUPDATE2;
82 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
83 return DC_IRQ_SOURCE_VUPDATE3;
84 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
85 return DC_IRQ_SOURCE_VUPDATE4;
86 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
87 return DC_IRQ_SOURCE_VUPDATE5;
88 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
89 return DC_IRQ_SOURCE_VUPDATE6;
90
91 case DCN_1_0__SRCID__DC_HPD1_INT:
92 /* generic src_id for all HPD and HPDRX interrupts */
93 switch (ext_id) {
94 case DCN_1_0__CTXID__DC_HPD1_INT:
95 return DC_IRQ_SOURCE_HPD1;
96 case DCN_1_0__CTXID__DC_HPD2_INT:
97 return DC_IRQ_SOURCE_HPD2;
98 case DCN_1_0__CTXID__DC_HPD3_INT:
99 return DC_IRQ_SOURCE_HPD3;
100 case DCN_1_0__CTXID__DC_HPD4_INT:
101 return DC_IRQ_SOURCE_HPD4;
102 case DCN_1_0__CTXID__DC_HPD5_INT:
103 return DC_IRQ_SOURCE_HPD5;
104 case DCN_1_0__CTXID__DC_HPD6_INT:
105 return DC_IRQ_SOURCE_HPD6;
106 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
107 return DC_IRQ_SOURCE_HPD1RX;
108 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
109 return DC_IRQ_SOURCE_HPD2RX;
110 case DCN_1_0__CTXID__DC_HPD3_RX_INT:
111 return DC_IRQ_SOURCE_HPD3RX;
112 case DCN_1_0__CTXID__DC_HPD4_RX_INT:
113 return DC_IRQ_SOURCE_HPD4RX;
114 case DCN_1_0__CTXID__DC_HPD5_RX_INT:
115 return DC_IRQ_SOURCE_HPD5RX;
116 case DCN_1_0__CTXID__DC_HPD6_RX_INT:
117 return DC_IRQ_SOURCE_HPD6RX;
118 default:
119 return DC_IRQ_SOURCE_INVALID;
120 }
121 break;
122
123 default:
124 break;
125 }
126 return DC_IRQ_SOURCE_INVALID;
127 }
128
hpd_ack(struct irq_service * irq_service,const struct irq_source_info * info)129 static bool hpd_ack(
130 struct irq_service *irq_service,
131 const struct irq_source_info *info)
132 {
133 uint32_t addr = info->status_reg;
134 uint32_t value = dm_read_reg(irq_service->ctx, addr);
135 uint32_t current_status =
136 get_reg_field_value(
137 value,
138 HPD0_DC_HPD_INT_STATUS,
139 DC_HPD_SENSE_DELAYED);
140
141 dal_irq_service_ack_generic(irq_service, info);
142
143 value = dm_read_reg(irq_service->ctx, info->enable_reg);
144
145 set_reg_field_value(
146 value,
147 current_status ? 0 : 1,
148 HPD0_DC_HPD_INT_CONTROL,
149 DC_HPD_INT_POLARITY);
150
151 dm_write_reg(irq_service->ctx, info->enable_reg, value);
152
153 return true;
154 }
155
156 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
157 .set = NULL,
158 .ack = hpd_ack
159 };
160
161 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
162 .set = NULL,
163 .ack = NULL
164 };
165
166 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
167 .set = NULL,
168 .ack = NULL
169 };
170
171 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
172 .set = NULL,
173 .ack = NULL
174 };
175
176 #undef BASE_INNER
177 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
178
179 /* compile time expand base address. */
180 #define BASE(seg) \
181 BASE_INNER(seg)
182
183
184 #define SRI(reg_name, block, id)\
185 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
186 mm ## block ## id ## _ ## reg_name
187
188
189 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
190 .enable_reg = SRI(reg1, block, reg_num),\
191 .enable_mask = \
192 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
193 .enable_value = {\
194 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
195 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
196 },\
197 .ack_reg = SRI(reg2, block, reg_num),\
198 .ack_mask = \
199 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
200 .ack_value = \
201 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
202
203
204
205 #define hpd_int_entry(reg_num)\
206 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
207 IRQ_REG_ENTRY(HPD, reg_num,\
208 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
209 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
210 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
211 .funcs = &hpd_irq_info_funcs\
212 }
213
214 #define hpd_rx_int_entry(reg_num)\
215 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
216 IRQ_REG_ENTRY(HPD, reg_num,\
217 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
218 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
219 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
220 .funcs = &hpd_rx_irq_info_funcs\
221 }
222 #define pflip_int_entry(reg_num)\
223 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
224 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
225 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
226 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
227 .funcs = &pflip_irq_info_funcs\
228 }
229
230 #define vupdate_int_entry(reg_num)\
231 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
232 IRQ_REG_ENTRY(OTG, reg_num,\
233 OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\
234 OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\
235 .funcs = &vblank_irq_info_funcs\
236 }
237
238 #define vblank_int_entry(reg_num)\
239 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
240 IRQ_REG_ENTRY(OTG, reg_num,\
241 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
242 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
243 .funcs = &vblank_irq_info_funcs\
244 }
245
246 #define dummy_irq_entry() \
247 {\
248 .funcs = &dummy_irq_info_funcs\
249 }
250
251 #define i2c_int_entry(reg_num) \
252 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
253
254 #define dp_sink_int_entry(reg_num) \
255 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
256
257 #define gpio_pad_int_entry(reg_num) \
258 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
259
260 #define dc_underflow_int_entry(reg_num) \
261 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
262
263 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
264 .set = dal_irq_service_dummy_set,
265 .ack = dal_irq_service_dummy_ack
266 };
267
268 static const struct irq_source_info
269 irq_source_info_dcn21[DAL_IRQ_SOURCES_NUMBER] = {
270 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
271 hpd_int_entry(0),
272 hpd_int_entry(1),
273 hpd_int_entry(2),
274 hpd_int_entry(3),
275 hpd_int_entry(4),
276 hpd_rx_int_entry(0),
277 hpd_rx_int_entry(1),
278 hpd_rx_int_entry(2),
279 hpd_rx_int_entry(3),
280 hpd_rx_int_entry(4),
281 i2c_int_entry(1),
282 i2c_int_entry(2),
283 i2c_int_entry(3),
284 i2c_int_entry(4),
285 i2c_int_entry(5),
286 i2c_int_entry(6),
287 dp_sink_int_entry(1),
288 dp_sink_int_entry(2),
289 dp_sink_int_entry(3),
290 dp_sink_int_entry(4),
291 dp_sink_int_entry(5),
292 dp_sink_int_entry(6),
293 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
294 pflip_int_entry(0),
295 pflip_int_entry(1),
296 pflip_int_entry(2),
297 pflip_int_entry(3),
298 [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
299 [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
300 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
301 gpio_pad_int_entry(0),
302 gpio_pad_int_entry(1),
303 gpio_pad_int_entry(2),
304 gpio_pad_int_entry(3),
305 gpio_pad_int_entry(4),
306 gpio_pad_int_entry(5),
307 gpio_pad_int_entry(6),
308 gpio_pad_int_entry(7),
309 gpio_pad_int_entry(8),
310 gpio_pad_int_entry(9),
311 gpio_pad_int_entry(10),
312 gpio_pad_int_entry(11),
313 gpio_pad_int_entry(12),
314 gpio_pad_int_entry(13),
315 gpio_pad_int_entry(14),
316 gpio_pad_int_entry(15),
317 gpio_pad_int_entry(16),
318 gpio_pad_int_entry(17),
319 gpio_pad_int_entry(18),
320 gpio_pad_int_entry(19),
321 gpio_pad_int_entry(20),
322 gpio_pad_int_entry(21),
323 gpio_pad_int_entry(22),
324 gpio_pad_int_entry(23),
325 gpio_pad_int_entry(24),
326 gpio_pad_int_entry(25),
327 gpio_pad_int_entry(26),
328 gpio_pad_int_entry(27),
329 gpio_pad_int_entry(28),
330 gpio_pad_int_entry(29),
331 gpio_pad_int_entry(30),
332 dc_underflow_int_entry(1),
333 dc_underflow_int_entry(2),
334 dc_underflow_int_entry(3),
335 dc_underflow_int_entry(4),
336 dc_underflow_int_entry(5),
337 dc_underflow_int_entry(6),
338 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
339 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
340 vupdate_int_entry(0),
341 vupdate_int_entry(1),
342 vupdate_int_entry(2),
343 vupdate_int_entry(3),
344 vupdate_int_entry(4),
345 vupdate_int_entry(5),
346 vblank_int_entry(0),
347 vblank_int_entry(1),
348 vblank_int_entry(2),
349 vblank_int_entry(3),
350 vblank_int_entry(4),
351 vblank_int_entry(5),
352 };
353
354 static const struct irq_service_funcs irq_service_funcs_dcn21 = {
355 .to_dal_irq_source = to_dal_irq_source_dcn21
356 };
357
dcn21_irq_construct(struct irq_service * irq_service,struct irq_service_init_data * init_data)358 static void dcn21_irq_construct(
359 struct irq_service *irq_service,
360 struct irq_service_init_data *init_data)
361 {
362 dal_irq_service_construct(irq_service, init_data);
363
364 irq_service->info = irq_source_info_dcn21;
365 irq_service->funcs = &irq_service_funcs_dcn21;
366 }
367
dal_irq_service_dcn21_create(struct irq_service_init_data * init_data)368 struct irq_service *dal_irq_service_dcn21_create(
369 struct irq_service_init_data *init_data)
370 {
371 struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
372 GFP_KERNEL);
373
374 if (!irq_service)
375 return NULL;
376
377 dcn21_irq_construct(irq_service, init_data);
378 return irq_service;
379 }
380