1 /* $NetBSD: amdgpu_hw_factory_dcn21.c,v 1.2 2021/12/18 23:45:05 riastradh Exp $ */
2
3 /*
4 * Copyright 2013-15 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: amdgpu_hw_factory_dcn21.c,v 1.2 2021/12/18 23:45:05 riastradh Exp $");
29
30 #include "dm_services.h"
31 #include "include/gpio_types.h"
32 #include "../hw_factory.h"
33
34
35 #include "../hw_gpio.h"
36 #include "../hw_ddc.h"
37 #include "../hw_hpd.h"
38 #include "../hw_generic.h"
39
40 #include "hw_factory_dcn21.h"
41
42 #include "dcn/dcn_2_1_0_offset.h"
43 #include "dcn/dcn_2_1_0_sh_mask.h"
44 #include "renoir_ip_offset.h"
45
46 #include "reg_helper.h"
47 #include "../hpd_regs.h"
48 /* begin *********************
49 * macros to expend register list macro defined in HW object header file */
50
51 /* DCN */
52 #define block HPD
53 #define reg_num 0
54
55 #undef BASE_INNER
56 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
57
58 #define BASE(seg) BASE_INNER(seg)
59
60
61
62 #define REG(reg_name)\
63 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
64
65 #define SF_HPD(reg_name, field_name, post_fix)\
66 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
67
68 #define REGI(reg_name, block, id)\
69 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
70 mm ## block ## id ## _ ## reg_name
71
72 #define SF(reg_name, field_name, post_fix)\
73 .field_name = reg_name ## __ ## field_name ## post_fix
74
75 /* macros to expend register list macro defined in HW object header file
76 * end *********************/
77
78
79
80 #define hpd_regs(id) \
81 {\
82 HPD_REG_LIST(id)\
83 }
84
85 static const struct hpd_registers hpd_regs[] = {
86 hpd_regs(0),
87 hpd_regs(1),
88 hpd_regs(2),
89 hpd_regs(3),
90 hpd_regs(4),
91 };
92
93 static const struct hpd_sh_mask hpd_shift = {
94 HPD_MASK_SH_LIST(__SHIFT)
95 };
96
97 static const struct hpd_sh_mask hpd_mask = {
98 HPD_MASK_SH_LIST(_MASK)
99 };
100
101 #include "../ddc_regs.h"
102
103 /* set field name */
104 #define SF_DDC(reg_name, field_name, post_fix)\
105 .field_name = reg_name ## __ ## field_name ## post_fix
106
107 static const struct ddc_registers ddc_data_regs_dcn[] = {
108 ddc_data_regs_dcn2(1),
109 ddc_data_regs_dcn2(2),
110 ddc_data_regs_dcn2(3),
111 ddc_data_regs_dcn2(4),
112 ddc_data_regs_dcn2(5),
113 };
114
115 static const struct ddc_registers ddc_clk_regs_dcn[] = {
116 ddc_clk_regs_dcn2(1),
117 ddc_clk_regs_dcn2(2),
118 ddc_clk_regs_dcn2(3),
119 ddc_clk_regs_dcn2(4),
120 ddc_clk_regs_dcn2(5),
121 };
122
123 static const struct ddc_sh_mask ddc_shift[] = {
124 DDC_MASK_SH_LIST_DCN2(__SHIFT, 1),
125 DDC_MASK_SH_LIST_DCN2(__SHIFT, 2),
126 DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
127 DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
128 DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
129 DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)
130 };
131
132 static const struct ddc_sh_mask ddc_mask[] = {
133 DDC_MASK_SH_LIST_DCN2(_MASK, 1),
134 DDC_MASK_SH_LIST_DCN2(_MASK, 2),
135 DDC_MASK_SH_LIST_DCN2(_MASK, 3),
136 DDC_MASK_SH_LIST_DCN2(_MASK, 4),
137 DDC_MASK_SH_LIST_DCN2(_MASK, 5),
138 DDC_MASK_SH_LIST_DCN2(_MASK, 6)
139 };
140
141 #include "../generic_regs.h"
142
143 /* set field name */
144 #define SF_GENERIC(reg_name, field_name, post_fix)\
145 .field_name = reg_name ## __ ## field_name ## post_fix
146
147 #define generic_regs(id) \
148 {\
149 GENERIC_REG_LIST(id)\
150 }
151
152 static const struct generic_registers generic_regs[] = {
153 generic_regs(A),
154 };
155
156 static const struct generic_sh_mask generic_shift[] = {
157 GENERIC_MASK_SH_LIST(__SHIFT, A),
158 };
159
160 static const struct generic_sh_mask generic_mask[] = {
161 GENERIC_MASK_SH_LIST(_MASK, A),
162 };
163
define_generic_registers(struct hw_gpio_pin * pin,uint32_t en)164 static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
165 {
166 struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
167
168 generic->regs = &generic_regs[en];
169 generic->shifts = &generic_shift[en];
170 generic->masks = &generic_mask[en];
171 generic->base.regs = &generic_regs[en].gpio;
172 }
173
define_ddc_registers(struct hw_gpio_pin * pin,uint32_t en)174 static void define_ddc_registers(
175 struct hw_gpio_pin *pin,
176 uint32_t en)
177 {
178 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
179
180 switch (pin->id) {
181 case GPIO_ID_DDC_DATA:
182 ddc->regs = &ddc_data_regs_dcn[en];
183 ddc->base.regs = &ddc_data_regs_dcn[en].gpio;
184 break;
185 case GPIO_ID_DDC_CLOCK:
186 ddc->regs = &ddc_clk_regs_dcn[en];
187 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;
188 break;
189 default:
190 ASSERT_CRITICAL(false);
191 return;
192 }
193
194 ddc->shifts = &ddc_shift[en];
195 ddc->masks = &ddc_mask[en];
196
197 }
198
define_hpd_registers(struct hw_gpio_pin * pin,uint32_t en)199 static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
200 {
201 struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
202
203 hpd->regs = &hpd_regs[en];
204 hpd->shifts = &hpd_shift;
205 hpd->masks = &hpd_mask;
206 hpd->base.regs = &hpd_regs[en].gpio;
207 }
208
209
210 /* fucntion table */
211 static const struct hw_factory_funcs funcs = {
212 .init_ddc_data = dal_hw_ddc_init,
213 .init_generic = dal_hw_generic_init,
214 .init_hpd = dal_hw_hpd_init,
215 .get_ddc_pin = dal_hw_ddc_get_pin,
216 .get_hpd_pin = dal_hw_hpd_get_pin,
217 .get_generic_pin = dal_hw_generic_get_pin,
218 .define_hpd_registers = define_hpd_registers,
219 .define_ddc_registers = define_ddc_registers,
220 .define_generic_registers = define_generic_registers
221 };
222 /*
223 * dal_hw_factory_dcn10_init
224 *
225 * @brief
226 * Initialize HW factory function pointers and pin info
227 *
228 * @param
229 * struct hw_factory *factory - [out] struct of function pointers
230 */
dal_hw_factory_dcn21_init(struct hw_factory * factory)231 void dal_hw_factory_dcn21_init(struct hw_factory *factory)
232 {
233 /*TODO check ASIC CAPs*/
234 factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
235 factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
236 factory->number_of_pins[GPIO_ID_GENERIC] = 4;
237 factory->number_of_pins[GPIO_ID_HPD] = 6;
238 factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28;
239 factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
240 factory->number_of_pins[GPIO_ID_SYNC] = 0;
241 factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/
242
243 factory->funcs = &funcs;
244 }
245
246