1 /* $NetBSD: amdgpu_hw_factory_dcn20.c,v 1.2 2021/12/18 23:45:05 riastradh Exp $ */
2
3 /*
4 * Copyright 2013-15 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: amdgpu_hw_factory_dcn20.c,v 1.2 2021/12/18 23:45:05 riastradh Exp $");
29
30 #include "dm_services.h"
31 #include "include/gpio_types.h"
32 #include "../hw_factory.h"
33
34
35 #include "../hw_gpio.h"
36 #include "../hw_ddc.h"
37 #include "../hw_hpd.h"
38 #include "../hw_generic.h"
39
40 #include "hw_factory_dcn20.h"
41
42
43 #include "dcn/dcn_2_0_0_offset.h"
44 #include "dcn/dcn_2_0_0_sh_mask.h"
45 #include "navi10_ip_offset.h"
46
47
48 #include "reg_helper.h"
49 #include "../hpd_regs.h"
50 /* begin *********************
51 * macros to expend register list macro defined in HW object header file */
52
53 /* DCN */
54 #define block HPD
55 #define reg_num 0
56
57 #undef BASE_INNER
58 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
59
60 #define BASE(seg) BASE_INNER(seg)
61
62
63
64 #define REG(reg_name)\
65 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
66
67 #define SF_HPD(reg_name, field_name, post_fix)\
68 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
69
70 #define REGI(reg_name, block, id)\
71 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
72 mm ## block ## id ## _ ## reg_name
73
74 #define SF(reg_name, field_name, post_fix)\
75 .field_name = reg_name ## __ ## field_name ## post_fix
76
77 /* macros to expend register list macro defined in HW object header file
78 * end *********************/
79
80
81
82 #define hpd_regs(id) \
83 {\
84 HPD_REG_LIST(id)\
85 }
86
87 static const struct hpd_registers hpd_regs[] = {
88 hpd_regs(0),
89 hpd_regs(1),
90 hpd_regs(2),
91 hpd_regs(3),
92 hpd_regs(4),
93 hpd_regs(5),
94 };
95
96 static const struct hpd_sh_mask hpd_shift = {
97 HPD_MASK_SH_LIST(__SHIFT)
98 };
99
100 static const struct hpd_sh_mask hpd_mask = {
101 HPD_MASK_SH_LIST(_MASK)
102 };
103
104 #include "../ddc_regs.h"
105
106 /* set field name */
107 #define SF_DDC(reg_name, field_name, post_fix)\
108 .field_name = reg_name ## __ ## field_name ## post_fix
109
110 static const struct ddc_registers ddc_data_regs_dcn[] = {
111 ddc_data_regs_dcn2(1),
112 ddc_data_regs_dcn2(2),
113 ddc_data_regs_dcn2(3),
114 ddc_data_regs_dcn2(4),
115 ddc_data_regs_dcn2(5),
116 ddc_data_regs_dcn2(6),
117 {
118 DDC_GPIO_VGA_REG_LIST(DATA),
119 .ddc_setup = 0,
120 .phy_aux_cntl = 0,
121 .dc_gpio_aux_ctrl_5 = 0
122 }
123 };
124
125 static const struct ddc_registers ddc_clk_regs_dcn[] = {
126 ddc_clk_regs_dcn2(1),
127 ddc_clk_regs_dcn2(2),
128 ddc_clk_regs_dcn2(3),
129 ddc_clk_regs_dcn2(4),
130 ddc_clk_regs_dcn2(5),
131 ddc_clk_regs_dcn2(6),
132 {
133 DDC_GPIO_VGA_REG_LIST(CLK),
134 .ddc_setup = 0,
135 .phy_aux_cntl = 0,
136 .dc_gpio_aux_ctrl_5 = 0
137 }
138 };
139
140 static const struct ddc_sh_mask ddc_shift[] = {
141 DDC_MASK_SH_LIST_DCN2(__SHIFT, 1),
142 DDC_MASK_SH_LIST_DCN2(__SHIFT, 2),
143 DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
144 DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
145 DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
146 DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)
147 };
148
149 static const struct ddc_sh_mask ddc_mask[] = {
150 DDC_MASK_SH_LIST_DCN2(_MASK, 1),
151 DDC_MASK_SH_LIST_DCN2(_MASK, 2),
152 DDC_MASK_SH_LIST_DCN2(_MASK, 3),
153 DDC_MASK_SH_LIST_DCN2(_MASK, 4),
154 DDC_MASK_SH_LIST_DCN2(_MASK, 5),
155 DDC_MASK_SH_LIST_DCN2(_MASK, 6)
156 };
157
158 #include "../generic_regs.h"
159
160 /* set field name */
161 #define SF_GENERIC(reg_name, field_name, post_fix)\
162 .field_name = reg_name ## __ ## field_name ## post_fix
163
164 #define generic_regs(id) \
165 {\
166 GENERIC_REG_LIST(id)\
167 }
168
169 static const struct generic_registers generic_regs[] = {
170 generic_regs(A),
171 generic_regs(B),
172 };
173
174 static const struct generic_sh_mask generic_shift[] = {
175 GENERIC_MASK_SH_LIST(__SHIFT, A),
176 GENERIC_MASK_SH_LIST(__SHIFT, B),
177 };
178
179 static const struct generic_sh_mask generic_mask[] = {
180 GENERIC_MASK_SH_LIST(_MASK, A),
181 GENERIC_MASK_SH_LIST(_MASK, B),
182 };
183
define_ddc_registers(struct hw_gpio_pin * pin,uint32_t en)184 static void define_ddc_registers(
185 struct hw_gpio_pin *pin,
186 uint32_t en)
187 {
188 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
189
190 switch (pin->id) {
191 case GPIO_ID_DDC_DATA:
192 ddc->regs = &ddc_data_regs_dcn[en];
193 ddc->base.regs = &ddc_data_regs_dcn[en].gpio;
194 break;
195 case GPIO_ID_DDC_CLOCK:
196 ddc->regs = &ddc_clk_regs_dcn[en];
197 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;
198 break;
199 default:
200 ASSERT_CRITICAL(false);
201 return;
202 }
203
204 ddc->shifts = &ddc_shift[en];
205 ddc->masks = &ddc_mask[en];
206
207 }
208
define_hpd_registers(struct hw_gpio_pin * pin,uint32_t en)209 static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
210 {
211 struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
212
213 hpd->regs = &hpd_regs[en];
214 hpd->shifts = &hpd_shift;
215 hpd->masks = &hpd_mask;
216 hpd->base.regs = &hpd_regs[en].gpio;
217 }
218
define_generic_registers(struct hw_gpio_pin * pin,uint32_t en)219 static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
220 {
221 struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
222
223 generic->regs = &generic_regs[en];
224 generic->shifts = &generic_shift[en];
225 generic->masks = &generic_mask[en];
226 generic->base.regs = &generic_regs[en].gpio;
227 }
228
229 /* fucntion table */
230 static const struct hw_factory_funcs funcs = {
231 .init_ddc_data = dal_hw_ddc_init,
232 .init_generic = dal_hw_generic_init,
233 .init_hpd = dal_hw_hpd_init,
234 .get_ddc_pin = dal_hw_ddc_get_pin,
235 .get_hpd_pin = dal_hw_hpd_get_pin,
236 .get_generic_pin = dal_hw_generic_get_pin,
237 .define_hpd_registers = define_hpd_registers,
238 .define_ddc_registers = define_ddc_registers,
239 .define_generic_registers = define_generic_registers,
240 };
241 /*
242 * dal_hw_factory_dcn10_init
243 *
244 * @brief
245 * Initialize HW factory function pointers and pin info
246 *
247 * @param
248 * struct hw_factory *factory - [out] struct of function pointers
249 */
dal_hw_factory_dcn20_init(struct hw_factory * factory)250 void dal_hw_factory_dcn20_init(struct hw_factory *factory)
251 {
252 /*TODO check ASIC CAPs*/
253 factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
254 factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
255 factory->number_of_pins[GPIO_ID_GENERIC] = 4;
256 factory->number_of_pins[GPIO_ID_HPD] = 6;
257 factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28;
258 factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
259 factory->number_of_pins[GPIO_ID_SYNC] = 0;
260 factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/
261
262 factory->funcs = &funcs;
263 }
264
265