1 /* $NetBSD: amdgpu_hw_factory_dce120.c,v 1.2 2021/12/18 23:45:04 riastradh Exp $ */
2
3 /*
4 * Copyright 2013-15 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_hw_factory_dce120.c,v 1.2 2021/12/18 23:45:04 riastradh Exp $");
30
31 #include "dm_services.h"
32 #include "include/gpio_types.h"
33 #include "../hw_factory.h"
34
35 #include "../hw_gpio.h"
36 #include "../hw_ddc.h"
37 #include "../hw_hpd.h"
38 #include "../hw_generic.h"
39
40 #include "hw_factory_dce120.h"
41
42 #include "dce/dce_12_0_offset.h"
43 #include "dce/dce_12_0_sh_mask.h"
44 #include "soc15_hw_ip.h"
45 #include "vega10_ip_offset.h"
46
47 #define block HPD
48 #define reg_num 0
49
50 /* set field name */
51 #define SF_HPD(reg_name, field_name, post_fix)\
52 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
53
54 /* set field name */
55 #define SF_HPD(reg_name, field_name, post_fix)\
56 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
57
58 #define BASE_INNER(seg) \
59 DCE_BASE__INST0_SEG ## seg
60
61 /* compile time expand base address. */
62 #define BASE(seg) \
63 BASE_INNER(seg)
64
65 #define REG(reg_name)\
66 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
67
68 #define REGI(reg_name, block, id)\
69 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
70 mm ## block ## id ## _ ## reg_name
71
72
73 #include "reg_helper.h"
74 #include "../hpd_regs.h"
75
76 #define hpd_regs(id) \
77 {\
78 HPD_REG_LIST(id)\
79 }
80
81 static const struct hpd_registers hpd_regs[] = {
82 hpd_regs(0),
83 hpd_regs(1),
84 hpd_regs(2),
85 hpd_regs(3),
86 hpd_regs(4),
87 hpd_regs(5)
88 };
89
90 static const struct hpd_sh_mask hpd_shift = {
91 HPD_MASK_SH_LIST(__SHIFT)
92 };
93
94 static const struct hpd_sh_mask hpd_mask = {
95 HPD_MASK_SH_LIST(_MASK)
96 };
97
98 #include "../ddc_regs.h"
99
100 /* set field name */
101 #define SF_DDC(reg_name, field_name, post_fix)\
102 .field_name = reg_name ## __ ## field_name ## post_fix
103
104 static const struct ddc_registers ddc_data_regs[] = {
105 ddc_data_regs(1),
106 ddc_data_regs(2),
107 ddc_data_regs(3),
108 ddc_data_regs(4),
109 ddc_data_regs(5),
110 ddc_data_regs(6),
111 ddc_vga_data_regs,
112 ddc_i2c_data_regs
113 };
114
115 static const struct ddc_registers ddc_clk_regs[] = {
116 ddc_clk_regs(1),
117 ddc_clk_regs(2),
118 ddc_clk_regs(3),
119 ddc_clk_regs(4),
120 ddc_clk_regs(5),
121 ddc_clk_regs(6),
122 ddc_vga_clk_regs,
123 ddc_i2c_clk_regs
124 };
125
126 static const struct ddc_sh_mask ddc_shift = {
127 DDC_MASK_SH_LIST(__SHIFT)
128 };
129
130 static const struct ddc_sh_mask ddc_mask = {
131 DDC_MASK_SH_LIST(_MASK)
132 };
133
define_ddc_registers(struct hw_gpio_pin * pin,uint32_t en)134 static void define_ddc_registers(
135 struct hw_gpio_pin *pin,
136 uint32_t en)
137 {
138 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
139
140 switch (pin->id) {
141 case GPIO_ID_DDC_DATA:
142 ddc->regs = &ddc_data_regs[en];
143 ddc->base.regs = &ddc_data_regs[en].gpio;
144 break;
145 case GPIO_ID_DDC_CLOCK:
146 ddc->regs = &ddc_clk_regs[en];
147 ddc->base.regs = &ddc_clk_regs[en].gpio;
148 break;
149 default:
150 ASSERT_CRITICAL(false);
151 return;
152 }
153
154 ddc->shifts = &ddc_shift;
155 ddc->masks = &ddc_mask;
156
157 }
158
define_hpd_registers(struct hw_gpio_pin * pin,uint32_t en)159 static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
160 {
161 struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
162
163 hpd->regs = &hpd_regs[en];
164 hpd->shifts = &hpd_shift;
165 hpd->masks = &hpd_mask;
166 hpd->base.regs = &hpd_regs[en].gpio;
167 }
168
169
170 /* fucntion table */
171 static const struct hw_factory_funcs funcs = {
172 .init_ddc_data = dal_hw_ddc_init,
173 .init_generic = NULL,
174 .init_hpd = dal_hw_hpd_init,
175 .get_ddc_pin = dal_hw_ddc_get_pin,
176 .get_hpd_pin = dal_hw_hpd_get_pin,
177 .get_generic_pin = NULL,
178 .define_hpd_registers = define_hpd_registers,
179 .define_ddc_registers = define_ddc_registers
180 };
181 /*
182 * dal_hw_factory_dce120_init
183 *
184 * @brief
185 * Initialize HW factory function pointers and pin info
186 *
187 * @param
188 * struct hw_factory *factory - [out] struct of function pointers
189 */
dal_hw_factory_dce120_init(struct hw_factory * factory)190 void dal_hw_factory_dce120_init(struct hw_factory *factory)
191 {
192 /*TODO check ASIC CAPs*/
193 factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
194 factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
195 factory->number_of_pins[GPIO_ID_GENERIC] = 7;
196 factory->number_of_pins[GPIO_ID_HPD] = 6;
197 factory->number_of_pins[GPIO_ID_GPIO_PAD] = 31;
198 factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
199 factory->number_of_pins[GPIO_ID_SYNC] = 2;
200 factory->number_of_pins[GPIO_ID_GSL] = 4;
201
202 factory->funcs = &funcs;
203 }
204