1 /* $NetBSD: amdgpu_gfxhub_v2_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
2
3 /*
4 * Copyright 2019 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_gfxhub_v2_0.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
28
29 #include "amdgpu.h"
30 #include "gfxhub_v2_0.h"
31
32 #include "gc/gc_10_1_0_offset.h"
33 #include "gc/gc_10_1_0_sh_mask.h"
34 #include "gc/gc_10_1_0_default.h"
35 #include "navi10_enum.h"
36
37 #include "soc15_common.h"
38
gfxhub_v2_0_get_fb_location(struct amdgpu_device * adev)39 u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev)
40 {
41 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);
42
43 base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
44 base <<= 24;
45
46 return base;
47 }
48
gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device * adev)49 u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev)
50 {
51 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;
52 }
53
gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device * adev,uint32_t vmid,uint64_t page_table_base)54 void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
55 uint64_t page_table_base)
56 {
57 /* two registers distance between mmGCVM_CONTEXT0_* to mmGCVM_CONTEXT1_* */
58 int offset = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
59 - mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
60
61 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
62 offset * vmid, lower_32_bits(page_table_base));
63
64 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
65 offset * vmid, upper_32_bits(page_table_base));
66 }
67
gfxhub_v2_0_init_gart_aperture_regs(struct amdgpu_device * adev)68 static void gfxhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
69 {
70 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
71
72 gfxhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
73
74 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
75 (u32)(adev->gmc.gart_start >> 12));
76 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
77 (u32)(adev->gmc.gart_start >> 44));
78
79 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
80 (u32)(adev->gmc.gart_end >> 12));
81 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
82 (u32)(adev->gmc.gart_end >> 44));
83 }
84
gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device * adev)85 static void gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
86 {
87 uint64_t value;
88
89 /* Disable AGP. */
90 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0);
91 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0);
92 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF);
93
94 /* Program the system aperture low logical page number. */
95 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
96 adev->gmc.vram_start >> 18);
97 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
98 adev->gmc.vram_end >> 18);
99
100 /* Set default page address. */
101 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
102 + adev->vm_manager.vram_base_offset;
103 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
104 (u32)(value >> 12));
105 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
106 (u32)(value >> 44));
107
108 /* Program "protection fault". */
109 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
110 (u32)(adev->dummy_page_addr >> 12));
111 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
112 (u32)((u64)adev->dummy_page_addr >> 44));
113
114 WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,
115 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
116 }
117
118
gfxhub_v2_0_init_tlb_regs(struct amdgpu_device * adev)119 static void gfxhub_v2_0_init_tlb_regs(struct amdgpu_device *adev)
120 {
121 uint32_t tmp;
122
123 /* Setup TLB control */
124 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
125
126 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
127 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
128 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
129 ENABLE_ADVANCED_DRIVER_MODEL, 1);
130 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
131 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
132 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
133 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
134 MTYPE, MTYPE_UC); /* UC, uncached */
135
136 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
137 }
138
gfxhub_v2_0_init_cache_regs(struct amdgpu_device * adev)139 static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
140 {
141 uint32_t tmp;
142
143 /* Setup L2 cache */
144 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
145 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
146 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
147 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
148 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
149 /* XXX for emulation, Refer to closed source code.*/
150 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
151 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
152 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
153 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
154 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
155 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp);
156
157 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);
158 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
159 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
160 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
161
162 tmp = mmGCVM_L2_CNTL3_DEFAULT;
163 if (adev->gmc.translate_further) {
164 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
165 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
166 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
167 } else {
168 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
169 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
170 L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
171 }
172 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
173
174 tmp = mmGCVM_L2_CNTL4_DEFAULT;
175 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
176 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
177 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp);
178 }
179
gfxhub_v2_0_enable_system_domain(struct amdgpu_device * adev)180 static void gfxhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
181 {
182 uint32_t tmp;
183
184 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);
185 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
186 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
187 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
188 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
189 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp);
190 }
191
gfxhub_v2_0_disable_identity_aperture(struct amdgpu_device * adev)192 static void gfxhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
193 {
194 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
195 0xFFFFFFFF);
196 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
197 0x0000000F);
198
199 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
200 0);
201 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
202 0);
203
204 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
205 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
206
207 }
208
gfxhub_v2_0_setup_vmid_config(struct amdgpu_device * adev)209 static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
210 {
211 int i;
212 uint32_t tmp;
213
214 for (i = 0; i <= 14; i++) {
215 tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i);
216 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
217 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
218 adev->vm_manager.num_level);
219 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
220 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
221 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
222 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
223 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
224 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
225 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
226 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
227 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
228 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
229 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
230 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
231 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
232 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
233 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
234 PAGE_TABLE_BLOCK_SIZE,
235 adev->vm_manager.block_size - 9);
236 /* Send no-retry XNACK on fault to suppress VM fault storm. */
237 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
238 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
239 !amdgpu_noretry);
240 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i, tmp);
241 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
242 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
243 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,
244 lower_32_bits(adev->vm_manager.max_pfn - 1));
245 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
246 upper_32_bits(adev->vm_manager.max_pfn - 1));
247 }
248 }
249
gfxhub_v2_0_program_invalidation(struct amdgpu_device * adev)250 static void gfxhub_v2_0_program_invalidation(struct amdgpu_device *adev)
251 {
252 unsigned i;
253
254 for (i = 0 ; i < 18; ++i) {
255 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
256 2 * i, 0xffffffff);
257 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
258 2 * i, 0x1f);
259 }
260 }
261
gfxhub_v2_0_gart_enable(struct amdgpu_device * adev)262 int gfxhub_v2_0_gart_enable(struct amdgpu_device *adev)
263 {
264 if (amdgpu_sriov_vf(adev)) {
265 /*
266 * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
267 * VF copy registers so vbios post doesn't program them, for
268 * SRIOV driver need to program them
269 */
270 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE,
271 adev->gmc.vram_start >> 24);
272 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP,
273 adev->gmc.vram_end >> 24);
274 }
275
276 /* GART Enable. */
277 gfxhub_v2_0_init_gart_aperture_regs(adev);
278 gfxhub_v2_0_init_system_aperture_regs(adev);
279 gfxhub_v2_0_init_tlb_regs(adev);
280 gfxhub_v2_0_init_cache_regs(adev);
281
282 gfxhub_v2_0_enable_system_domain(adev);
283 gfxhub_v2_0_disable_identity_aperture(adev);
284 gfxhub_v2_0_setup_vmid_config(adev);
285 gfxhub_v2_0_program_invalidation(adev);
286
287 return 0;
288 }
289
gfxhub_v2_0_gart_disable(struct amdgpu_device * adev)290 void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev)
291 {
292 u32 tmp;
293 u32 i;
294
295 /* Disable all tables */
296 for (i = 0; i < 16; i++)
297 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i, 0);
298
299 /* Setup TLB control */
300 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
301 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
302 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
303 ENABLE_ADVANCED_DRIVER_MODEL, 0);
304 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
305
306 /* Setup L2 cache */
307 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
308 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);
309 }
310
311 /**
312 * gfxhub_v2_0_set_fault_enable_default - update GART/VM fault handling
313 *
314 * @adev: amdgpu_device pointer
315 * @value: true redirects VM faults to the default page
316 */
gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device * adev,bool value)317 void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev,
318 bool value)
319 {
320 u32 tmp;
321 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
322 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
323 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
324 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
325 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
326 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
327 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
328 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
329 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
330 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
331 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
332 value);
333 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
334 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
335 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
336 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
337 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
338 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
339 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
340 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
341 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
342 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
343 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
344 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
345 if (!value) {
346 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
347 CRASH_ON_NO_RETRY_FAULT, 1);
348 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
349 CRASH_ON_RETRY_FAULT, 1);
350 }
351 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
352 }
353
gfxhub_v2_0_init(struct amdgpu_device * adev)354 void gfxhub_v2_0_init(struct amdgpu_device *adev)
355 {
356 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
357
358 hub->ctx0_ptb_addr_lo32 =
359 SOC15_REG_OFFSET(GC, 0,
360 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
361 hub->ctx0_ptb_addr_hi32 =
362 SOC15_REG_OFFSET(GC, 0,
363 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
364 hub->vm_inv_eng0_sem =
365 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM);
366 hub->vm_inv_eng0_req =
367 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ);
368 hub->vm_inv_eng0_ack =
369 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK);
370 hub->vm_context0_cntl =
371 SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL);
372 hub->vm_l2_pro_fault_status =
373 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS);
374 hub->vm_l2_pro_fault_cntl =
375 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
376 }
377